JPH0226904B2 - - Google Patents

Description

[Detailed Description of the Invention] (a) Technical Field of the Invention The present invention relates to a multiprocessor system, and particularly relates to a multiprocessor communication control method that improves communication efficiency between processors via a common bus. .

(b) Technical background FIG. 1 is a diagram showing an example of a multiprocessor system to which the present invention is applied. In Figure 1, this multiprocessor system includes one management processor MPR and n processing processors with a capacity of n.
It consists of CPR. The management processor MPR and each processing processor CPR are connected to the common bus BUS via the communication control unit CCU, respectively.
They communicate with each other via the common bus BUS under the control of the bus control unit BCU. The bus control unit BCU is
In accordance with a predetermined order, each communication control unit CCU is inquired about the necessity of communication via the common bus BUS (hereinafter referred to as polling), and a response signal requesting communication is returned from the corresponding communication control unit CCU within a predetermined period. If the communication control unit CCU has a common bus
Grant the right to use the BUS.

(c) Prior Art and Problems FIG. 2 is a diagram showing an example of a conventional polling process in this type of multiprocessor system. The multiprocessor system has i processing processors (i<n) as shown in Fig. 1.
Only CPR is connected to the common bus via communication control unit CCU
Assume that it is connected to BUS. Even in such a case, a conventional bus control unit BCU polls n+1 communication control units CCU corresponding to the full capacity. i.e. bus control unit BCU
sequentially sends the device numbers CN=0 to n given to each communication control device CCU to the common bus BUS,
If a response signal requesting communication is returned within a predetermined period t, the communication control unit CCU assigned the device number CN that sent it is given the right to use the common bus BUS, and the communication control unit CCU Further polling will be stopped until communication via BUS is terminated. Also, after sending the device number CN, a predetermined period t
If a response signal requesting communication is not returned within that time, the communication control unit CCU assigned the sent device number CN determines that communication is not necessary and starts polling using the next device number CN. In this multiprocessor system, the device number
Communication control device assigned CN=i+1 to n
Since the CCUs are not connected to the common bus BUS, each bus control unit BCU spends a predetermined period t polling, even though a response signal requesting communication is naturally not returned.

As is clear from the above explanation, in the conventional multiprocessor communication control system, the bus control unit BCU always controls the capacity of the multiprocessor system, regardless of whether the communication control unit CCU is connected to the common bus BUS. For each corresponding n+1 communication control device CCU, a predetermined period t,
Polling takes a polling cycle T=(n+1)t, which has the disadvantage of reducing the usage efficiency of the common bus BUS.

(d) Purpose of the Invention The purpose of the present invention is to eliminate the drawbacks of the conventional multiprocessor communication control method as described above, and to connect to a common bus without making any major changes to the polling control function of the bus control device. The purpose of this invention is to rationalize the polling cycle according to the number of processors being used, and to improve the efficiency of use of the common bus.

(e) Structure of the Invention According to the present invention, a common bus to which a bus control device is connected at one end has a plurality of processing processors and one management processor that manages the status of these processing processors, each having a communication control device. Communication between each processor via the common bus is based on the right to use the common bus, which is granted to the communication control device that returns a response signal within a predetermined time when polling each communication control device. In a system based on the above, the bus control device is provided with a polling control circuit, a memory, a selection circuit, and a polling prohibition circuit, and the memory stores the device number and polling information of each communication control device given by the management processor via the selection circuit. The device number sent to the common bus from the polling control circuit during polling is also given to the memory via the selection circuit, and the memory stores the polling necessity information corresponding to the number to the polling prohibition circuit. the circuit continues the polling operation of the polling control circuit in the case of polling required information;
In the case of polling failure information, this is achieved by immediately stopping the polling operation for the device number.

In other words, the polling control circuit is designed to be able to perform sequential polling in accordance with the maximum number of communication control devices connected to the common bus, and in that case, if there is a communication control device that responds to polling, it The right to use the common bus is given to the device, and the next polling is interrupted while the device is communicating, and the polling control circuit has the function of changing the polling cycle in advance. However, in order to perform thinning of polling or change the position of thinning, it is necessary to make significant changes to the polling control circuit.

However, according to the present invention, a memory, a selection circuit, and a polling prohibition circuit are added to the bus control device, and the polling control circuit has a polling cycle change function that has been previously provided with only a slight modification. The number of processors connected to the common bus can be increased by continuing polling for all communication control devices that are not yet connected or whose functions have been interrupted, but by stopping the polling midway through. The polling cycle is rationalized accordingly, thereby reducing wasteful polling time and significantly increasing the efficiency of common bus usage.

(f) Embodiment of the invention An embodiment of the invention will be described below with reference to the drawings. FIG. 3 is a diagram showing a bus control device according to an embodiment of the present invention, and FIG. 4 is a diagram showing a polling process according to an embodiment of the present invention. In addition,
The same reference numerals indicate the same objects throughout the figures. The configuration of the target multiprocessor system is shown in FIG. In FIG. 3, the bus control unit BCU has polling necessity information ID indicating whether polling is necessary for each communication control unit CCU, which corresponds to the device number CN, in addition to the conventional polling control circuit PC and driver DV/receiver RV. A polling prohibition circuit JC is provided which controls the cancellation of polling in accordance with the polling necessity information ID outputted from the memory M. Prior to inter-processor communication, the management processor MPR sets the polling necessity information ID corresponding to the communication control units CCU(0) to CCU(i) connected to the common bus BUS to a logical value of 0, and connects the common bus BUS.
Communication control unit CCU (i+1) not connected to
Polling necessity information ID corresponding to CCU(n)
is set to a logical value of 1 and stored in advance in the memory M via the selection circuit SEL in the bus control unit BCU. In this state, the polling control circuit PC first drives the device number CN=0 and the synchronization signal SYN.
Send to the common bus BUS via DV. Note that the device number CN is also transmitted to the memory M via the selection circuit SEL. Memory M is the transmitted device number CN=
Outputs the polling necessity information ID of logical value 0 stored corresponding to 0, and outputs the polling prohibition circuit JC.
to communicate. Polling necessity information ID with logical value 0
The polling prohibition circuit JC that received the polling prohibition circuit JC does not transmit the polling discontinuation signal IH to the polling control circuit PC. As a result, the polling control circuit PC finishes polling the communication control unit CCU (0) when a predetermined period t has elapsed during which the response signal AS set to logical value 1 indicating a communication request is not returned from the communication control unit CCU (0). Then, it sends the device number CN=1 and the synchronization signal SYN to the common bus BUS, and starts polling the communication control device CCU(1).
This time as well, the memory M that received the device number CN = 1 transmits the polling necessity information ID set to a logical value of 0 to the polling prohibition circuit JC, and the polling prohibition circuit JC sends a polling stop signal IH to the polling control circuit PC. Don't communicate. After the polling control circuit PC finishes polling the communication control device CCU(i) in the same manner, the device number CN=i+
1 and a synchronization signal SYN to the common bus BUS to start polling for the communication control unit CCU (i+1), the polling necessity information ID set to the logical value 1 is output from the memory M, and the polling prohibition circuit JC is transmitted to. The polling prohibition circuit JC, which has received the polling necessity information ID having a logical value of 1, transmits a polling stop signal IH to the polling control circuit PC. The polling stop signal
Upon receiving the IH, the polling control circuit PC immediately sends the communication control unit CCU to the communication control unit CCU without waiting for the elapse of the predetermined period t.
Stop polling for (i+1) and send device number CN=i+2 and synchronization number SYN to the common bus.
It sends it to the BUS and shifts to polling for the communication control unit CCU (i+2). This time too, a polling necessity information ID with a logical value of 1 is output from memory M.
Polling prohibition circuit JC to polling control circuit
Since the polling stop signal IH is transmitted to the PC,
Polling control circuit PC immediately becomes communication control device
Shifts to polling for CCU (i+3).
As a result, as shown in Figure 4, the common bus BUS
The communication control units CCU(0) to CCU(i) connected to the common bus are polled for a predetermined period t as in FIG.
Communication control unit CCU (i+1) not connected to BUS
For CCU(n), polling is stopped for a short period t', and the total polling period T is much shorter than in FIG.

As is clear from the above description, according to the present embodiment, the bus control unit BCU spends the predetermined period t only on the communication control units CCU(0) to CCU(i) connected to the common bus BUS. polls the communication control device that is not connected to the common bus BUS.
Short term for CCU(i+1) to CCU(n)
In order to stop polling during t′, the polling period T is the communication control device connected to the common bus BUS.
It is optimally set according to the number of CCUs, and can be significantly shortened, especially when there are only a small number of connected communication control unit CCUs.

Note that FIGS. 1, 3, and 4 are merely examples of the present invention, and for example, the common bus BUS
The connection state of the communication control unit CCU to the processor is not limited to the one shown in the figure, and when the management processor MPR disconnects the processing processor CPR in which an abnormality has been detected from the common bus BUS, the polling necessity information ID is set to logical value 1. Although many other modifications may be considered, such as setting , the effect of the present invention does not change in any case.

(g) Effects of the Invention As described above, according to the present invention, it is possible to rationalize the interval for determining whether or not to communicate according to the number of processors connected to a common bus, and to improve the efficiency of use of the common bus. Become.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an example of a multiprocessor system to which the present invention is applied, FIG. 2 is a diagram showing an example of a conventional polling processing process, and FIG. 3 is a diagram showing a bus control device according to an embodiment of the present invention. It is a diagram showing
FIG. 4 is a diagram showing a polling process according to an embodiment of the present invention. In the figure, AS is a response signal, BCU is a bus control device, BUS is a common bus, CCU is a communication control device,
CN is the device number, CPR is the processing processor, DV is the driver, ID is the polling necessity information, IH is the polling stop signal, JC is the polling prohibition circuit, M
is a memory, MPR is a management processor, PC is a polling control circuit, RV is a receiver, SEL is a selection circuit, SYN is a synchronization signal, T is a period, and t is a period.

Claims (1)

[Claims] 1 A common bus to which a bus control device is connected at one end can be connected to a plurality of processing processors and one management processor that manages the states of these processing processors through communication control devices, respectively, and is connected to a common bus through the common bus. In a system in which communication between processors is performed based on a common bus usage right granted to a communication control device that returns a response signal within a predetermined time when the bus control device polls each communication control device, the bus control device is provided with a polling control circuit, a memory, a selection circuit, and a polling prohibition circuit, and the memory stores the device number and polling necessity information of each communication control device given by the management processor via the selection circuit, and stores the device number and polling necessity information given by the management processor via the selection circuit. The device number sent from the polling control circuit to the common bus is also given to the memory via the selection circuit, and the memory gives the polling necessity information corresponding to the number to the polling prohibition circuit, and when polling is necessary, the circuit 1. A multiprocessor communication control method, characterized in that the polling operation of a polling control circuit is continued, and when polling rejection information is received, the polling operation for the device number is immediately stopped.