JPH02268367A - Average value calculating circuit - Google Patents

Abstract

PURPOSE:To quickly calculate an average value by reducing the number of times of operation for the average value. CONSTITUTION:Data X1 to X4 are held in registers 2d to 2a 4t-number of seconds after the start of data supply from an input terminal 1. Data X5 is held in the terminal 1 then. At this time, a value X1+X2+X3+X4 is held in a register 6. Consequently, an adder 3 adds data X5 and X1+X2+X3+X4. Data outputted from the register 6 is inputted to a divider 7 and is divided by 4 and is outputted from an output terminal 8. Meanwhile, output data of the adder 3 is inputted to a subtractor 5, and output data X1 in a register 4 is subtracted, and the result X2+X3+X4+X5 is inputted to the register 6. After 5t-number of seconds, said value is outputted. This value is outputted from a terminal 8. This operation is repeated at intervals of t-number of seconds. By this constitution, the number of times of operation for the total sum of input data is reduced. This effect is increased according as N is larger.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an average value calculation circuit used to remove noise, drift noise, etc. contained in a digital signal.

2. Description of the Related Art Recently, image processing devices, audio processing devices, and the like have come to actively handle digital signals. In these devices, digital signal processing technology for removing noise, drift noise, etc. contained in data is an important point. As one of these digital signal processing techniques, a method of obtaining a moving average of time-series data is frequently used.

The moving average will be explained below using FIG. 2. Second
Figure (a) shows measurement data of a certain device. It can be assumed that this measurement data contains the noise component shown in FIG. 2(b) in the true data. In other words, the measured data is the true data plus the noise component.

The moving average is used to estimate true data from measurement data that includes noise components. In this method, the average value of N pieces of adjacent measurement data is determined as a measurement result.

In the example shown in FIG. 2, the average value of three adjacent pieces of data is calculated.

That is, Y, = 1/3 (X, +X2 + X3) Y2 =: 1 /3 (Xl + X3 + X4)
Y3” 1/3 (Xs + X4 + X5)Y(
1= 1 /3 (Xn + Xn+t + Xn+2
) Figure 2 (C) shows the result of moving the three pieces of measurement data one after another as described above and finding their average value.

Next, a case will be described in which drift noise is removed from measurement data to estimate true data.

In this case, a larger number of data are extracted for calculating the average value than in the case of noise removal described above.

For example, the average value of 11 adjacent measurement data is calculated, and this average value is subtracted from the original measurement data to remove drift noise.

That is, Yn ==Yn - (1/11 (Xn-5+ Xn-a + Xn-3+ Xl-2+
Xn-t + Xn ++ Xn+1 + Xn+
2 + Xn+3+Xn+4 + Xn+s)).

As explained above, average values are frequently calculated in digital signal processing, and therefore a high-speed average value calculation circuit is desired.

Hereinafter, a conventional average value calculation circuit will be explained using FIG. 3. Note that, for the sake of simplicity, FIG. 3 describes an example in which the average value of four pieces of data is calculated.

In FIG. 3, 1 is a data input terminal, 2a, 2b,
2c is a register that delays input data by t seconds, and 4at 4bs 4c are registers 2a and 2b.

an adder for calculating the sum of data output from 2c, 7
is a 1/4 divider for calculating the average value, and 8 is an output terminal.

The operation shown in FIG. 3 will be explained below. First, let input data be Xl, Xl, Xs, X4, X5, . . . . These data are supplied from input terminal 1 at intervals of t seconds. Therefore, when 3 is the sand diameter, data of X 11X 2 and Xs are held in the registers 2c and 2bs 2a, respectively.

Further, data of X4 is supplied to the input terminal 1.

Next, register 2c.

The data of Xl, Xl, Xs output from 2b, 2a and the data of X4 supplied from input terminal 1 are added to adder 3a,
3b and is added. Furthermore, the data (X4+X3) output from the adder 3a and the data (Xl+Xs) output from the adder 3b are input to the adder 3c and are added together. That is, this adder 3c adds 4
The sum of the data is calculated. The data output from the adder 3c is input to the division booklet, where the calculation of 1/4 is performed.

That is, the average value is calculated here. The data output from the divider 7 is output from the output terminal 8.

The above is an explanation of the operation in FIG.

Next, using the conventional average value calculation circuit using FIG.
A method for calculating the average value of one piece of data will be explained.

In FIG. 4, 1 is a data input terminal, and 2a.

2b12c, 2ds 2e, 2fs 2gs 2h, 2
is2j are registers 3a, 3b, 3c, 3d, 3e, 3f, and 3g that delay input data by t seconds.

3h, 3i s 3j are registers 2a, 2b,
`` `` `` 21. An adder that calculates the sum of the data output from 2j, 7 is a 1/11 divider that calculates the average value, and 8 is an output terminal. The number of registers and adders in Figure 3 is expanded to calculate 11 average values, and the operation in Figure 4 is the same as that in Figure 3, so the operation explanation is as follows. Omitted.

Problems to be Solved by the Invention However, in the conventional configuration as described above, the number of calculations increases when calculating the sum of input data. Therefore, there was a problem that the calculation speed was also slow. This means that when calculating the average value for N input data, N should not be a big problem! The more noticeable it becomes.

An object of the present invention is to calculate the average value quickly by reducing the number of calculations when calculating the average value.

Means for Solving the Problems In order to achieve the above object, the technical solution of the present invention is as follows:
The first one delays the input digital signal by the time T.
selecting means for connecting a plurality of delay means in series, selecting one of the outputs of each of the first delay means connected in series; and selecting one of the outputs of the first delay means connected in series; an addition means for calculating the sum of N pieces of data before the data; a subtraction means for subtracting the N pieces of data before the data of interest selected by the selection means from the sum; a second delay means for delaying the sum of data from the data immediately before the data of interest to N data before the data of interest by a time T; It is equipped with a calculation means.

Effects In the present invention, since the number of calculations is fixed without depending on N when calculating the average value for N pieces of input data, the number of calculations and the calculation speed can be reduced.

Embodiment Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a first embodiment of the present invention. Note that, for the sake of simplicity, FIG. 1 shows an example in which the average value of four pieces of data is calculated.

In FIG. 1, 1 is a data input terminal, 2a, 2b,
2c, 2d, 2e12f, 2g, 2h, 2is2j, 2
3 is a register that delays input data by seconds; 3 is an adder that adds data supplied from input terminal 1 and data output from register 6, which will be described later; 4 is register 2a, 2b.

2cs 2d, 2es 2fq 2g, 2h, 2
i12j.

The input terminal 4a is a selector that selects one of the data output from each of the input terminals 2k and 2k.

4b, 4c, 4d, 4e s 4r, 4gl
4h, 4+s4J, and 4 have an output terminal 40 and a selection control terminal 41. 6 is a subtracter that subtracts the output data of selector 4 from the data output from adder 3, and 6 is a register that holds the result output from subtracter 5, similar to registers 2a and 2bq - -12Js2. , the output data is delayed by t seconds with respect to the input data. 7 is a 1/n divider for calculating the average value, and has a control terminal 71. 8 is an output terminal.

The operation of the above configuration will be described below. First of all, registers 2a, 2b, 2cs 2d,
2e, 2fs 2g, 2h, 2js2 and register 6 are cleared to 0°. Also, selector 4 is configured so that output terminal 4o selects input terminal 4d based on the data input to selection control terminal 41. Also, the divider 7 is set to 1 by the data input from the control terminal 71.
/4 calculation is performed.

In the above state, data is input from input terminal 1 at intervals of t seconds. The input data is X4, X2, X3, X4,
Let it be X5,...

41 seconds after data starts being supplied from input terminal 1, Xl s is input to registers 2d, 2c, 2b, and 2a, respectively.
Data of X2, X3, and X4 is held.

Further, data of X5 is supplied to input terminal 1.

At this time, register e contains registers 2a and 2b in advance.
Since s2cs2d and register θ were cleared to "0", the value of (Xl+X2+X3+X4) is held. Therefore, the adder 3 adds the data of X5 supplied from the input terminal 1 and the data (XI+X2 +'X3 +X4) output from the register 6. That is, the result of adder 3 is (XI +X2 + X
3 + X4 + X5). In addition, register 6
The data (X1+X2+X3+X4) outputted from the divider 7 is inputted to the divider 7, divided into 1/4, and outputted from the output terminal 8. On the other hand, the data output from the adder 3 is transferred to the subtracter 6.
is input. The subtracter 6 subtracts the output data X1 of the selector 4 from the data output from the adder 3. That is,
The result of the subtracter 6 is (Xz +x3 +X4+Xs), which is input to the register 6.

Next, when 5 seconds have passed since data began to be supplied from input terminal 1, register 6 outputs (Xz + X3 + X4 +
The value of X5) is output. This value is input to the divider 7, divided into 1/4, and outputted from the output terminal 8. On the other hand, data of X6 is supplied from input terminal 1, and adder 3
adds this data of X6 and the data output from register 6 (Xz + X3 + X4 + X5). That is, the result of adder 3 is (Xz +x3 +x4 +X5
+X6). The data output from the adder 3 is input to the subtracter 5. The subtracter 6 subtracts the output data X2 of the selector 4 from the data output from the adder 3. In other words, the result of subtractor 6 is (X3+X4+X5+X6)
becomes. The result of this subtracter 6 is input to register e,
After a second, the divider 7 divides the value into 1/4 and calculates the average value. This result is output from the output terminal 8. The above operation is repeated at intervals of t seconds.

That is, FIG. 1 is a circuit implementation of equation (3) shown below.

First, the average values Y1, Yl, Y3, and Yn are defined as follows.

Yl: 1/4< X+ +X2 +X3 +X4)
Yl =1 /4 (Xz +X3 +X4 +Xs
)Y3=1/4 (X3 +x4+X5 +X5)Yn
=1/4 (Xn +Xn+1 +Xn+2 +Xn-
+-3)・・・・・・・・・(1) Here, if P1=(X1+X2+X3+X4), then P2=(X2+X3+X4+X5) =p, +x5-x.

P3 = P2 + 4Pn'・
......(3).

That is, the register 6 in FIG. 1 holds Pr+ in equation (2), and the adder 3 holds Pr+ in equation (2).
Pn-+ + Xn+3), and the subtracter 6 calculates Pn in equation (2).

The method for calculating the average value of the four pieces of data has been described above.

In addition, in order to calculate the average value of 11 data, the output terminal 4o of the selector 4 shown in FIG. /11 calculation may be performed.

In addition, in FIG. 1, the output data of the selector 4 is subtracted from the result of the adder 3, but after subtracting the output data of the selector 4 from the data output from the register 6, the input terminal 1
You may add data input from . That is, in the above formula (2), (pn-1-XH-1) + X1
It may be set to +3.

Similarly, after subtracting the output data of the selector 4 from the data input from the input terminal 1, the data output from the register 6 may be added. That is, in the above equation (2), (Xn+3-Xn-t) +Pn-1 may be used.

Furthermore, when calculating the average value of eight pieces of input data, it is clear that the selector 4 may be omitted if N is fixed.

As described above, according to this embodiment, the number of calculations required to calculate the sum of input data can be reduced compared to the conventional example.

For example, when calculating the average value of 11 input data, in the conventional example, addition must be performed 10 times as shown in FIG. In contrast, in the present invention, only two additions and subtractions are required. Therefore, the present invention can increase the calculation speed. Note that this effect becomes more pronounced as N becomes larger when calculating the average value for N pieces of input data.

Effects of the Invention As described above, the present invention has great effects because the number of calculations needed to calculate the sum of input data is smaller than in the conventional example, and as a result, the calculation speed can be increased.

Note that this effect becomes more pronounced as N becomes larger when calculating the average value for N pieces of input data.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an average value calculation circuit according to an embodiment of the present invention, FIG. 2 is a diagram for explaining a moving average, and FIGS. 3 and 4 are conventional average value calculation circuits. . 1... Input terminal, 2a, 2b, 2c, 2d,
2es 2f. 2g, 2h, 2i, 2j, 2k... register, 3...
・Adder, 4...Selector, 4a, 4b, 4c, 4d
, 4e, 4f. 4 g, 4 h 1'! s' J, 4k...
- Input terminal of selector, 40... Output terminal of selector, 41... Selection control terminal, 5... Subtractor, θ...
Register, 7... Divider, 71... Control terminal, 8.
...Output terminal. Name of agent: Patent attorney Shigetaka Awano and 1 other personQ

Claims (1)

[Claims] The first one delays the input digital signal by the time T.
selecting means for connecting a plurality of delay means in series and selecting one of the outputs of each of the first delay means connected in series; an addition means for calculating the sum of N data before the data; a subtraction means for subtracting only the N data before the data selected by the selection means from the sum; a second delay means for delaying the sum of the data from the data immediately before the data of interest to N pieces of data before the data of interest by a time T during calculation;
and a dividing means for calculating an average value by dividing the total sum result outputted from the second delay means to 1/N.