JPH0226835B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to television equipment, and in particular realizes a system with a relatively simple configuration that is convenient for use in measurements, measurement, etc. without reducing vertical resolution.

Test equipment has been developed that combines television systems with measurement and checking equipment. Typically, the television system used in conjunction with such devices is of a standard format (525 horizontal scanning lines in the case of the NTST format). However, with this standard method, the vertical resolution is sometimes insufficient, and it is desired to improve the vertical resolution, especially for purposes such as measurement. In the past, in order to meet these demands, it was necessary to lower the vertical scanning frequency of both the television imaging device and the video signal monitor to create a new television system that differed from the standard system. . However, creating such a non-standard system is very expensive, and the low vertical scanning frequency causes flickering on the screen, making it tiring to monitor the monitor.

Therefore, on the imaging side, the present invention increases the number of horizontal scanning lines within one vertical period by lowering the vertical scanning frequency of the standard video signal.
It is an object of the present invention to provide a television device that can easily obtain an enlarged image by extracting the number of horizontal scanning lines of a normal standard method on the monitor side.

Embodiments of the present invention will be described below with reference to the drawings. Figure 1 shows the system configuration of this device.
Reference numeral 1 denotes an image pickup device, which includes an image pickup tube 12, a video amplification circuit 13, a vertical deflection circuit 14, a horizontal deflection circuit 15, and the like. The output video signal of the resolution tube 12 is amplified by the video amplification circuit 13 and output to the measurement video output terminal 16 as well as to the gate circuit 17 . The measurement video signal is used, for example, in a measurement device such as a pattern recognition device. Measurements include, for example, measuring the interval between printed patterns on a printed wiring board and checking parts.

The gate circuit 17, together with a video selection switch 18 provided therein, generates a normal standard video signal from the modified video signal, and one of the standard video signals.
The field portion is supplied to the field memory 19. The standard video signal read from the field memory 19 is input to the monitor 21 via one input terminal (X ₁ ) of the mode switch 20.
Further, the output video signal from the video amplification circuit 13 can also be directly supplied to the monitor 21 via the other input terminal (Y ₁ ) of the switch 20.

Reference numeral 22 denotes a synchronization signal generation circuit, which generates a synchronization signal including a vertical synchronization signal (VD) and a horizontal synchronization signal (HD) of standard frequency, and supplies this to the monitor 21.

Further, the vertical synchronizing signal (VD) is also applied to the 1/N frequency divider circuit 23, and the horizontal synchronizing signal (HD) is also input to the horizontal deflection circuit 15. The vertical synchronizing signal (1/NVD) frequency-divided by the frequency dividing circuit 23 is input to the vertical deflection circuit 14 via the first input terminal (X ₂ ) of the mode switch 24. The mode switch 24 can also directly introduce the vertical synchronization signal (VD) into the vertical deflection circuit 14 via the second input terminal (Y ₂ ). Further, the vertical synchronizing signal (VD) and the second vertical synchronizing signal (1/NVD) obtained by frequency-dividing the vertical synchronizing signal (VD) are also input to the gate circuit 17. In this case, the delay amount of the second vertical synchronizing signal 1/NVD is set by the video selection switch 18, and the gate timing of the gate circuit 17 is determined.

One embodiment of the present invention is constructed as described above, and its operation will now be described with reference to the time chart of FIG. Now mode switch 20, 24
are respectively switched to the input terminal (X ₁ ) (X ₂ ) side. In this switch state, the vertical scanning frequency of the image pickup tube 12 is 1/N lower than the frequency of the standard system.
Therefore, as shown in FIG. 2a, the imaging-side video signal output from the video amplification circuit 13 has one field period (VT ₁ ) equal to one vertical (one field) period (VT _{2 )} on the monitor side. ) is now N times larger.

Figure 2b shows the imaging side vertical synchronization signal (1/NVD), and Figure 2c shows the monitor side vertical synchronization signal (VD). As a result, a large number of horizontal scanning lines (5 times the normal number in this embodiment) are inserted into one vertical period (VT ₁ ) on the imaging side, resulting in good vertical resolution.

Next, if the above modified video signal is supplied as is to the standard monitor 21, synchronization cannot be obtained, so the gate circuit 17 converts the video signal for 525 horizontal scanning lines, that is, the monitor side video signal. This is stored in the field memory 19.

In the gate circuit 17, the monitor side vertical synchronization signal (VD) and the imaging side vertical synchronization signal (1/NVD)
In synchronization with , a gate signal (G ₁ ) as shown in FIG. 2d is generated. Therefore, the gate circuit 17
A video signal (B) as shown in FIG. 2e is extracted from the output of the field memory 19.
is stored in Update in field memory 19,
Data rewriting is performed once in one field period of the modified video signal (A).

Therefore, on the monitor 21 side, as shown in FIG. 2f, the video signal for one field in the field memory 19 is normally read out and displayed repeatedly in synchronization with the standard method. This interpolates periods where there is no video signal and eliminates flicker. Note that if flicker is acceptable, the field memory 19 is not necessary, and the output of the gate circuit 17 may be directly supplied to the monitor 21.

In the above configuration, if N of the 1/N frequency divider circuit 23 is selected as a parsimal, the video signal on the imaging side has an interlaced relationship as in the standard system. Therefore, the output video signal of the gate circuit 17 is also interlaced. In this case, an interlaced image can be obtained on the monitor 21 by using a frame memory instead of the field memory 19 and recording the first field and the second field alternately.

Here, a part of the modified video signal (A) is displayed on the monitor 21 as a standard video signal, but if you want to change the display (monitoring) position,
The switch 18 is adjusted to change the timing of generation of the gate signal (G ₁ ) shown in FIG. 2d.

Next, when the mode switches 20 and 24 are respectively switched to the input terminal (Y ₁ ) (Y ₂ ) side, the gate circuit 17 and the frequency dividing circuit 23 are disconnected. Therefore, the frequency of the synchronization signal on both the imaging side and the monitor side is the same standard method, and the entire field of view of the image pickup tube 12 can be viewed on the monitor 21. While looking at the entire image here, if you find a part you want to enlarge, change the switch 18 to adjust the gate signal generation timing, and then switch the switches 20 and 24 to display the enlarged image of that part on the entire screen of the monitor 21. can be viewed without reducing vertical resolution.

As described above, according to the device of the present invention, the gate circuit 17, the switch 18, and the field memory 1
9. By simply providing the frequency dividing circuit 23, switches 20, 24, etc., there is no need to remanufacture the entire system in a manner different from the standard system as in the past, and monitoring can be performed with a simple configuration without deterioration.

As explained above, the present invention increases the number of horizontal scanning lines within one vertical period by lowering the vertical scanning frequency of a standard video signal on the imaging side, and increases the number of horizontal scanning lines within one vertical period on the imaging side. It is possible to provide a television device that can easily obtain an enlarged image by extracting the number of standard horizontal scanning lines.

[Brief explanation of drawings]

FIG. 1 is a configuration explanatory diagram showing one embodiment of the present invention, and FIGS. 2 a to 2 f are operating signal waveform diagrams shown to explain the operation of the apparatus of FIG. 1. DESCRIPTION OF SYMBOLS 11...Imaging device, 17...Gate circuit, 18...Video selection switch, 19...Field memory, 2
0, 24...Mode switch, 21...Monitor, 23
...Frequency divider circuit.

Claims (1)

[Claims] 1. Frequency dividing means for dividing the frequency of the vertical synchronizing signal used in the monitor section using a frequency dividing circuit; In addition to the circuit, means for synchronizing only the vertical frequency of the imaging unit with the second vertical synchronization signal to increase the number of horizontal scans in one field; gate means for extracting a video signal for a scanning line that can be displayed on the monitor unit, and for changing a vertical region to be extracted in the video signal on the imaging side during extraction; What is claimed is: 1. A television device comprising: storage means for storing a video signal for a screen and repeatedly supplying the video signal to the monitor unit.