JPH02267650A - Semiconductor storage device - Google Patents
Semiconductor storage deviceInfo
- Publication number
- JPH02267650A JPH02267650A JP1089350A JP8935089A JPH02267650A JP H02267650 A JPH02267650 A JP H02267650A JP 1089350 A JP1089350 A JP 1089350A JP 8935089 A JP8935089 A JP 8935089A JP H02267650 A JPH02267650 A JP H02267650A
- Authority
- JP
- Japan
- Prior art keywords
- check sum
- sum value
- data
- memory
- storage device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 29
- 238000012360 testing method Methods 0.000 abstract description 8
- 238000010586 diagram Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000000034 method Methods 0.000 description 3
Landscapes
- Techniques For Improving Reliability Of Storages (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、半導体記憶装置の構成に関するものである
。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to the structure of a semiconductor memory device.
翅51閾、第6図に従来の半導体記憶装置の畜き込み、
およびdみdし時におけるデータの流れを示すブロック
図である。Wing 51 threshold, Figure 6 shows the conventional semiconductor memory device,
FIG. 3 is a block diagram showing the flow of data when the data is read and read.
次に動作について説明する。舊き込み時は。Next, the operation will be explained. At the time of planting.
第5図のように、半導体記憶4&置12)のメモ17(
2a)内のデータを半1体記憶装置)11のメモリセル
C1a)icilき込むも書き込み終了時、半導体試験
g @ !21の演算器(jl!b)で計算されたチエ
ツクサム値をCRT(2&)などに表示し、それを作業
者・3:が読み取り、記録媒体141に記録する。読み
出し時は、半導体記憶!! 1111+からデータを読
み出すと同時に、半導体試験装置(!Iの演算器(g’
b)にデータを送り、チエツクサム値(叱和値)を計算
する。読み出し終了時に計算C!RTli)に表示さね
たチエツクサム値と以前記憶媒体141に記録したチエ
ツクサム値を作業者131が比較して、一致すればrO
KJとし、不一致であればrNGJとしていた。As shown in Figure 5, the memo 17 (
2a) The data in the semi-synthetic storage device) 11 memory cell C1a) icil is written, but when the writing is completed, the semiconductor test g @! The checksum value calculated by the arithmetic unit 21 (jl!b) is displayed on a CRT (2&) or the like, and the worker 3 reads it and records it on the recording medium 141. Semiconductor memory when reading! ! At the same time as reading data from the 1111+, the arithmetic unit (g'
Send the data to b) and calculate the checksum value. Calculate C at the end of reading! The operator 131 compares the checksum value displayed on the RTli) with the checksum value previously recorded on the storage medium 141, and if they match, the rO
It was set as KJ, and if there was a discrepancy, it was set as rNGJ.
従来の半導体記憶装置は、作業者がチエツクサム値を&
i録、比較9判定しなければならず、作業者の介入が必
要で、また、チエツクサム1直の記録?保存する必要力
;あるなどの問題があった〇
この発明は、上記のような問題点を解消するためになさ
れたもので、作業者の介入無しで、チエツクサム値の判
定ができ、チエツクサム値の外部への記録も不要とする
半導体記憶装置を得ることを目的とする。In conventional semiconductor storage devices, an operator must check the checksum value &
I record, comparison 9 judgments have to be made, operator intervention is required, and checksum 1st shift record? This invention was made to solve the above-mentioned problems, and it is possible to determine the checksum value without operator intervention. The object of the present invention is to obtain a semiconductor memory device that does not require external recording.
この発明に係る半導体記憶装#Lけ通常のメモリセル以
外にチエツクサム値を記録するためのメモリセルを有し
、それに対しての書き込み及び読み出し全可能てしたも
のである。The semiconductor memory device #L according to the present invention has a memory cell for recording a checksum value in addition to the normal memory cells, and is capable of writing and reading from and to the memory cell.
この発明における半導体記憶装置は、チエツクサム値の
記録及びチエツクサム値による判定を作業者の介入無し
で、実行することができる。The semiconductor memory device according to the present invention can record checksum values and perform judgment based on checksum values without operator intervention.
〔実施−1〕
以下、この発明の一実施例を図について説明でる。第1
図ないし第4図は半導体記憶装置へのデータの書き込み
あるいは読み出しを行う場OK、半導体記憶装置及び半
導体試験装置の構成を示すブロック図で、第1図はデー
タの書き込み時のデータの流れ、第8図はデータの書き
込み時のチエツクサム値の書き込み方法、第3図にデー
タの絖み出し時のデータの流れ、第4図はデータの続み
出し時のチエツクサム値の読み出し方法を示す。図にお
いて+Il 、 rla)、 121 。[Embodiment-1] Hereinafter, one embodiment of the present invention will be explained with reference to the drawings. 1st
4 through 4 are block diagrams showing the configuration of a semiconductor memory device and a semiconductor testing device, which are suitable for writing or reading data into a semiconductor memory device. FIG. 8 shows a method for writing a checksum value when writing data, FIG. 3 shows a data flow when starting data, and FIG. 4 shows a method for reading a checksum value when starting data. In the figure +Il, rla), 121.
’ 2 a ) T ’ 2 b )は第5図の従来例
に示したものと同等であるので説明を省略する。(1)
flチエツクサム記録用メモリ、(20)は比較器であ
る。' 2 a ) T ' 2 b ) are the same as those shown in the conventional example of FIG. 5, so their explanation will be omitted. (1)
fl checksum recording memory; (20) is a comparator;
次に動作について説明する。データの畜き込み時は、第
1図のように半導体試験装置〔2!のメモ+7(fa)
内にあるデータを半導体記憶装置Il+のメモリセル(
1a)に書き込む。誓き込み終了時、半導体試験装置(
2)の演算器(2b)で、計算されたチエツクサム値を
、半導体記憶装置ll:Ilのチエツクサム値記録用メ
モI) (xb)に賽き込む。読み出し時には、半導体
記憶装置(11力・らデータを読み出すと同時に、半導
体試験装置・′llの演算器(2b)に、データを送り
、チエツクサム値を計算する。Next, the operation will be explained. When storing data, use the semiconductor test equipment [2!] as shown in Figure 1. Memo +7 (fa)
The data in the memory cell of the semiconductor storage device Il+ (
Write in 1a). At the end of the pledge, semiconductor testing equipment (
The arithmetic unit (2b) of step 2) puts the calculated checksum value into the checksum value recording memo I) (xb) of the semiconductor storage device ll:Il. At the time of reading, data is read from the semiconductor memory device (11) and at the same time, the data is sent to the arithmetic unit (2b) of the semiconductor testing device (2b) to calculate a checksum value.
絖み出し終了時に、計算されたチエツクサム値と以前に
半導体記憶装置…のチエツクサム値記録用メモリrib
)iで薔き込んだチエツクサム値を比較器r2c)tで
より比較して、一致すれげrGOJとし、不一致であれ
ばrNGJとする。When the start-up is completed, the calculated checksum value and the checksum value recording memory rib stored in the semiconductor storage device are stored.
) The checksum values set in i are compared by comparators r2c)t, and if they match, it is set as rGOJ, and if they do not match, it is set as rNGJ.
以上のように、この発明によれば半導体記憶装置にチエ
ツクサム値記録用メモリを設け、チエツクサム値の書き
込み及び読み出しができるように構成したので、チエツ
クサム値の記録及びチエツクサム値による判定を作業者
の介入なしで行うことk o’J能とする半導体記憶装
置を得られる効果がある。As described above, according to the present invention, a semiconductor memory device is provided with a memory for recording checksum values, and is configured to be able to write and read checksum values, so that recording of checksum values and judgments based on checksum values can be performed without the operator's intervention. This has the effect of providing a semiconductor memory device with high k o'J performance.
第1図ないし第4図はこの発明の一実施例による半導体
記憶装置へのデータの書き込み、あるいは読み出しを行
う場合に半導体試験装置及で、第5図にデータの書き込
み時のデータの流れを示す図、第6図はデータの読み出
し時のデータの流れを示す図である。
図において、+11 V′1半導体記憶fe(1M、
(la)iメモリセル、(1b)はチエツクサム記録用
メモリ、21は半導体試験装置、 r2a)はメモリ
、rgb)は演算器、(2C社比較器である。
なお、図中、同一符号は同一 又は相当部分?不す〇Figures 1 to 4 show a semiconductor test device used when writing or reading data to a semiconductor memory device according to an embodiment of the present invention, and Figure 5 shows the flow of data when writing data. FIG. 6 is a diagram showing the flow of data when reading data. In the figure, +11 V'1 semiconductor memory fe (1M,
(la) i memory cell, (1b) memory for checksum recording, 21 semiconductor test equipment, r2a) memory, rgb) arithmetic unit, (2C company comparator). Note that the same reference numerals in the figure are the same. Or a considerable portion? Not 〇
Claims (1)
メモリセルを備えたことを特徴とする半導体記憶装置。A semiconductor memory device comprising a memory cell for recording a total value of data for each address of the semiconductor memory device.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1089350A JPH02267650A (en) | 1989-04-07 | 1989-04-07 | Semiconductor storage device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1089350A JPH02267650A (en) | 1989-04-07 | 1989-04-07 | Semiconductor storage device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH02267650A true JPH02267650A (en) | 1990-11-01 |
Family
ID=13968261
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1089350A Pending JPH02267650A (en) | 1989-04-07 | 1989-04-07 | Semiconductor storage device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH02267650A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5590134A (en) * | 1990-06-27 | 1996-12-31 | Texas Instruments Incorporated | Test circuits and method for integrated circuit having memory and non-memory circuits by accumulating bits of a particular logic state |
-
1989
- 1989-04-07 JP JP1089350A patent/JPH02267650A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5590134A (en) * | 1990-06-27 | 1996-12-31 | Texas Instruments Incorporated | Test circuits and method for integrated circuit having memory and non-memory circuits by accumulating bits of a particular logic state |
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