JPH02262734A - Channel separating device - Google Patents

Abstract

PURPOSE:To realize the miniaturization of a device and the simplification of a channel separation processing which perform the separation and the demodulation of a channel by using a multiplier that is one of constituents provided at every channel and a memory commonly to each channel. CONSTITUTION:A reception signal is inputted to the multipliers 1 and 2, and the output of an in-phase component and that of an orthogonal component can be obtained, and they are A/D-converted by A/D converters 7 and 8, then, inputted to the multipliers 9 and 10, and the multipliers 11 and 12, respectively. The output of the multipliers 9 and 11 are subtracted by a subtractor 15, and that of the multipliers 10 and 12 are added by an adder 13, and only low frequency band areas are outputted by low-pass filters 20 and 21, then, the in-phase component 1 and the orthogonal component 2 can be obtained. Similarly, the output of the multipliers 10 and 12 are subtracted by a subtractor 14, and that of the multipliers 9 and 11 are added by an adder 16, then, the in-phase component 3 and the orthogonal component 4 can be obtained via low-pass filters 22 and 23.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention relates to a channel separation device used for demodulation when performing frequency division multiplex communication.

(Prior Art) In frequency division multiplex communication, the amount of information that can be transmitted through one channel is limited due to band limitations and other reasons. However, in recent years, opportunities to transmit information exceeding the bandwidth of one channel have increased. When it is necessary to transmit data larger than the capacity of one channel, a system is used that receives multiple channels in a mixed manner and uses each channel separately. ing. FIG. 4 shows an example of a device for converting a plurality of transmitted channels into baseband signals of each channel and separating the channels, taking the case of two channels as an example. First, received signals transmitted through two channels whose center frequencies are f and f are input to two multipliers 30 and 33. The multiplier 30 converts the frequency to the baseband by the local oscillator 31, while the multiplier 33 uses the signal from the local oscillator 31 to be phase-shifted by π/2 through the phase shifter 32. Frequency converted. That is, the outputs of the multipliers 30 and 33 have a phase shift of π/2 from each other. The outputs of multipliers 30 and 33 are passed through low-pass filters 3i and 35, respectively.
is input and only low frequency components are output. The output low frequency components are input to human converters 36 and 37, respectively, and the analog values are converted into digital values. The two outputs of the AD converters 36 and 37 are input to both a channel 1 processing section and a channel 2 processing section that respectively process two channels. The channel 1 processing section and the channel 2 processing section perform similar processing, respectively, and separate and demodulate the channel 1 signal and the channel 2 signal. First, the channel 1 processing section will be explained. It is assumed that the center frequency of each channel is also known in advance on the side that demodulates the received signal. Using this center frequency, the integrator 46
The signal from the AD converter 36 is input to multipliers 38 and 39. On the other hand, the signal of the AD converter 37 is multiplied by f,, -
f is input to the unit 40.41. Each time 2π-t and tg are inputted, the same value is cumulatively added, and the cumulatively added value is outputted next time, which is a repeated operation. The output of this integrator 46 is stored in the ROM 4 in which the sine waveform is stored.
2. The cos waveform is input to the ROM43 where it is stored, and the sine waveform and CO5 are input from the ROM42 and ROM43, respectively.
The sample value of the waveform is output.

Next, this sample value is transferred to the multiplier 38, 39°40.4
1 is input. As a result, the multipliers 38, 39, 40
t41 performs multiplication, and the outputs of the multipliers 39 and 40 are input to an adder 44 and added. Also, multiplier 3
The output of 8.41 is input to a subtracter 45° and subtracted. The output of the adder 44 is a low frequency component that is passed through a low pass filter 47 and an output 1 which is a quadrature component is obtained.The output of the 0 subtracter 45 is a low frequency component that is passed through a low pass filter 48 and an output that is an in-phase component. 2 is obtained. Code values of these orthogonal components and in-phase components are obtained as demodulated signals. Similarly, the operation of the channel 2 processing section will be explained. The output of the AD converter 36 is sent to a multiplier 49.5.
It is input to 0. On the other hand, the output of the AD converter 37 is input to the multipliers 51 and 52 and is output every time the cumulative addition is performed.
5. Input to ROM 56 in which the cos waveform is stored. The sample signals of ROM 55 and ROM 56 are input to multipliers 50.52 and 49.51, respectively. The signals multiplied by the multipliers 50 and 51 are added together by the adder 53, and only low frequency components are output by the low-pass filter 58. The output value of output 3 represents the orthogonal component. The signals multiplied by multipliers 49 and 52 are subtracted by subtracter 54, and low-pass filter 59 outputs only low frequency components. The output value of output 4 represents the in-phase component. Code values of these orthogonal components and in-phase components are obtained as demodulated signals.

(Problems to be Solved by the Invention) As described above, in order to separate and demodulate each channel, ROM, integrator, orthogonal Duplicate demodulators must be provided. The equipment etc. will become larger due to the overlapped portions.

Furthermore, since most of the processing time associated with demodulation is spent on arithmetic processing in the multiplier, it takes time and effort to perform calculations for each channel.

The present invention has been made in view of these points. 1. It is an object of the present invention to provide a channel separation device that can be miniaturized by using common processing parts for each channel. [Structure of the Invention] (Means for Solving the Problem) In order to achieve the above object, in the present invention, the received signals transmitted on the first and second channels having different center frequencies are Using a quadrature demodulation unit that divides into in-phase components and quadrature components and demodulates each and outputs the demodulated in-phase components and quadrature components, and a reference value obtained from the center frequency of each of the first and second channels, a reference signal generator that generates an in-phase component and a quadrature component of a reference signal; a first multiplier that multiplies the in-phase component of the reference signal by the demodulated in-phase component; a second multiplier that multiplies the orthogonal component of the reference signal by the demodulated in-phase component; and a fourth multiplier that multiplies the orthogonal component of the reference signal by the demodulated orthogonal component. , a first adder that adds the output of the fourth multiplier to the output of the first multiplier, and a second addition that adds the output of the third multiplier to the output of the second multiplier. a first subtractor that subtracts the output of the third multiplier from the output of the second multiplier; and a second subtractor that subtracts the output of the fourth multiplier from the output of the first multiplier. the output of the first adder and the subtracter of the first
The signal obtained from the output of the subtracter is taken as the signal transmitted on the first channel, and the output of the second adder and the second
The signal obtained from the output of the subtracter is used as the signal transmitted on the second channel.

(Operation) The first and second demodulators have different center frequencies in the orthogonal demodulator
The received signal transmitted on the channel is divided into an in-phase component and a quadrature component and tuned. The reference signal generating section generates an in-phase component and a quadrature component of the reference signal using reference values obtained from the center frequencies of each of the first and second channels. A first multiplier and a second multiplier are provided for multiplying the in-phase component of the reference signal generated by these by the demodulated in-phase component and quadrature component, respectively.

Further, a third multiplier and a fourth multiplier are provided for multiplying the demodulated in-phase component and quadrature component of the orthogonal component of the reference signal, respectively.

The first adder is for adding the output of the fourth multiplier to the output of the first multiplier. The second adder is for adding the output of the third multiplier to the output of the second multiplier.

Further, the first subtractor subtracts the output of the third multiplier from the output of the second multiplier. The second subtractor subtracts the output of the fourth multiplier from the output of the first multiplier. The signal transmitted on the first channel is then obtained from the output of the first adder and the output of the first subtracter. Further, the signal transmitted on the second channel is obtained from the output of the second adder and the output of the second subtracter.

(Example) Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

The following description will be made based on a diagram showing an embodiment of the present invention shown in FIG. 1 and a waveform diagram shown in FIG. FIG. 1 shows a channel separation device for two channels. The center frequency of channel 1 is f, and the center frequency of channel 2 is f! shall be. This channel #
1.2 is input as a received signal to the channel separation device shown in FIG. The waveform diagram at this time is shown in Figure 2 (
Shown in a). This received signal is input to multiplier 1.2. The received signal input to the multiplier 11C is: Local oscillator f +f The oscillator 3 oscillates the intermediate frequency above -L to convert the frequency of the received signal to the baseband.

The frequency is oscillated and this frequency is transferred to the phase shifter 4 by 90°.
The received signal is frequency-converted to the baseband using a phase-shifted signal. This yields the outputs of the in-phase component and the orthogonal component. The waveform at this time is shown in FIG. 2(b). The signals output from the multipliers 1 and 2 are input to low-pass filters 5 and 6, respectively, and are subjected to fiAD conversion by AD converters 7 and 8. The output of the AD converter 7 is sent to the multiplier 9
, 10. Further, the output of the AD converter 8 is input to multipliers 11 and 12.

Here, a description will be given of the part that outputs the reference signal to be multiplied by the multipliers 9, 10, 11.12.

The center frequency of channel 1.2 is set to AD converter 7°.
-f A reference value of 2π-1 "1-T" is input to the integrator 19 based on the relationship with the sampling period of 8. This reference value is
It is equal to the difference φ between the center frequency and the frequency of each channel/l'. The integrator 19 performs a repetitive operation of outputting the input reference value and at the same time accumulatively adding the same reference value input next to produce the next output. The value output from the integrator 19 is stored in the ROM 17 where the sine waveform is stored and the ROM 1 where the CO8 waveform is stored.
8 is input. That is, in ROM17 and ROM18,
The SIN waveform and the CO8 waveform are converted into digital values and stored, and the ROM 17 stores the sampling signals using the output of the integrator 19 as the sampling interval.
0.11 ROM18 multiplier 9. It is output to J2. The sampling signal is a signal representing the sine wave or cosine wave of φ described above. This output sampler signal is added to the output of the AD converter 7.8 to the multipliers 9, 10, 11, 1.
2 is multiplied.

The waveform at this time is shown in Fig. 2 (C). In this state, the signal frequency-converted to the baseband band is
It is just a mixed signal of channels A/1 and 2. Therefore,
The outputs of the multipliers 9 and 11 are subtracted by the subtracter J5, and the outputs of the multipliers 1o and 12 are added by the adder 13 and inputted to the low-pass filters 20 and 21, respectively, to output only the low frequency band. , output 1 can be obtained as the in-phase component, and output 2 can be obtained as the orthogonal component. Similarly, multiplier 1
The output of 0.12 is subtracted by the subtracter 14, and the multipliers 9 and 1
1 in the adder 16, and output only the low frequency band through the low-pass filters 22 and 23, it is possible to obtain an output 3 as an in-phase component and an output 4 as a quadrature component.

These outputs 1.2 and 3.4 provide channels 2.2 and 3.4, respectively. l demodulated signals are obtained. Regarding this waveform, channel 1 is shown in FIG. 2(d) and channel 2 is shown in FIG. 2(e).

In this way, the number of multipliers and the number of ROMs can be reduced compared to the conventional ones, so the device can be made smaller.

Next, the processing of the above-mentioned 17 signals will be explained below using the formula.

Now the received signal is A(t)eos(2yrf1 is 1φ1)+B(t)eo
s(2rf, t+φ, ), this signal is orthogonally demodulated at the center frequency (fm + ft )], 2, and by passing through a low-pass filter, the in-phase component becomes A(t)eos(-2πφt+F, )+B(t )co
s (2xφt+lF,) orthogonal component is -(,4t)3 i, n (-2πφt +F1)
+Bct) s t n (2xφt+V'ri).

When this signal is multiplied by a complex number by the reference value of frequency φ, the output from the adder 13 of the complex multiplier is passed through the low-pass filter 21 (output 2), which is the output from the B (t) Sindt subtracter 15. The output 1 passed through the low-pass filter 20 becomes A(t) Co sφ.

These are divided by the quadrature component and the in-phase component of the channel 2 signal, respectively.

Next, the input to the adder 13 is input to the subtracter 14, and the input to the subtracter 15 is input to the subtracter 14.
When the input from the adder 16 is input to the adder 16, the output from the adder 16 is passed through the low-pass filter 23, and the output 4 is: The continuous output 3 is B(t)Sinφ1 and F), and from this result channel l
The in-phase and orthogonal components of can be obtained.

As described above, it is possible to separate signals transmitted through two channels into channel 1 and channel A/2.

FIG. 3 schematically shows the process of channel separation in the case of three channels. When a series of data is transmitted through three channels, the received signal will be as shown in FIG. 3(a). This signal f1 ft f.

are assumed to be equally spaced. This signal is orthogonally demodulated (in Fig. 3), and the received signal is converted into a baseband signal. Here, the baseband signal of channel 2 is obtained by passing this baseband signal through a low-pass filter with a narrow band. Below, channel 1 and channel 3 can be separated by complex number multiplication by frequency φ, similar to the embodiment of FIG.

By the same method as the embodiment shown in FIGS. 1 and 3,
Even when transmitting a series of data using n channels, the principle shown in Figure 1 is used when transmitting an even number of channels, and the principle shown in Figure 3 is used when transmitting an odd number of channels. According to the embodiment described above, by inputting the input to the adder J3 in FIG. In order to separate the channels 2, the multipliers that existed independently can be used as a shared I7, so that the dispersion of the multipliers can be halved.

〔Effect of the invention〕

As described above in detail, according to the button of the present invention, the number of multipliers and memories, which are conventionally provided for each channel, can be reduced by using them in common for each channel. Therefore, it is possible to reduce the size of the device for performing channel separation and demodulation and to simplify the channel separation process.

[Brief explanation of drawings]

Fig. 1 is a diagram showing an embodiment of the present invention, Fig. 2 is a diagram showing processing waveforms of each main part in Fig. 1, and Fig. 3 is a diagram showing waveforms in the case of 3 channels. , FIG. 4 is a diagram showing a conventional example. ], , 2.9, 1.0. IL 12... Multiplier, 3... Local oscillator, 4... Phase shifter 15, 6, 20.21.22.23... Low pass filter, 7.8... AD converter, 13.16...Adder, 14.15...Subtractor, 17.18...ROM. 19...' Integrator. Agent Patent Attorney Noriyuki Chika Yudo Hikaru Matsuyama

Claims (1)

[Claims] A received signal transmitted through first and second channels having different center frequencies is divided into an in-phase component and a quadrature component, each of which is demodulated, and the demodulated in-phase component and quadrature component are combined. an orthogonal demodulator that outputs an in-phase component; a reference signal generator that generates an in-phase component and an orthogonal component of a reference signal using reference values obtained from center frequencies of each of the first and second channels; and an in-phase component of the reference signal. a first multiplier that multiplies the in-phase component of the reference signal by the demodulated in-phase component; a second multiplier that multiplies the in-phase component of the reference signal by the demodulated quadrature component; a fourth multiplier that multiplies the quadrature component of the reference signal by the demodulated quadrature component; and a fourth multiplier that multiplies the output of the first multiplier by the demodulated quadrature component. a first adder that adds the outputs of the third multiplier to the output of the second multiplier; a second adder that adds the output of the third multiplier to the output of the second multiplier; a first subtracter that subtracts the output of the third multiplier; and a second subtracter that subtracts the output of the fourth multiplier from the output of the first multiplier; The signal obtained from the output of the adder and the output of the first subtracter is the signal transmitted on the first channel, and the signal obtained from the output of the second adder and the output of the second subtracter is A channel separation device characterized in that the signal transmitted through the second channel is used as the signal transmitted through the second channel.