JPH02259832A - Data processor - Google Patents

Abstract

PURPOSE:To perform the designation of an accumulator as keeping orthogonality by setting a first operand as the accumulator for arithmetic operation by an instruction which performs a binary operation, and designating a second operand with a universal addressing mode. CONSTITUTION:An instruction format is separated to an OP(operation)field 110, a D(direction) field 120, and an EA field 130, and the EA(effective address) field 130 shows the effective address information of a universal register 610 or a main memory 645. An EA mode decoder 670 decodes the EA field, and performs the multiplication of the accumulator 611 for data arithmetic operation and a memory data register MDR 642 by a computing element 630 under the control of a control circuit 680. In such a way, it is possible to keep the orthogonality between an instruction function and the operand, and to simplify the generation processing of an instruction code in a high-level language compiler.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention mainly relates to the architecture of microprocessors (M'LJ), and particularly to an instruction format and register configuration suitable for high-level language programs.

[Conventional technology]

As an example of the prior art, a 32-bit microprocessor 80386 manufactured by Intel Corporation will be used.

Registers EAX and EBX as general-purpose registers.

ECX, El)X, and register EAX is an accumulator.

The (abbreviated) commands that can implicitly specify an accumulator are limited to the following. Phase inversion instructions can only be specified in transfers to and from memory. For arithmetic/logical operation instructions, this can be specified only in operations with immediates. Furthermore, in multiplication/division instructions, one of the operands is limited to an accumulator.

The detailed specifications are shown in Microprocessor and Peripheral Handbook Vol. 1, pp. 4-107 to 127, published by Intel Corporation in 1988.

[Problem to be solved by the invention]

In general, the instruction format that implicitly specifies the accumulator has a shorter instruction length than the instruction format that specifies the accumulator using general-purpose addressing mode.
Execution time is also shorter. Therefore, high-level language compilers generate instruction formats that are implicitly specified. However, as mentioned above, the 80386 has a limited number of instructions that can implicitly access the accumulator. For other instructions, it is necessary to specify the accumulator as the general-purpose register FAX. Therefore, when Ilb class language compilers generate instruction codes, complicated processing is required. In other words, the instruction code must be determined while determining whether or not the accumulator can be implicitly specified depending on the function of the instruction.

Similarly, in other conventional 32-bit microprocessors, it is not possible to implicitly specify an accumulator regardless of the function of an instruction.

Therefore, complicated processing is required when generating instruction codes in a high-level language compiler.

In addition, orthogonality was maintained by accessing the accumulator in a general-purpose addressing mode, but in this case, an address field pointing to the accumulator was required in the instruction code, resulting in an increase in the instruction code.

Therefore, one object of the present invention is to provide an instruction system capable of specifying an accumulator while maintaining orthogonality.

[Means to solve the problem]

The purpose of the above is (1) to enable processing between the operand specified by general-purpose addressing and the accumulator in all instructions, and (2) to store the operation result in the accumulator or (3) has means for detecting the flag in the instruction; (4) has means for detecting the flag in the instruction;
) This is achieved by having a control circuit that stores the calculation results according to the detection means.

[Effect]

The case where the sum of variable X and variable Y is stored in variable Z is expressed in an assembler program as follows.

LD x (1) AD
D Y (2) ST
Z (:1) (1) is a load instruction and indicates that the contents of variable X are set in the accumulator.

(2) is an addition instruction which indicates that the contents of the variable Y and the contents of the AccuL router are added, and the result is set in the AccuL router.

(3) is a store instruction, which indicates that the contents of the accumulator are stored in variable Z.

It can be written using a simple sequence of instructions as shown above.

Furthermore, the case where the sum of variables X and Y is stored in variable Y is expressed in an assembler program as follows.

LL)X (4)A
Do/ST y (5) (4) is a load instruction and indicates that the contents of variable X are set in the accumulator.

(5) is an addition instruction, which indicates that the contents of variable Y and the contents of the accumulator are added, and the result is set in variable Y.

It can be written using a simple sequence of instructions as shown above.

Note that the instruction mnemonic /ST indicates that the operation result is stored in the operand specified by general-purpose addressing.

〔Example〕

Hereinafter, one implementation of the present invention will be explained using the drawings.

FIG. 1 is a block diagram showing an example of the internal configuration of the data processing device of this embodiment. The register file 610 is 32
This is a register file consisting of 16 registers with a bit data width, and is connected to internal data buses 620, 621, and 622 as shown in the figure. RO611 is used as an accumulator AccD for calculations, and R1612 is used as an accumulator A c a A for address calculations. Also, R
14613 is frame pointer FP, R15614 is stack pointer S)', 619 is protarum counter P
Used as C. The ALU 630 is also a 32-bit wide arithmetic unit that can perform not only arithmetic operations such as addition and subtraction of human data but also logical operations. MAR 640 is a register that holds the access address of main memory 645. This content is sent to main memory 645 via external address bus 641. The MDR 642 is a register that holds data written to the main memory 645 or data read from the main memory 645. An instruction register 650 that transfers data to and from the main memory 645 via the external data bus 643 is a register that holds instructions read from the main memory 645. OP code decoder 6
60 decodes the OP field 110 of the instruction register 650 and transfers the result to the control circuit 680. EA mode decoder 670 decodes the EA field 120 of instruction register 650 and forwards the result to control circuit 680. In addition to the decoding results described above, the control circuit 680 uses the D field 130 of the instruction register 650 to control the register file 610, the arithmetic unit 630, etc., and executes the processing written in the instruction register 650.

FIG. 2 shows the instruction format of this embodiment.

The instruction length is a fixed 16-bit length, followed by a 16-bit or 32-bit extension depending on the addressing mode.The instruction format is an 8-bit OP field, 110 bits, a 1-bit D field, 120 bits, and a 7-bit EA. It is divided into fields 130. The OP field 110 is an operation field, which will be described later.
As shown in the figure, instruction codes (operation codes) are shown.

1) (Direction) field 120 indicates the storage location of the calculation result. EA (effective address) field 130
indicates effective address information of general-purpose register 610 or main memory 645.

In this embodiment, one instruction is written in the above order of O)', 13°EA, and is expressed as OP/l)EA. This is called a mnemonic code.

The contents of the OP field 110 are shown in FIG.

The D field 120 is mainly used to specify the storage location of the results. For example, in the case of At)l) (addition) instruction, if D=O, AccD+(EA)→A c c D If D=1, AccD+(EA)→(EA), SUB (subtraction) instruction The same applies to AND (logical product) instructions.

Here, (EA) represents the operand specified in the EA field 130. Also, the "→" mark indicates that the value on the left side is the value of the operand on the right side.

In the case of S'l' (store) instruction, if D=O, then A
cc D-+(EA) If D=1, then A cc A-)(EA).

In the case of Ll) (load) instruction, if 1)=O, then (E
If A)→A c c D 1)=1, then (E A)→A c c A.

In the case of an LDA (load address) instruction, if I)=O, then E A −+ A c c DD; if D=1, E A −+ A a c A.

Here, EA represents the address of the operand specified in the EA field 130.

In the case of a JUMP instruction, if D=O,
If EA-+PC D=1.

(E A) → pc becomes.

Here, PC is a program counter that indicates the address of an instruction.

For B/c c (conditional branch) instructions, D=
If O, then when cc holds, EA-)PC l)=1, when cc does not hold, EA-))'C. Here, cc is a branch condition indicated by the ccc field 310 of the B instruction.

For JSR (subroutine jump) instructions, one =
If 0, next PC-+PUSH, EA-+
If PCD=1, next PC-+PUSH, FP-+PUS
H.

SP-+F'P, EA-+PC becomes.

Here, next PC is the address of the instruction following the JSR instruction. Further, PUSH means to reduce the contents of the stack pointer SP by 4 and store it at the address pointed to by the new stack pointer SP.

In the case of an RTS (return) instruction, if 1)=O, PoP→PC; if D=1, POP-+FP, pop-+pc.

Here, POP is the stack pointer SP
, and then increment the contents of the stand point pointer 81-1 by 4.

The contents of the EA field 130 are shown in FIG.

In FIG. 4, Rn indicates the contents of the n4th general-purpose register indicated by the 4-bit field nnnn in the EA field 130.

(aaa) indicates that the contents of the memory whose address is aaa in parentheses are used as the operand.

Therefore, (Rn) indicates that the contents of the memory whose address is the contents of the general-purpose register Rn are used as the operand. Also, (Rn+disρ16) is general-purpose register R
This indicates that the operand is the contents of the memory whose address is the sum of the contents of n and the 16-bit displacement.

(Ac cA+Rn 2) indicates that the operand is the contents of the memory whose address is the sum of the contents of the address calculation accumulator A c c A 612 and the value obtained by doubling the contents of the general-purpose register Rn.

In the addressing mode with disp16 or 1mm16, a 16-bit basic part 100 is followed by a 16-bit extended part 140. Also, disp32 or 1
In an addressing mode with mm32, a 16-bit basic part 100 is followed by a :32-bit extension part 150.

POP/PUSH indicates that the operand operates as a pop when it is a source operand, and as a PUSH when it is a destination operand. Here, FOP means fetching from the address pointed to by the stack pointer SP, and then increasing the contents of the stack pointer SP by 4. P.U.
SH means to reduce the contents of the stack pointer S)J by 4 and store it at the address pointed to by the new stack pointer SP.

(FP+8+nn *4) indicates that the value of the rightmost 2-bit field nn in the EA field 130 is multiplied by 4, and the contents of the memory that addresses the sum of the contents of the frame pointer FP613 and 8 are operanded. This is used to access subroutine arguments when they are allocated in the stack frame. In this case, the value of doP of the parent routine is saved at the address indicated by doP. Further, the return address of the parent routine is saved at the address indicated by F''P+4.

The first argument is saved at the address indicated by I'P+8, and the second and third arguments are also saved.On the other hand, the address indicated by I'P-4 is saved. The area for the second local variable is reserved at the address indicated by "first local variable area, )" P-8.

(FP-4-nn*4) multiplies the value of the rightmost 2-bit field nn in the EA field 130 by 4, subtracts it from the inner value of the frame pointer FP613, and then subtracts 4 to obtain the address. Indicates that the contents of memory are used as operands. This is used to access the argument when a local variable is allocated on the stack as described above.

FIG. 5 shows an example of a program for ffW'.

Figure 5(a) shows the contents of general-purpose register R2 and register R.
3 indicates that the contents of the memory whose address is indicated are added and the result is stored in the memory area whose address is indicated by (register R4+disρ16). The code size is 2+2+4=8 bytes. This is an example of a three-operand operation.

FIG. 5(b) shows the addition of the contents of general-purpose register r<2 and the contents of the memory whose address is indicated by register R3.
This indicates that the result is stored in the memory area whose address is set by register R3. Code size is 2+2=
It is 4 bytes. This is an example of a two-operand operation.

Figure 5(c) is (PC+displ 6+R2*4)
The content of the memory indicated by the address is set to low 1 in the arithmetic accumulator A c c D. The code size is 4+2=6 bytes. This is an example of index addressing mode.

FIG. 5(d) shows that the contents of the memory indicated by the address obtained by adding disp162 to the contents of the memory indicated by the address (R2+displ 6 L) are loaded into the arithmetic accumulator A c c D. ing. The code size is 4+4=8 bytes.

This is an example of a dual indirect addressing mote.

According to the instruction format of this embodiment, it is possible to specify the update of the frame pointer "P" with the JSR instruction or the R'rS instruction.
High-level procedure call/return processing can be performed at 6'h speed.

Furthermore, a 3-operand instruction can be realized in a minimum of 6 bytes, which is effective in reducing the code size.

Furthermore, considering the case where the sum of variable X and variable Y is multiplied by variable Z and the result is stored in variable Z ((x+y)*z→Z), in the embodiment of the present invention.

It can be executed with three instructions: L D / A c c D X ADD / Acc D Y MUL / ST Z. However, conventional microprocessors such as Intel's 80386 cannot store the result of a multiplication instruction in the location indicated by the general address field, so MOV X, FAX ADI) Y, FAX MUL Z, FAX MOV EA, It cannot be executed unless it is divided into four instructions, X and Z.

FIG. 6 is a flowchart showing the operation of the control circuit 680. After the initial routine 710, if the EA field 130 is in register direct mode, a direct instruction execution routine 740 is executed; if the EA field 130 is in memory reference mode, after executing the EA calculation routine 730, the instruction execution routine 740 is executed. Execute.

The contents of the initial routine 710 are shown in FIG.

In step 810, the PC (instruction address) 619 is
The instruction is transferred to the AR 640 and read from the main memory 645.

In step 820, the instruction read into the ML)R642 is set in the instruction register 1R650.

Update P'C619.

In step 830, the contents of the instruction register 650 are decoded by the OP code decoder 660 and the EA mode decoder 670.

A part of the contents of the EA calculation routine 730 is shown in FIG.

The EA calculation routine 730 sets the address when referencing the memory to A.
Calculate on LU630. Depending on the decoding results of the EA mode decoder 670, independent routines are executed.

FIG. 8(a) shows a processing routine in register indirect mode. The contents of the register indicated by the EA field 130 are assigned to the ALU 630.

FIG. 8(b) shows a processing routine in register indirect mode with displacement.

In step 920, the PC (instruction register) 619 is
Transfer to R640 and read the displacement from main memory 645.

In step 930) 'C619 is updated.

In step 940, the ALU 630 adds the displacement read into the MDR 642 and the contents of the register indicated by the EA field 130.

FIG. 8(Q) is a processing routine in the scaled index mode. The contents of the register specified by the EA field 130 are shifted 2 bits to the right by the shifter 631 attached to one input side of the ALU 630, and the address calculation accumulator A c c A
Add the contents of 612 with AL[J630.

A part of the contents of the instruction execution routine 740 is shown in FIG.

The instruction execution routines 730 execute independent routines depending on the decoding results of the ○P code decoder 660.

FIG. 9(a) is a processing routine for the Al)l) instruction.

Depending on the decoding result of the EA mode decoder 670, step 1010 is executed in the case of register direct mode, and step 1013 is executed in case of memory reference mode.

In step 1010, 8JL calculation accumulator A
The ALU 630 adds c c D 611 and the contents of the register indicated by the EA field 130 . after that,
If D field 120 of instruction register 650 is O, step 1011. If it is l, step 1012 is executed.

In step 1011, the calculation result of the ALU 630 is stored in the calculation accumulator A c c D 611 .

In step 1012, the calculation result of the ALU 630 is stored in the register designated by the EA field 130.

In step 1013, the memory address calculated by the ALU 630 is transferred to the MAR 640, and the memory address calculated by the ALU 630 is transferred to the main memory 640.
Read the operand from.

In step 1014, the calculation accumulator AccD
611 and the contents of the operand MDR 642 read from the main memory 645 are added by the ALU. Thereafter, if the D field 120 of the instruction register 650 is O, step Loll is executed, and if it is l, step 1015 is executed.

In step 1015, the calculation result of AL[J630 is
) is transferred to R642 and stored in main memory 645.

The address at this time is the same content of the MAR 640 as the address from which the operand was read immediately before.

FIG. 9(b) is a processing routine for the LL) instruction and the LL)A instruction. For the LD instruction, depending on the decoding result of the EA mode decoder 670, step 1020 is executed in the register direct mode, and step 1023 is executed in the memory reference mode.

Also, in the LDA instruction, in the memory reference mode, the judgment is 1.
Execute 025, and if in register direct mode, do nothing and exit.

In step 1020, the contents of the register indicated by the EA field 130 are transferred to the ALU 630.

In decision 1025, if D field 120 of instruction register 650 is 0, then step 1021.1, then step 1022 is executed.

In step 102J, the calculation result of the ALU 630 is stored in the calculation accumulator AC 611.

In step 1022, the calculation result of the ALU 630 is stored in the address calculation accumulator AccA 612.

In step 1023, the memory address calculated by the ALU 630 is transferred to the MAR 640, and the memory address calculated by the ALU 630 is transferred to the main memory 640.
Read the operand from.

In step 1024, the contents of the operand ML)R642 read from the main memory 645 are transferred to the ALU.

FIG. 9(c) is a processing routine for the ST instruction.

According to the decoding result of the EA mode decoder 670 and the value of the D field 120 of the instruction register 650, if the register direct mode L) = O, step 1030 is executed, and if the register direct mode is 1 = 1, step 10 is executed.
Execute 31. If L)=O in memory reference mode, execute step 1032, and D=1 in memory reference mode.
If so, step 1033 is executed.

In step 1030, the calculation accumulator Acc
l) Store the contents of 611 in the register indicated by EA field 130;

In step 1031, the contents of the address calculation accumulator A c c A 612 are stored in the EA field 130.
Store in the register specified by .

In step 1032, the address calculated by the ALU 630 is transferred to the MAR 640, and the contents of the calculation accumulator A c c D 6 L l are transferred to the MAR 640.
642 and stored in the main memory 645.

Step 1033 is ALU 630;? Transfer the calculated address to the MAR640, and also.

Accumulator for address calculation A c c A 61
Transfer the contents of 2 to the MDR 642 and store it in the main memory 64.
Store in 5.

The effects of the present invention will be explained using FIG. Consider the case of multiplying an accumulator by the contents of memory and storing the result in memory. In the present invention, a D field is also provided in the MUL (multiplication) instruction, so that the result of the operation can be stored either in the accumulator or in the memory. Therefore, the above multiplication operation can be performed by one M LJ L instruction. Its operation is similar to the At)L) instruction.

(1) In the initialization routine, the addressing mode is set to E.
It is decoded by the A-mode coder 670, and the type of instruction is decoded by the OP coder 660.

(2) The EA/L/-chinte calculates an effective address in the ALLI 630 according to the output of the EAII-decoder 6''10.

(3) In the instruction execution routine, first, memory data is fetched using the effective address calculated by the ALU 630. Next, the data calculation accumulator 611
and memory data register MDR642 (1) multiplication AL
[Implemented on J630.]

Finally, according to the D flag detector 690, the ALU6
30 multiplication results are stored in memory.

On the other hand, the case of a conventional microprocessor will be explained using Intel's 80386 as an example. In the 80386, the execution result of a multiplication instruction can only be stored in a register. Therefore,
when storing it in memory.

It is necessary to first store it in a register and then transfer it to memory using a transfer instruction. In other words, the D flag is not detected in (3) of the instruction execution step of the upper A pi, and the multiplication result is uniquely stored in the data calculation accumulator 611. To transfer this multiplication result to memory, MO
Execute V (transfer) command. Furthermore, if the instruction is divided into two instructions and executed in this way, the effective memory address must be calculated again, which is wasteful.

According to the present invention, storing the multiplication result in memory as described above can also be executed with one instruction.

〔Effect of the invention〕

As described above, according to the present invention, each instruction always has a general-purpose addressing field, and it is possible to maintain the target and deformation between the instruction function and the operand. This has the effect of simplifying processing.

Furthermore, since the operation result can be stored in the operand indicated in the general-purpose addressing mode instead of the accumulator, there is an effect that the number of store instructions for operation results can be reduced.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a data processing device that is an embodiment of the present invention, FIG. 2 is a diagram showing an instruction format of the data processing device of FIG. 1, and FIG. 3 is a diagram showing the instruction format of the data processing device of FIG. 1.
FIG. 4 is a diagram showing details of the P field and D field; FIG. 4 is a diagram showing details of the EA field of the data processing device of FIG. 1; FIG. 5 (a), (b), (c), (d) 6 is a flowchart showing the operation of the control circuit 680, and FIG.
8(a), (b), and (c) are flowcharts showing an example of the EA calculation routine 730. FIG. 9(a) is a flowchart showing details of the initial routine 710.
, (b), and (c) are flowcharts showing examples of an instruction execution routine 740. 100... Instruction basic part, 110... OP field, 120... D field, 130... To:A field, 140... Instruction extension part, 650... Instruction register lR1660... OP Code decoder, 6”
DESCRIPTION OF SYMBOLS 10... EA mode decoder, 680... Control circuit, 690... D flag detector, 611... Accumulator for data operation <Nino 1 Figure 2 Instruction format, ○P field tz. Figure 3 ○Details of P field and D field Figure 5 Program example (a) 3-operand operation (b) 2-operand operation (C) Index addressing mode (d) Double indirect addressing mode Figure 4 Details of EA field 1st otsuki 3rd prostitute

Claims (1)

[Claims] 1. In the instruction format of a data processing device, an instruction that performs a binary operation such as an addition instruction or a multiplication instruction is
The first operand is an accumulator for calculation, and the second
A data processing device characterized in that an operand of is specified in a general-purpose addressing mode. 2. In the instruction format of data processing devices, instructions that perform binary operations such as addition instructions and multiplication instructions are
A data processing device having a general-purpose addressing field for implicitly specifying an arithmetic accumulator as a first operand and specifying a second operand. 3. In the data processing device according to claim 1 or 2, the instruction for performing the second term operation: stores the operation result in the operation accumulator;
Alternatively, a data processing device comprising a 1-bit field that determines whether a calculation result is stored in the second operand specified by the general-purpose addressing field. 4. The data processing device according to any one of claims 1 to 3, wherein at least the instruction for performing the second operation includes: an OP field indicating the type of operation; an EA field indicating the general-purpose addressing mode; and a storage direction of the result. 1. A data processing device comprising a D field that determines a D field, wherein a bit position of the field is common to an instruction that performs the second term operation. 5. The data processing device according to claim 1, wherein the data processing device is comprised of a one-chip microprocessor.