JPH02254824A - Decoder - Google Patents

Abstract

PURPOSE:To prevent the scale of hardware from being increased and to attain high speed decoding processing by managing a code quantity not shifted in one code and an unprocessed data quantity in a parallel shifter section, deciding the shift quantity in response to the code quantity and the unprocessed data quantity and processing the shift by one clock. CONSTITUTION:A parallel shifter section 3 uses a code data fetched in a latch section 1 and a latch section 2 by using a latch pulse 12 to generate an address, which is given to a decoding table 6, from which a coefficient or a 0-run length and code length are obtained. Then a control section 5 controlling the shift quantity given to the parallel shifter section 3, a counting section 7 counting the code length in response to the processing data quantity in the parallel shifter section 3 and a counting section 8 counting the processing data quantity in the parallel shifter section 3 in response to the shift quantity given from the control section 5 are used to manage the unprocessed data quantity in the parallel shifter section 3 and the code quantity not shifted in one code, decides the shift quantity in response to the unprocessed data quantity in the parallel shifter section 3 and processing the shift by one clock.

Description

[Detailed description of the invention] Industrial applications The present invention relates to a variable length code decoding device.

Conventional technology As a hierarchical encoding method for still images, focusing on the fact that images have correlations, image data is divided into blocks of NXN (N: an integer) pixels, and the data within the block consisting of NXN pixels is A method that performs orthogonal transform such as discrete cosine transform (DCT), groups transform coefficients with similar frequency components within the block, and encodes and compresses the transform coefficients within that layer as one layer. be.

FIG. 5 shows the characteristics of the transform coefficients of the discrete cosine transform. The figure shows transform coefficients when discrete cosine transform is applied to pixels of an NXN two-dimensional block, and the shaded areas are parts with large values. Such transform coefficients are quantized and encoded, and the transform coefficients of blocks containing many low frequency components are concentrated at the upper left of the transform block.

FIG. 6 shows a diagram in which the conversion coefficients of one block (8×8 pixels) are classified into four hierarchies. The first layer is the direct current (DC) component of the conversion coefficient, the second layer is the three conversion coefficients obtained by removing the first layer part from the 2 lines x 2 rows of the low frequency component, and the third layer is the direct current (DC) component of the conversion coefficient.
4 lines x 4 rows of low frequency components as a hierarchy, first and second
It is classified into four hierarchies: 12 transform coefficients excluding the hierarchical part, and 48 transform coefficients excluding the first to third hierarchy parts from the 8 lines x 8 rows of low frequency components as the fourth hierarchy.

In this way, one block is divided into groups, and all blocks of the image are encoded for each grouped layer. In the first layer, no encoding is performed and the transform coefficients themselves are handled. From the second layer onwards, a non-fixed length code is assigned according to the coefficient value and the probability of O-run occurrence, and backing is performed on data with a predetermined effective length. During decoding, in the first layer containing DC components, data backed to a predetermined effective length is unbacked according to the precision of the transform coefficient, and from the second layer onwards, data is unbacked from the encoded data string according to the code bit length. Unbacking.

The unbacking process will be explained below.

FIG. 7 is a block diagram of conventional unbacking processing. In FIG. 7, 71 is encoded code pit string data read out as needed, 72 is a shift circuit,
73 is a decoding circuit that takes in and decodes a predetermined number of consecutive bits from the beginning of the pit string data from the shift circuit 72; 74 is data decoded by the decoding circuit 73;

75 is code length data indicating how many bits of the predetermined number of bits of the encoded code taken into the decoding circuit 73 are used for the decoding operation, and this is fed back to the shift circuit 72 and used. A shift circuit 72 shifts the code portion. 77 is a second shift circuit, which aligns with the end of the encoded code string existing in the shift circuit 72, transfers and supplements the n-bit encoded code string, and is a barrel shift circuit. Consists of. Here, "a"bC-"d" in 72 represents a code.

An arithmetic circuit 78 is provided to assist the operation of the shift circuit 77. This counts the number of encoded code string bits existing in the shift circuit 72, and during a shift-out operation, the number of bits of the code portion shifted out is subtracted from the count value, and every time a replenishment operation is performed, n Add bits. And the count content is n
If the number is n or more, it is determined that the shift circuit 72 has an empty space exceeding n bits, which is one unit of replenishment, and a trigger for transfer and replenishment is sent to the shift circuit 77. , has the role of informing the transfer position.The transfer position, that is, the bit position next to the last bit of the effective code pit string in the shift circuit 72 is based on the bottom stage of the shift circuit 72. From the number of steps,
This is the number obtained by subtracting the total bit length of the encoded code pit string remaining in the shift circuit 72.

Problems to be Solved by the Invention In the above-described hierarchical encoding method for still images, there is a high probability that the transform coefficients in the second and subsequent layers are O, and it is considered that 0 runs continue. In this case, while the 0 run is being output, the process of unbacking the code data string according to the code length and the process of outputting the transform coefficients operate in parallel. However, depending on the quantization method of the transform coefficients or the image, 0 runs may not always be continuous. Therefore, when code data is processed serially, the code part needs to be shifted serially, and processing speed cannot be increased. I can't hope.

On the other hand, if the second and subsequent layers are configured to process non-fixed length codes in parallel and unback them in code length units as described above (for example, Japanese Patent Application Laid-Open No. 60-259067), multiple selectors, Adders and subtracters are required, which increases the hardware scale.

In view of this, an object of the present invention is to provide a decoding device for variable length codes that can realize high-speed decoding processing with a simple hardware configuration.

Means for Solving the Problems In order to solve the above problems, the present invention provides a first importing means for importing compressed data in parallel in units of n bits (n: a natural number), and a first importing means for importing compressed data in parallel in units of n bits. a second importing means, a decoding table;
a barrel shifter section that generates an address to be given to the table from code data; means for controlling a shift amount given to the barrel shifter section; and a counting means that counts the code length according to the shift amount given by the shift amount control means; and counting means for counting the amount of processed data in the barrel shifter section according to the shift amount given by the shift amount control means, and manages the amount of unshifted codes in one code and the amount of unprocessed data in the barrel shifter section. , a shift amount is determined according to the unshifted code length and the amount of unprocessed data in the barrel shifter section, and the shift amount is processed in one clock.

According to the present invention, the amount of unshifted code in one code and the amount of unprocessed data in the barrel shifter section are managed, and the amount of shift is determined according to the unshifted code length and the amount of unprocessed data in the barrel shifter section. Since the shift is processed in one clock, the decoding process can be accelerated without increasing the hardware scale, and efficient decoding can be performed.

Example Hereinafter, the present invention will be explained in detail using the drawings.

FIG. 1 shows a block diagram of a decoding device in an embodiment of the present invention. In the figure, 1 and 2 are latch parts that take in code data of a predetermined bit length, 3 is a barrel shifter part that generates the code data taken in by latch parts 1 and 2 as an address, 4 is a timing control part, and 5 is a barrel shifter. Shift amount control section that controls the shift amount of section 3; 6 is a decoding table; 7 is a code length counter section that counts the code length of a code for one conversion coefficient or one O-run according to the shift amount; 8 9 is a counter unit that counts the amount of processed data according to the shift amount; 9 is a counter that counts the number of 0 conversion coefficients; 10 is a selector unit that selects O and conversion coefficients other than O; 11 is a selector unit 10
This is a latch unit that captures and outputs the conversion coefficients selected by .

Hereinafter, the operation of the circuit shown in FIG. 1 will be explained in detail. First, code data is taken into the latch section 1 and the latch section 2 by the latch pulse 12 output from the timing control section 4 . In the barrel shifter section 3, the latch section 1 and the latch section 2
Generate an address using the code data taken in,
The address is given to the decoding table 6 to obtain the coefficient value or O-run length and code length. At this time, the effective bit length of the code data is given to the code length counter section 7. Further, the code length counter section 7 and the counter section 8 give counter values to the shift amount control section 5 . The shift amount control section 5 controls the shift amount based on this counter value, and provides the shift amount to the barrel shifter section 3, code length counter section 7, and counter section 8. The barrel shifter section 3 performs a shift by the given shift amount. Further, the code length counter section 7 and the counter section 8 move the counters by the given shift amount. If the data from the decoding table 6 is a coefficient value, the selector 10 selects the output from the decoding table 6 and outputs it to the latch unit 11. Data from decryption table 6 is O
If the number of conversion coefficients is , the number of O's is set in the O run counter 9. In this case, the selector 10 selects 0 and outputs O for the number of 0s to the latch unit 11.

The latch section 11 takes in and outputs data in response to a latch pulse 18 from the timing control section 4.

Next, the operation of the barrel shifter section 3 will be explained using FIGS. 2, 3, and 4. In FIG. 2, 31 is a barrel shifter that takes in data from latch unit 2, 32 is a barrel shifter that takes in data from latch unit 1, and 7 is one conversion coefficient, or a code length for one O-run, depending on the amount of shift. A code length counter section 8 for counting is a counter section that counts the amount of processed data according to the shift amount. Figure 3 shows
This is a backing diagram of a non-fixed length code.■■■■・
It is assumed that the data is read in byte units in the order of... Fourth
The figure shows how the code shown in FIG. 3 is taken into the barrel shifters 31 and 32 and data is shifted.

First, insert the cord into the barrel shifter 31 and 32,
Barrel shifters 31 and 32 are as shown in (4-1). The 9 bits from the MSB side are given to the decoding table 16 as an address. The coefficient value and code length for code (■) are obtained from the decoding table 16. In this case, since the code length of the code ■ is 4-, the code length "4" is input to the code length counter section 7.
Set to . At this time, the value of the code length counter section 7 (RE
MCODE) is “4”, the value of counter section 9 (REVBY
TE) is "8". The shift amount control section 5 is a REMC
The shift amount is determined from ODE and REMBYTE, and the shift amount is sent to the barrel shifter 31, 32 and the code length counter section 7.
, is given to the counter section 8. The barrel shifters 31 and 32 shift by one clock by the shift amount, and the code length counter section 7
, the counter unit 8 moves the counter by the shift amount.

The smaller of the REMCODE and REMBYTE values is given as the shift amount. Assuming that the maximum shift amount is 4 bits, the shift amount is "4" in this case, so the barrel shifters 31 and 32 become (4-2). Next (4-2)
The 9 bits from the MSB side are given to the decoding table 16 as an address. The address enable signal at this time is
It is created from 5FTEND of the code length counter section 7. From this, the coefficient value and code length for code ■ are obtained from the decoding table 16. In this case, since the code length of code ■ is 5", the code length "5" is set in the code length counter section 7. At this time, the code length counter section ? (7) value (REMCOD
E) is "5", the value of counter section 9 (REMBYTE
) is “4°.The shift amount control unit 5
The shift amount is determined from E and REMBYTE, and the shift amount is applied to the barrel shifter 31, 32, code length counter section 7, and counter section 8. In this case, the shift amount is -4''.

The barrel shifters 31 and 32 shift by one clock by the shift amount, and the code length counter section 7 and the counter section 8 move the counters by the shift amount. Here, barrel shifter 31,3
2 becomes (4-3). In this case, there is no data to be processed in the barrel shifter 32 (REMBYTE=O)
Therefore, load the following code into the barrel shifters 31 and 32.

At this time, the data request signal is FUL from the counter section 8.
Created from L signal. The following code is loaded into the barrel shifter 31.32, and the barrel shifter 31.32 becomes (4-4). At this time, REMCODE is “1” and RE
Since MBYTE is "8", it is shifted by 1 bit.

In this way, the barrel shifter section 3 shifts a plurality of bits in one clock.

In addition, by limiting the maximum barrel shift amount to m bits depending on the frequency of occurrence of the code length of the generated code, the circuit scale of the barrel shifter section, the code length counter, and the processing data amount counter in the barrel shifter section can be reduced, and the hardware scale can be reduced. can be made smaller. In this case, if the code length of one code is e bits (N>m), it will be shifted multiple times.

Further, by setting the barrel shift amount to 2k (k: positive integer), the hardware scale can be further reduced.

Effects of the Invention As described above, according to the present invention, in a variable length code decoding device, the unshifted code amount in one code and the unprocessed data amount in the barrel shifter section are managed, and the unshifted code length is By determining the shift amount according to the amount of unprocessed data in the barrel shifter section, decoding can be performed at high speed without increasing the hardware scale. In addition, by setting the barrel shift amount to a maximum of m bits (m≦n, n: bit length when importing code data in parallel), or by setting the barrel shift amount in units of 2 (k: a positive integer). , faster decoding can be achieved with a simpler configuration.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a decoding device according to an embodiment of the present invention;
Figure 2 is a block diagram of the decoding table access address generation section, Figure 3 is a diagram showing non-constant length code backing, Figure 4 is a diagram showing the operation of the barrel shifter section, and Figure 5 is a diagram of the discrete cosine transform. A diagram showing the characteristics of conversion coefficients, Figure 6 is 1
FIG. 7 is a block diagram of conventional unbacking, which shows the block transform coefficients classified into four hierarchies. DESCRIPTION OF SYMBOLS 1... Latch part, 2... Latch part, 3... Barrel shifter part, 4... Timing control part, 5... Shift amount control part, 6... Decoding table, 7... Code Long counter section, 8... Counter section, 9... O run counter, 10... Selector, 11... Latch section. Name of agent Patent attorney Shigetaka Awano and one other person Figure 1 Figure Figure Figure

Claims (3)

[Claims] (1) In decoding in a variable length encoding system, a decoding table, a barrel shifter unit that generates an address to be given to the table from code data, means for controlling a shift amount given to the barrel shifter unit, and a code length that is a counting means for counting according to the shift amount given by the shift amount control means; and a counting means for counting the amount of processing data in the barrel shifter section according to the shift amount given by the shift amount control means; A decoding device characterized in that the amount of unshifted code in the code and the amount of unprocessed data in the barrel shifter section are managed, and the amount of shift is determined according to the unshifted code length and the amount of unprocessed data in the barrel shifter section. . (2) In the decoding device, the shift amount given to the barrel shifter section is set to a maximum of m bits (m<=l, m: natural number, l
2. The decoding device according to claim 1, wherein the decoding device has a maximum code length. (3) The decoding device according to claim 1, wherein the amount of shift given to the barrel shifter section is in units of 2^k (k: positive integer).