JPH0225293B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a phase discriminator that receives an input signal in the form of a pulse train. The device according to the invention may for example:
It is used for phase-based automatic frequency control, etc. in ultrasonic flowmeters, which generates a signal proportional to the phase mismatch between pulse trains. It is also used for automatic frequency control in radio and television receivers.

[Prior art and problems to be solved by the invention]

Phase discriminators are known in the art (see USSR Inventor's Certificate No. 534031, classification number H03K9/04), one input of which receives a reference signal in the form of a series of reference pulses, and , electrically connected to one of the inputs of the first storage element connected to one of the inputs of the first matching circuit, providing a signal to be analyzed in the form of a series of pulses to be analyzed. The other input of the phase discriminator is electrically connected to one of the inputs of a second storage element which is electrically connected to one of the inputs of the second matching circuit, and the output of the second matching circuit is is the output of the phase discriminator as well as the output of the first matching circuit. Further, the discriminator includes two inverters, the input of one inverter being connected to the discriminator input to which the reference signal is supplied;
The input of another inverter is connected to the discriminator input, to which the signal to be analyzed is supplied, and the output of the inverter is connected to the input of a second storage element. Furthermore, in the discriminator, first and second
The other inputs of the matching circuit are the second and first
is connected to the output of the storage element.

However, in known discriminators, due to the time delay of the signal in the inverter, a pulse is generated at one of the inverter outputs, the duration of which is greater than the error in the pulse train being compared. differ by a time equal to the delay time in . In this case a pulse is generated at the other output of the inverter, the width of which is equal to the delay time of the inverter. However, since these pulses give a signal indication in the opposite direction to the true direction for errors in the pulse trains being compared, the resolution of known discriminators is limited to a value equal to twice the delay time in the inverter. be done.

Furthermore, the circuit of the known discriminator is designed in such a way that only a rectangular reference signal is supplied to one of its inputs, which limits the field of application of the discriminator.

Furthermore, known discriminators have poor rejection of noise effects.

Other phase discriminators are known (Japanese Unexamined Patent Application Publication No. 1983-1993-
(See Figure 3 of Publication No. 36452), the phase discriminator is 1
A further input is provided with a gate signal in the form of a series of gate pulses and electrically connected to the set inputs of the first and second storage elements.

However, this conventional phase discriminator has the disadvantage of producing an uncertain output when the pulse trains of the reference and test signals to be compared are in phase.

Moreover, due to improper signal delays or differences in delay time in each storage element, the width of the pulses generated at one of its outputs will differ by the difference in delay time and mismatch value of the pulse trains to be compared. produce results. This difference has the disadvantage of being difficult to compensate for due to changes in the parameters of the storage element, such as temperature changes.

The two problems mentioned above limit the resolution of the conventional phase discriminator.

Since the gate signal of the phase discriminator is only used to return the storage element to the starting position,
The discriminator had inadequate noise resistance.

It is an object of the present invention to provide a phase discrimination device that makes it possible to increase the resolution of phase-sensitive automatic frequency control.

Another object of the present invention is to improve the ability to eliminate the influence of noise in a phase discriminator.

[Means and actions for solving problems]

These objects are achieved by providing a phase discriminator as follows, and in the present invention, one input 5 of the phase discriminator receives a series of reference pulses. one of the first storage elements 1 receiving the reference signal U ₀ in the form of a group and connected to one 9 of the inputs of the first matching circuit 7;
one input 3 is electrically connected to the second matching circuit 8 while the other input 6 receives the signal U ₁ to be analyzed in the form of a series of pulses to be analyzed; electrically connected to one input end 4 of the second storage element 2 connected to one of the inputs 10;
The output 19 of the second matching circuit 8, as well as the output 18 of the first matching circuit 7, is the output 1 of the phase discriminator.
9, the phase discriminator comprises a further input 13 to which a gating signal U ₂ is supplied in the form of a series of gating pulses, said input 13 being connected to a first and a second storage element, respectively. The first and second storage elements are electrically connected to the set input terminals 14 and 15 of the first and second set input terminals, and the first and second storage elements are connected to the set input terminals 14 and 15 during the pulse period of the gate signal to be input to the other input terminal. The output is inverted by the leading edge of the reference signal input to one input terminal or the signal to be analyzed and continues in this state until the pulse period of the gate signal ends, and the reference signal U ₀ The input 5 of the phase discriminator, which is supplied with U, is electrically connected to another input 12 of the second matching circuit 8, while the input of the phase discriminator is supplied with the signal U ₁ to be analyzed. The end 6 is electrically connected to a further input 11 of the first matching circuit 7, and the input 13 of the discriminator, to which the gate signal U ₂ is supplied, is connected to the first and second respectively. Also electrically connected to the inputs 16, 17 of the matching circuits 7, 8, each gate pulse from the series of gate pulses is connected to the reference signal
A phase discriminator is provided that receives an input signal in the form of a pulse train, which is characterized in that it includes the rising edge of each reference pulse from a series of reference pulses forming U ₀ .

In the device according to the invention it is possible to determine the true time of misalignment of the compared pulse trains of the reference and analyzed signals, thereby increasing the resolution of the phase discriminator.

Furthermore, the device according to the invention ensures that short pulses with the same time length are simultaneously present at the output of the phase discriminator when the phase difference of the compared pulse trains of the reference and of the signal to be analyzed is equal to zero; This provides continuous operation of the actuator of the phase-responsive automatic frequency control system, which improves the resolution of the phase discriminator.

Additionally, the device according to the invention provides phase-sensitive automatic frequency control for selected pulse trains, thereby improving the immunity of noise in the system.

〔Example〕

The invention will be illustrated by way of example with reference to the accompanying drawings, in which: FIG.

The phase discrimination device of the present invention includes a memory element 1 which can be represented by two RS type or D type trigger circuits, etc.
2 (FIG. 1), the respective inputs 3, 4 of which are a discriminator input 5 receiving the reference signal U ₀ and a discriminator input 6 receiving the signal to be analyzed U ₁ . Coincidence circuits 7 and 8 are connected to the outputs of storage elements 1 and 2 via their respective inputs 9 and 10. Other inputs 11 and 1 of respective matching circuits 7 and 8
2 are connected to discriminator inputs 6 and 5, respectively. The discriminator has an input 13 for receiving the gate signal U ₂ and connected to the set inputs 14 and 15 of the storage elements 1 and 2, respectively, and to the inputs 16 and 17 of the matching circuits 7 and 8, respectively. have This storage element is then activated at discriminator inputs 5 and 6 during the pulse period of the gate signal input to set inputs 14 and 15.
The output is inverted by the leading edge of the reference signal U ₀ inputted to the input signal U ₀ and the signal to be analyzed U 1 and remains in this state until the end of the pulse period.

The phase discriminator operates as follows. If there is no gate signal U ₂ (shown in FIG. 2, 1) at the input 13 (FIG. 1) of the phase discriminator, the storage element 1,
2 are set to a unit bias state by the appropriate set inputs 14 and 15. The reference signal U ₀ (FIG. 2 2) and the signal to be analyzed U ₁ (FIG. 2 3) are connected to the corresponding inputs of the phase discriminator and 6 (FIG. 1),
Thus, when the respective inputs 3 and 4 of storage elements 1 and 2 are reached, these storage elements 1 and 2 are set to the zero state. In this case, storage elements 1 and 2 are operated preferentially by set inputs 14 and 15.

When the gate signal U ₂ (FIG. 2 1) is applied to the input 13 (FIG. 1) of the phase discriminator, the storage elements 1,
2 is prepared for operation, in which case storage elements 1,
A signal is applied to inputs 14 and 15 of 2, which allows information to be stored in these storage elements, and a gate signal U ₂ (FIG. 2 1) is input to matching circuits 7 and 8, respectively. 16, 17 (Figure 1)
Allow input in . Furthermore, since storage elements 1 and 2 are set to the unitary state in the absence of gate signal U ₂ (FIG. 2), inputs 9 and 10 of the respective matching circuits 7 and 8 from storage elements 1 and 2 permit signals is supplied.

In the device according to the invention, one of the signals, for example the reference signal U ₀ (FIG. 2 2), is such that the leading edge of each reference pulse of the reference pulse train of the reference signal U ₀ (FIG. 2 2) is connected to the gate signal U 0 (FIG. 2 2). ₂ (Fig. 2 1) so that it is included in the gate pulse from the gate pulse train that constitutes
It is combined with the gating signal U ₂ (FIG. 2, 1).

The operation of the discriminator in three different states of phase mismatch of the signals being compared is considered as follows.

In the first operating state of the phase discriminator, there is a large value of phase mismatch between the signal U ₁ being analyzed and the reference signal U ₀ , and furthermore the pulse 20 of the signal U ₁ is separated from the gate signal. It's off.

In the first operating state of the phase discriminator, i.e. pulse 20 of the signal U ₁ being analyzed
(Fig. 2 3) is delayed from the reference pulse 21 (Fig. 2 2) of the reference signal U ₀ , the reference pulse 21
(Fig. 2 2), the memory element 2 (first
At the output of FIG. 2, the previously set state of the bias unit shown in FIG. 4 is maintained.
That is, within the time of pulse 20 the gate signal U ₂
This is because it does not exist.

When the reference pulse 21 (FIG. 2 2) is applied to the input 12 (FIG. 1) of the matching circuit 8, the signal being analyzed is present at the output 19 (FIG. 1) of the matching circuit 8.
A delayed pulse 23 (FIG. 2.5) is generated indicating that U ₁ is delayed from pulse 21 (FIG. 2.2) of the reference signal U ₀ .

In order to increase the immunity to noise effects, according to the invention the duration of the pulse 23 (FIG. 2 5) is equal to that of the gate pulse 22 (FIG. 2 1) applied to the input 17 (FIG. 1) of the matching circuit 8. ), ie the duration of the pulse 23 (FIG. 2, 5) is fixed when the value of the misalignment is large.

In the second operating state of the phase discriminator, i.e. when the pulse 25 being analyzed (FIG. 2, 3) is delayed from the reference pulse 26 (FIG. 2, 2) by a small delay value (second In the operating state of the phase discriminator (within the gate pulse 24 shown in FIG. 1), the output 19 of the matching circuit 8
The duration of the delayed pulse 27 (FIG. 2, 5), which shows the delay of the pulse 25 of the signal U ₁ being analyzed with respect to the pulse 26 of the reference signal U ₀ (FIG. 2, 2) in (FIG. 1), is the mismatch value. , which is equal to the zero state (FIG. 2.4) of the storage element 2 at the leading edge of the pulse 25 (FIG. 2.3) being analyzed which is applied to the input 4 (FIG. 1) of the storage element 2 (FIG. 2.3). ).Thus, passage of reference pulse 26 (FIG. 2) through matching circuit 8 is prohibited.

In this second operating state of the phase discriminator, no signal is present at the output 18 (FIG. 1) of the coincidence circuit 7 and thus at the discriminator output.

In the third operating state of the phase discriminator, the storage element 1 (first The output of FIG. 2 is biased to the state of the unit (FIG. 2, 6) until the arrival of pulse 28 (FIG. 2, 3). When the gate pulse 30 (FIG. 2 1) is applied to the input 16 (FIG. 1) of the matching circuit 7, the pulse to be analyzed 28 (FIG. 2 3) is the reference pulse at the output 18 of the matching circuit 7. A pulse 31 (FIG. 2, 7) is generated indicating that it is ahead of 29 (FIG. 2, 2). In this case, pulse 31 (FIG. 2, 7)
The leading edge of coincides with the leading edge of pulse 28 (FIG. 2, 3). The trailing edge of pulse 31 (FIG. 2, 7)
9 ((FIG. 2)), the pulse 29
is input 3 to storage element 1 (Fig. 1) according to Fig. 2 6.
bias toward zero. Therefore, matching circuit 7
The further passage of the pulse 28 (FIG. 2, 3) being analyzed, which is applied to the input 11 (FIG. 1) of the matching circuit 7, is prohibited, i.e. the continuation of the pulse at the output 18 (FIG. 1) of the matching circuit Time is reference pulse 2
9 (Fig. 2) and analysis of the pulse 28
(FIG. 2, 3). In this case, no pulse is generated at the output 19 (FIG. 1) of the matching circuit 8, but it is because the preceding pulse 28 (FIG. 2, 3), which is being analyzed, reaches the storage element 2 (FIG. 1). Reference pulse 29 (Figure 2 2)
This is because it is set to the zero state (FIG. 2, 4) before the leading edge of is reached. The passage of the reference pulse 29 (FIG. 2 2) through the matching circuit 8 (FIG. 1) is therefore prohibited. Gate pulse 30 (Figure 2 1)
When the operation of memory elements 1 and 2 (first
) are again set to their initial state.

In this way, the signal U ₁ (FIG. 2.3) to be analyzed lags in phase from the reference signal U ₀ (FIG. 2.2) or a gate signal is applied to it.
When proceeding within the range of U ₂ (Fig. 2 1), the outputs 19 and 1 of the corresponding circuits 8 and 7 respectively
8 (FIG. 1), a delayed pulse 27 (FIG. 2 5) and a leading pulse 31 (FIG. 2 7) occur. In this case, pulses 27 (FIG. 2, 5) and 3
1 (Fig. 2, 7) is the signal to be analyzed.
It is proportional to the phase difference between U ₁ (FIG. 2.3) and the reference signal U ₀ (FIG. 2.2).

If the duration of the signal U ₁ (FIG. 2.3) to be analyzed is not within the range of the gating signal U ₂ (FIG. 2.1), the output 19 (FIG. 1) of the matching circuit 8 will contain: A pulse 23 (FIG. 2, 5) having a duration from the leading edge of the reference pulse 21 (FIG. 2, 2) to the trailing edge of the gate pulse 22 (FIG. 2, 1), ie, a pulse with a maximum duration, occurs. , this pulse 2
3 (FIG. 2, 5) is used for phase detection.

Therefore, in the phase discriminator according to the invention, for example, an oscillator (not shown) under test that generates a selected sequence of pulses is used.
A phase-sensitive automatic frequency control is performed by aligning the gate pulse train with one of a series of coherent pulse trains provided as a reference signal.

The invention has technical and economic advantages, since in the invention an improvement in technical parameters is combined with a simple and reliable circuit.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a schematic circuit of a phase discrimination device according to the present invention, and FIG. 2 is a diagram showing temporal changes in signals of various parts in the phase discrimination device shown in FIG. 1. 1, 2...Storage element, 3...Input of memory element 1, 4
... input of memory element 2, 5, 6... input of phase discriminator, 7, 8... matching circuit, 9... input of matching circuit 7,
10... Input of matching circuit 8, 11... Input of matching circuit 7, 12... Input of matching circuit 8, 13... Input of phase discriminator, 14... Input of storage element 1, 15... Input of storage element 2, 16... Input of matching circuit 7, 17...
Input of matching circuit 8, 18...Input of matching circuit 7, 1
9...Input of matching circuit 8, _U0 ...Reference signal, _U1 ...Signal to be analyzed, _U2 ...Gate signal.

Claims (1)

[Scope of Claims] 1. A phase discrimination device, wherein 1.
One input 3 of the first storage element 1, whose two inputs 5 receive a reference signal U ₀ in the form of a series of reference pulses, and which is connected to one 9 of the inputs of the first matching circuit 7. , while the other input 6 receives the signal U ₁ to be analyzed in the form of a series of pulses to be analyzed, and one of the inputs of the second matching circuit 8 electrically connected to one input end 4 of the second storage element 2 connected to the second storage element 10;
The output 19 of the matching circuit 8 is, like the output 18 of the first matching circuit 7, the output 19 of the phase discriminator, which is supplied with the gate signal U ₂ in the form of a series of gate pulses. Yet another input terminal 1
3, the input terminal 13 is connected to the other input terminals 14, 1 of the first and second storage elements 1, 2, respectively.
5, and the first and second storage elements are electrically connected to the reference signal input to the one input terminal during the pulse period of the gate signal input to the other input terminal. or the input 5 of the discriminator, to which the reference signal U ₀ is supplied, whose output is inverted by the leading edge of the signal to be analyzed and continues in that state until the end of the pulse period of the gate signal;
is electrically connected to a further input 12 of the second matching circuit 8, while the input 6 of the phase discriminator, to which the signal U ₁ to be analyzed is supplied, is connected to the first matching circuit 7. electrically connected to another input end 11 of the
The input 13 of the discriminator, to which the gate signal U ₂ is then supplied, is also electrically connected to the inputs 16, 17 of the first and second matching circuits 7, 8, respectively, and a series of gate pulses A phase discriminator receiving an input signal in the form of a pulse train, characterized in that each gate pulse from the reference signal U ₀ includes a rising edge of each reference pulse from a series of reference pulses constituting the reference signal U 0 .