JPH02248063A - Semiconductor device and manufacture thereof - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Summary] Regarding a semiconductor device having groove-type isolation and a method for manufacturing the same, the present invention relates to a semiconductor device having groove-type isolation and a method for manufacturing the same. The method includes filling the trench with polysilicon with a lower impurity concentration from the sidewall of the trench toward the center, and oxidizing the upper layer of the polysilicon to form an insulating layer.

[Industrial application field]

The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a semiconductor device having groove type isolation and a method for manufacturing the same.

[Conventional technology]

The groove type isolation has a structure in which the inner wall of a groove 61 formed in a semiconductor substrate 60 is oxidized and the interior thereof is filled with polysilicon 2, as illustrated in FIG. 6(a).

In this groove type isolation, the semiconductor substrate 60
In order to prevent short circuit with the electrode wiring formed on the
Oxidize the upper layer of polysilicon 2 to 5tolJi.
63 (Fig. 6(b)), but when polysilicon 2 is oxidized, stress is concentrated on the upper edge of the groove 61, so oxidation of the peripheral portion of the polysilicon progresses. It is difficult to do so, and the center of 5iO1ii63 becomes raised.

By the way, as shown in FIG. 6(c), when there is a protrusion or step on the surface of the semiconductor substrate 60, the film formed on the semiconductor substrate 60 by a vapor phase growth method or the like will be damaged by the surrounding area A. A thick film is formed.

For this reason, if the conductive film 64 is grown on the semiconductor substrate 60 and then anisotropically etched to form the electrode wiring, a small amount of the conductive W464 will remain around the trench type isolation. , the electrode wirings will be short-circuited.

Therefore, when patterning the conductive film 64 on the 8108 layer 63 of the groove type isolation, after performing anisotropic etching, the conductive film 64 around the groove type isolation is removed by isotropic etching. There is a need.

[Problem to be solved by the invention]

However, when removing the excess conductive film 64 by such an isotropic etching process, the electrode wiring that has been finely and finely patterned by the anisotropic etching process in the previous process is also etched at the same time. In addition to not taking advantage of the advantages of static etching, problems such as thinning of the electrode wiring and increased resistance, increased tendency to generate electromigration silane, and reduction in gate length and increased seam channel effect are problems. occurs.

The present invention has been made in view of such problems, and provides a semiconductor device and a method for manufacturing the same that can maintain high pattern accuracy of electrodes formed on the Si01 layer of groove type isolation. The purpose is to

[Means to solve the problem]

The above-mentioned problem is solved by filling the groove 8 formed in the semiconductor substrate with non-monocrystalline silicon 11.12 (21, 30 to 35) with a low impurity concentration from the sidewall of the groove 8 toward the center. A semiconductor device characterized by having a trench-type isolation region, a step of forming a trench 8 in a semiconductor substrate, and a step of forming a trench 8 in a semiconductor substrate;
a step of filling non-monocrystalline silicon 11.12 with a lower impurity concentration from the sidewall toward the center; and a step of oxidizing the upper layer of the non-single-crystalline silicon 11.12 to form an insulating layer 13. The problem is solved by a method of manufacturing a semiconductor device characterized by having the following.

[For production]

According to the present invention, the non-single crystal silicon 11.12 (21°30-35) filled in the groove 8 provided in the semiconductor substrate l
Since the impurity concentration is made to decrease from the wall surface of the trench 8 toward the center, when the upper layer of the non-single crystal silicon 11.12 in the trench is oxidized, the impurity concentration added to the outside of the non-single crystal silicon 11.12 is reduced. It is possible to speed up the growth of oxides that are suppressed by stress, and it is possible to make the upward growth of the oxide film formed on the non-single crystal silicon 11.12 uniform. It becomes possible.

In this case, the non-single-crystal silicon in the trench 8 can have a multilayer structure with different impurity concentrations, or a film for preventing impurity diffusion can be formed between the eyebrows of this multilayer structure.

This makes it possible to appropriately control the growth rate of the non-single crystal silicon oxide film.

〔Example〕

(a) Description of one embodiment of the invention FIG. 1 is a process diagram showing an embodiment of the invention in cross section. First, as seen in FIG. 1(a), groove type isolation is formed. On the surface of the silicon substrate l to be
First silicon dioxide (Sing) film 2, nitride (Si3)
#4) After sequentially forming 83 and the second silicon dioxide film 4 to a thickness of 1000, 1000 and 1 μm, the resist 5 is applied on the second 5i021IIJ4.

After exposing and developing the resist 5 to form a window 6 in the isolation formation region, the resist 5 is used as a mask and a fluorine-based gas, for example CF, is applied.

Reactive ion etching (RIE) is performed using a gas containing CHF3 and a groove-forming window 7 is formed in the nitride film 4 and the Sing films 2 and 5 by anisotropic etching.

Next, after the resist 5 is ashed, the second 5IOt film 4 is used as a mask, and a chlorine-based gas, such as CAx or C, is applied.
CJ2. Anisotropic etching is performed on the substrate l by the RIE method using
A groove 8 with a depth of 3 μm and a width of
)).

With the groove 8 thus formed, thermal oxidation is performed to grow a 5IO film 9 with a thickness of 100° on the inner surface of the groove 8, as shown in FIG. 1(d).

Then, after forming a second nitride layer 1910 on the surface of the second S]0, the film 4 surface and the inner surface of the groove 8 by vapor phase epitaxy (the first
In Figure (e)), polysilicon 11 having an impurity concentration of 1011/cd is grown to a thickness of 2000 on the second nitride film 10, and a lower concentration than this polysilicon 11, for example, an impurity concentration is grown on the second nitride film 10. 1019 pieces/cd of polysilicon 12 are buried in the remaining space in the trench 7 (FIGS. 1(f) and (g)). In this case, impurities include elements such as phosphorus, arsenic, and boron.

This completes the groove forming process and filling process of the groove type isolation.

Next, the polysilicon 11.12 is etched by the RIE method so that the polysilicon 11.12 remains only in the groove 8, and is etched to a depth such that its upper end is below the surface of the semiconductor substrate l (step Figure 1 (h)).

After this, as shown in FIG. 1(i), the upper layer portion of the polysilicon 11.12 in the groove 8 is steam oxidized to form Si01
Grow layer 13. In this case, the thickness of the Sin layer 13 increases as the impurity concentration increases as shown in FIG. However, stress is applied to the polysilicon 11 in contact with the periphery of the groove 8, which suppresses its growth.
The StO film 13 growing from 2 grows uniformly upward. As a result, a flat insulating layer is formed on the surface of the substrate l.

In this case, a difference in concentration occurs between the two polysilicon IIs, 1211s''f, but no step occurs because the impurities are slightly diffused by the heat applied during steam oxidation.

Note that two nitride II layers formed on the surface of the silicon substrate l
! ! 3.10 and 2nd (7) When removing the SiOtl 14, phosphoric acid is used for the nitride film, and hydrofluoric acid is used for the Sin film.

(b) Description of the second embodiment of the present invention In the first embodiment described above, in the trench 8, the inner polysilicon 12 with a low impurity concentration is directly surrounded by the outer polysilicon 11 with a high impurity concentration. However, if the diffusion of impurities during thermal oxidation is large, the impurity concentration distribution within polysilicon becomes uniform, and the advantage of providing a concentration difference cannot be fully utilized.

As a method to suppress diffusion caused by such heat treatment,
A thin oxide lI*2o can also be formed between these polysilicon layers 1112, as shown in FIG.

Next, the process of forming this groove type isolation will be briefly explained.

The steps from forming the groove 8 in the silicon substrate 1 to forming the outer polysilicon 11 in the groove 8 are the same as those in the first embodiment (Figs. 1(a) to 1). f))
.

After that, as shown in FIG. 3(a), the impurity concentration is 10.
``One polysilicon 11/piece is etched by RIE method so that the upper end of the polysilicon 11 in the groove 8 is located below the upper surface of the substrate 1.The polysilicon 11 remaining in the groove 8 is then etched. is thermally oxidized to form a thin Sing film 20 on its inner surface.

After this, the groove 8 is filled with polysilicon 21 with an impurity concentration of 1019/C-, and anisotropic etching is performed until the polysilicon 21 has the same height as the inner polysilicon 11 (second Figure (k)).

Then, when the Sing film 22 is grown by steam oxidizing the upper parts of the two polysilicon layers 11 and 21, this Sing film 22 is grown.
The insulating layer 23 of the g film 22 is formed flat due to the difference in impurity concentration and stress with the trench 8 (second
Figure (1)).

(c) Description of other embodiments of the present invention In the two embodiments described above, two types of polysilicon with different impurity concentrations are formed by directing the polysilicon filling the trench 8 inward from the inner wall of the trench 8. However,
As shown in FIG. 4.5, it is also possible to fill three types of polysilicon.

For example, the impurity concentration is 1 from the inner wall of the groove 8 toward the center.
Three types of polysilicon, two types of polysilicon with a Qt of 1/cj and 10''/cal, and non-doped polysilicon are sequentially formed.

4(a) to 4(c) show a structure in which three types of polysilicon 30, 31, and 32 formed in the groove 8 are brought into direct contact, and FIGS. 5(a) to 5(c) show , SiO□ film 36.37 between three types of polysilicon 33, 34.35
is formed to prevent impurity diffusion.

In addition, in the above-mentioned four examples, the case where the concentration of the polysilicon filled in the groove 8 was grown discontinuously was explained, but when forming the polysilicon by the vapor phase growth method, the impurity element By continuously changing the addition,
It is also possible to continuously change the impurity concentration of the polysilicon inside the groove 8 from the wall surface toward the center, and then thermally oxidize the upper layer of the polysilicon.

Furthermore, although a silicon substrate was used in the above-described embodiment, the above-described embodiment can also be applied to the case where groove-type isolation is formed on a semiconductor substrate made of other semiconductors.

Further, in the above-described embodiment, the groove 8 is filled with polysilicon, but even when amorphous silicon is filled, the impurity concentration can be changed to make the growth of the Si0g film uniform.

〔Effect of the invention〕

As described above, according to the present invention, the impurity concentration of the non-single crystal silicon filled in the trench formed in the semiconductor substrate decreases from the wall surface of the trench toward the center. When oxidizing the upper layer of crystalline silicon, it is possible to speed up the growth of the oxide, which is suppressed by the stress applied to the outside of the non-monocrystalline silicon. It can be made uniform and groove-type isolation planarization is possible.

This eliminates the need for additional etching of the conductive film formed on the groove type isolation, and improves pattern accuracy.

[Brief explanation of drawings]

Figures 1 (a) to (+) are process diagrams showing the first embodiment of the present invention in cross section. Figure 2 is the relationship between oxide film growth and oxidation time using the impurity concentration of polysilicon as a parameter. FIGS. 3(j) to (1) are process diagrams showing the second embodiment of the present invention in cross section, and FIGS. 4(a) to (c) are characteristic diagrams showing the third embodiment of the present invention. A process diagram showing the embodiment in cross section, FIGS. 5(a) to (c) are process diagrams showing the fourth embodiment of the present invention in cross section, and FIGS. 6(a) to (c) are conventional method It is a process diagram showing a cross section. (Explanation of symbols) 1... Substrate (semiconductor substrate), 2... First Si0g film, 3... Nitride film, 4... Second 8108 film, 5... Resist, 8. ...Groove, 9...SiO□ film, 10...Second nitride film, lL12.21...Polysilicon (non-single crystal silicon), I3.23...Sin, layer (insulation M) , 20...5
IOt film, 30-36... polysilicon (non-single crystal silicon),
36.37...Si0g film.

Claims (4)

[Claims] (1) A semiconductor device comprising a groove-type isolation region formed in a groove formed in a semiconductor substrate and filled with non-single crystal silicon with a lower impurity concentration from the sidewalls of the groove toward the center. . (2) Claim (1) characterized in that the non-single-crystal silicon filled in the groove of claim (1) has a layered structure consisting of two or more non-single-crystal silicon layers having different impurity concentrations.
). (3) The semiconductor device according to claim (2), wherein a film made of a material that suppresses diffusion of impurities is formed between a plurality of non-single crystal silicon layers having different impurity concentrations. (4) forming a groove in the semiconductor substrate; filling the groove with non-monocrystalline silicon with a lower concentration of impurities from the sidewalls toward the center; and oxidizing the upper layer of the non-monocrystalline silicon. 1. A method of manufacturing a semiconductor device, comprising the step of: forming an insulating layer.