JPH02246612A - Watchdog timer circuit - Google Patents

Abstract

PURPOSE:To detect a fault of a final output stage itself by providing a flip-flop reset by a reset signal outputted from a CPU and setting the flip-flop when an output from a timer means exceeds a 1st setting value. CONSTITUTION:When the operation of a CPU to be monitored is normal, a reset signal WDTRSET is applied at a prescribed period. When the reset signal is applied, a flip-flop 6 is reset and when the reset signal WDTRSET goes to a low level, a capacitor C1 is charged by a constant current 11 and its terminal voltage et is increased gradually. A comparison means 3 outputs a pulse signal PS when the output voltage et of the timer means 1 is coincident with a 1st setting voltage es1. Thus, the function of the watchdog timer circuit itself and the circuit including the final stage inverter U4 is confirmed to be normal.

Description

DETAILED DESCRIPTION OF THE INVENTION <Field of Industrial Application> The present invention relates to a watchdog timer circuit for detecting failure or runaway of a computer (CPU), and more specifically, to a watchdog timer circuit itself and its output stage. The present invention relates to a watchdog timer circuit that has the ability to detect failures in circuits including circuits.

<Prior art> A watchdog timer circuit inputs a reset signal outputted from the CPU at fixed time intervals, and if the reset signal is not input even after a fixed period of time has elapsed, a time-up occurs and the CPU may malfunction or run out of control. This is to detect.

This type of watchdog timer circuit is provided to detect CPU failure or program runaway, so if such a situation occurs, it is necessary to output a signal that definitely indicates this. . Therefore, if the watchdog tie, the main circuit, or its output stage fails, its purpose will no longer be achieved.

No conventional watchdog timer circuit has a failure detection function for the entire circuit including the circuit itself and its final output stage.

<Problems to be Solved by the Invention> Here, an object of the present invention is to provide a watchdog timer circuit that has a failure detection function of the entire circuit including the watchdog timer circuit itself and its final output stage, and can improve reliability. It is about realization.

<Means for Solving the Problems> FIG. 1 is a block diagram showing the basic configuration of the present invention.

In the figure, 1 is a timer means to which a reset signal output from a CPU (not shown) is applied and reset;
2 is a set value signal output means, 3 is a comparison means for comparing the signal from the timer means 1 and the set value from the set value signal output means 2, and 4 is between the output terminal of the comparison means 3 and the output terminal 5. The provided low-pass filter 6 is a flip-flop that is set by a signal from the comparison means 3 and reset by a reset signal output from the CPU, and its output is applied to the set value signal output means 2. , change the set value signal to become larger.

When the reset signal is applied to the timer means, the timer means performs the timer operation after the reset operation. When the output from the timer means exceeds the first set value, the comparison means detects this and Set the result into a flip-flop. The output of the flip-flop becomes a signal indicating that the output stage circuit of the timer means is operating normally.

The output of the flip-flop increases the value of the setpoint signal from the first value to the second setpoint value and detects the time-up of the timer means.

<Example> Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 2 is a block diagram showing an embodiment of the present invention. In FIG. 6, the parts corresponding to those in FIG.
Shown with the same reference numerals.

The timer means 1 includes a transistor Q1 which is turned off by a reset signal WDTRESET signal from the CPU via an inverter Ul and a resistor R1, a capacitor C1 connected in parallel with the transistor Q1, and a constant current through the capacitor C1. It consists of a constant current source (1) for charging. R3 and R4 are resistors that divide the DC voltage Vcc.

The set value signal output means 2 includes a resistor R4, a transistor Q2 for connecting a resistor R5 in parallel to the resistor R4,
The output of the flip-flop 6 is applied to the base of this transistor Q2, and it is composed of a resistor R6 for driving this.

The comparison means 3 uses an operational amplifier U3 to which the output voltage et of the capacitor C1 is applied to one end and the voltage es generated across the resistor R4 to the other end, and which compares both signals.

The low-pass filter 4 is composed of resistors R7, R8 and a capacitor C2, and the output of the operational amplifier U3 is connected to the inverter U.
4. The time constant of this low-pass filter is selected so that short pulses occurring at the output of the comparison means 3 are not passed.

Flip-flop 6 connects the signal from operational amplifier U3 to inverter U4. A reset signal is applied to the 1' terminal via U5, and a reset signal is applied to the reset terminal R via the inverter U2, and the output <Q> (Q indicates an inverted signal of Q) is applied to the resistor R6. The check signal CHEC is applied to the base of the transistor Q2 through the check signal CHEC, which indicates whether the operation of the watchdog timer circuit is normal or abnormal.

The operation of the circuit configured in this way will be explained next.

FIG. 3 is a time chart showing an example of the operation.

When the operation of the CPLJ to be monitored is normal, the reset signal WDTRESET is applied to the timer means 1 at a constant period T1 as shown in (a>).

When this reset signal is applied, transistor Q1 is turned on, short-circuiting capacitor C1 and discharging the charge stored therein. Furthermore, the flip-flop 6 is reset.

When the flip-flop 6 is reset, the transistor Q2 is turned on in the setting signal output means 2, the resistor R4 and the resistor R5 are connected in parallel, and the first set voltage eS1 shown by equation (1) is set. is output.

Vcc (R4R5) esl=R3+(R4R5) (1) The broken line esl in (C) indicates the value of this first set voltage.

When the reset signal WDTRESET then becomes low level as shown in (a), the transistor Q1 is turned off and the capacitor C1 is charged by the constant current 11,
The terminal voltage et gradually increases as shown in (C).

The comparison means 3 calculates the first set voltage es expressed by equation (1).
l is compared with the voltage signal et from the timer means 1, and when ej exceeds the first set voltage esl, the output of the comparison means 3 is inverted from low level to high level as shown in (°d). However, the output of inverter U4 is inverted from high level to low level as shown in (e).

This signal passes through inverter U5 to flip-flop 6.
is applied to the set state. Therefore, its output <Q
> changes from high level to low level as shown in (b), and transistor Q2 changes from on to off. As a result, the parallel connection of the resistor R5 is released, and the set voltage es applied to the comparing means 3 is changed from the value of the above equation (1) to (2)
) second set voltage es2 (esl<es
2) will be changed.

e s 2= (Vc c −R4) / (R4shiR
5)...(2) Here, the changed second set voltage e expressed by equation (2)
The magnitude of s2 is selected to be larger than the output voltage et of the timer means 1 at the time when the time (corresponding to period T1) has elapsed until the next application of the reset signal WDTRESET.

Subsequently, the comparison means 3 compares the voltage e from the timer means 1 with
t and the second set voltage es2 are compared.

As a result, when the output voltage et of the timer means 1 matches the first set voltage esl expressed by equation (1),
The comparison means 3 outputs a pulse signal PS as shown in the figure, which changes from high level to low level in a short time as shown in (d).

This short pulse signal PS is applied to the low-pass filter 4, and this signal change is applied to the low-pass filter 4 with a time constant determined by the resistor R8 and capacitor C2, where it is removed and the signal is removed from the terminal. 5(I!I has (f
) does not appear as shown.

The voltage et of the capacitor C1 of the timer means 1 continues to increase as shown in (c), but the second set voltage es
Reset signal WDTRF applied before reaching 2:
The SET turns on the transistor Q1, discharges the charge, and returns to the initial state.

At this time, the CPU being monitored is 70 flips and 16
By confirming that the check signal CHECK output from the watchdog timer goes to low level and then goes to high level, it can be confirmed that the circuit including the watchdog timer circuit itself and its final stage inverter U4 is functioning normally. I can confirm that there is. As a result of this confirmation operation, if the check signal CHECK goes low once and then goes high, it is determined that the watchdog timer circuit is functioning normally, and the CPU outputs the next reset signal. It turns out.

From then on, as long as the monitored CPU is operating normally,
This kind of operation is repeated.

Next, the operation when the operation of the monitored CPU becomes abnormal will be explained.

In this case, the reset signal WDT'RESET is not applied even after the predetermined period T1 has elapsed.

The output voltage et of the timer means 1 is, as shown in (C), because the reset signal does not come even after a certain period of time has passed since the last reset signal WDTRESET was applied.
When the first set voltage esl expressed by the equation (1) is exceeded and a time corresponding to the time-up time T3 of the timer means 1 has elapsed, the second set voltage es2 expressed by the equation (2) is also increased. exceed.

When the output voltage et of the timer means 1 exceeds the second set voltage es2 expressed by equation (2) (corresponding to the time-up of the timer means 1), the comparison means 3 detects this and its output is (d). As shown in the figure, the level is reversed from low level to high level, and remains at high level.

This signal from the comparison means 3 is now passed through a low-pass filter 4 while maintaining a high level;
As shown in (f), a signal indicating time-up of the watchdog timer circuit is outputted from the terminal 5. The output signal of the watchdog timer circuit obtained at terminal 5 is:
It is used as a CPU reset signal, an external output signal, an interrupt signal, etc.

In the above embodiment, the timer means 1 is configured to charge the capacitor C1 with a constant current from a constant current source, but the capacitor C1 may be charged via a high resistance.

FIG. 4 is a configuration block diagram showing another embodiment of the present invention. In this embodiment, the timer means 1 is constituted by a counter that counts clocks, and the setting M signal output means 2 and the comparison means 3 are both constituted by logic circuits.

Here, the set value signal output means 2 outputs data A corresponding to the first set voltage esl and a second set voltage esl in advance.
2 is set, and when the signal Q from the flip 70 knob 6 is at a high level, the data B
is configured to output data A to the comparison means 3 when the signal is at a low level.

The basic operation is similar to the embodiment shown in FIG.

<Effects of the Invention> As explained in detail above, according to the present invention, by adding a simple circuit, it is possible to detect failures in the final output stage and the like, thereby providing a highly reliable watch. can be realized by the dock timer circuit.

[Brief explanation of drawings]

Figure 1 is a block diagram showing the basic configuration of the present invention, Figure 2 is a block diagram showing the basic configuration of the present invention.
FIG. 3 is a block diagram showing one embodiment of the present invention, FIG. 3 is a time chart showing an example of operation, and FIG. 4 is a block diagram showing another embodiment of the present invention. 1... Timer means, 2... Set value signal output means,
3... Comparison means, 4... Low pass filter, 5...
・Output terminal, 6...Flip-flop Figure 1, Figure Z

Claims (1)

[Scope of Claims] A timer means that is reset by applying a reset signal output from a CPU to be monitored, a set value signal output means that outputs two types of set value signals, and a signal from the timer means. a comparison means for comparing the set value from the set value signal output means; a low-pass filter provided between the output terminal of the comparison means and the output terminal;
a flip-flop that is reset by a reset signal output from the PU and outputs a signal for changing the set value of the set value signal output means, and obtains a time-up output via the low-pass filter; A watchdog timer circuit that allows checking whether the circuit is operating normally based on changes in the output signal of a flip-flop.