JPH02246546A - Decision device for peak position of correlation signal - Google Patents

Abstract

PURPOSE:To demodulate data correctly by setting an observation section which has certain width in a data section and deciding whether or not there is a peak position in the observation section. CONSTITUTION:The correlation peak of the correlation signal between a received signal and a code sequence with specific code length is detected. A peak position detecting circuit 26A is a circuit that detects which position in the data section the peak of the correlation output is at and the peak position PP is measured as the time from the point of time when the maximum value of the correlation output appears to a data section end signal ED. Then it is decided whether or not the peak position is in the observation section set in the data section. Consequently, the correct demodulation processing is enabled.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application This invention relates to a receiving device for spread spectrum (SS) communication, particularly for code shift keying (Code Shift Keying).
5hlfL Keying -CSK) This invention relates to a peak position determining device for a correlation signal in a receiving device based on modulation method 1.

The conventional SS communication system has been widely applied to power line communication as well as satellite communication and mobile communication. A conventional SS communication system will be explained with reference to FIGS. 15 and 16. On the transmitting side, the output a of the PN (pseudo-noise) code sequence generator 1 is EX-ORed with the transmission data b by the EX-OR circuit 2.
After the calculation (signal c) + amplifier 3 sends out as a transmission signal to the transmission path. On the receiving side, the received signal is amplified by an amplifier 4, then correlated with the output d of the synchronous PN code sequence generator 5 by a correlator 6, and the correlation value (signal e) is compared with a predetermined threshold value by a comparator 7. Demodulate the received data f.

The transmission path may be wireless, wired, or other transmission media. Therefore, the transmission signal is not only sent directly to the transmission medium, but also often converted into a signal suitable for transmission through the transmission medium and sent. In addition, power line communication requires an interface that is separate from the commercial 1U power line. The connection portion with the transmission medium that performs such signal conversion and separation is hereinafter referred to as a reception interface and a transmission interface.

Problems to be Solved by the Invention In conventional communication systems, it is necessary to synchronize the PN sequence generated by the synchronous PN code sequence generator 5 on the receiving side with the PN sequence on the transmitting side. There is a need to. If there is no problem with the transmission characteristics of the transmission path, a peak is detected in the correlation waveform at the synchronization point. However, in power line communications, where the transmission characteristics are extremely poor and there are dip points within the transmission band, the correlation waveform deteriorates and the relationship between positive and negative correlation values becomes reversed.

This may result in a data error of 1 or 0. Another drawback was that synchronization could not be maintained due to waveform deterioration.

The applicant has proposed a new C3K communication method that overcomes the drawbacks of the conventional SS communication method.

In the C5K communication system, on the transmitting side, two binary PN code sequences with low cross-correlation and the same code length are generated at a constant cycle, and at each constant cycle, the two binary PN code sequences are generated depending on whether the transmitted data is 1 or O. One of the different PN code sequences is selected and sent as a transmission signal. On the other hand, on the receiving side, two correlation outputs are obtained by correlating the received signal with the two PN code sequences used on the transmitting side. A correlation peak always appears in one of these two correlation outputs at each of the above-mentioned fixed periods. Therefore, 2
Demodulated data of 1 or 0 is created by comparing the peak values of the two correlation outputs.

In such a C5K communication system, the receiving side compares two correlation outputs and assigns O or 1 to the received data depending on the magnitude of the peak value, so the code sequence on the receiving side is the same as that on the transmitting side. There is no need to strictly synchronize with this, and data demodulation errors will not occur. Also as the output of the correlator.

By taking the absolute value, there is an effect that no error occurs even in the case of a transmission line whose characteristics are deteriorated such that the transmission peak value becomes negative.

As described above, a correlation peak appears in one of the two correlation outputs at each of the above-mentioned fixed periods. In order to correctly detect this correlation peak on the receiving side, it is necessary to synchronize the operation of the receiving side device with the received signal so that the correlation peak appears periodically within a certain period. especially,
In the case of power line communication, when using a poor transmission path such as a commercial AC power line, the transmission characteristics may change rapidly and the peak position may vary greatly. It is necessary to determine with a certain tolerance whether the correlation peak is at a predetermined position within the above-mentioned predetermined interval.

The present invention provides an apparatus for determining the peak position of a correlation signal in a receiving apparatus for the C8K communication system, which has the excellent features described above.

Means for Solving the Problems A correlation signal peak position determination device according to the present invention detects a correlation peak of a correlation signal between a received signal and a code sequence of a predetermined code length, and determines the period of this correlation peak corresponding to the code length. A peak position detection circuit that detects a position within the data interval, and a peak position determination circuit that determines whether the detected peak position is within an interval set within the data interval. shall be.

A correlation peak of a correlation signal between the active received signal and a code sequence of a predetermined code length is detected, and the position of this correlation peak within a data interval with a cycle corresponding to the code length is detected. Then, it is determined whether this peak position is within the observation interval set within the data interval.

Embodiment Below, an embodiment in which the present invention is applied to a C8K communication system using Manchester code M sequence as a PN code will be described in detail.

(1) Overall configuration of C8K communication system FIG. 1 shows the overall configuration of a C5K communication system using the Manchester code M sequence.

On the transmitting side, the modulating device (transmitting device) 11 is provided with two Manchester M-sequence generators 31 and 32 that each synchronize and generate Manchester code M-sequences with low cross-correlation and the same code length. The code output of is given to the switching circuit 33. This switching circuit 33 is controlled according to the binary transmission data (1 or 0); for example, when the transmission data is 0, the code output of the generator 31 is selected, and when the transmission data is 1, the code output of the generator 32 is selected.

The code output signal selected by this switching circuit 33 becomes the transmission signal TXO. Switching control in the switching circuit 33 is performed in synchronization with the cycle of the Manchester code M series that is generated, and one piece of binary data (1 or 0) is expressed by the Manchester code M series of -cycle.

Since the switching or selection of two different Manchester code M sequences is performed according to the code (1 or 0) of the data to be transmitted, this modulation method is called code shift keying (CSK).

Of course, CSK is not limited to the Manchester M sequence, and other PN code sequences may be used.

The transmission signal TXO is sent out to the transmission line or transmission medium via the transmission interface 12A. As described in the "Prior Art" section, the transmission interface 12A is a connection section in a broad sense, and is a section that performs carrier modulation, mixing processing into a power line, and the like.

The reception interface 12B also demodulates the carrier.

It performs separation from the power line, A/D conversion, etc., and converts the signal input from the transmission path or transmission medium into a digital reception signal RXI and outputs it.

The receiving device on the receiving side includes two correlators 21, 22° demodulator 23. Carrier detection circuit 24. It includes a synchronous control circuit 25 and the like. The digital reception signal RXI output from the reception interface 12B is branched into two parts and sent to correlators 21 and 22, respectively. A Manchester code M sequence generated from one Manchester M sequence generator 31 is set in one correlator 21, and a correlation is taken between this set sequence and the received signal RXI. Similarly, the other correlator 22 is set with the Manchester code M sequence generated from the other Manchester M sequence generator 32.
The correlation between this setting sequence and the received signal RXI is taken. The correlation outputs obtained from these correlators 21 and 22 are given to a demodulator 23, in which a demodulated signal 1 or 0 is assigned according to the correlation value, and the received data R
Output as XD. That is, if the correlator 21 shows a larger correlation peak value among the correlation outputs of the correlators 21 and 22, the received data of 0 will be received by the correlator 22.
If the correlation peak value is larger than that of the correlation peak value, one received data is generated.

The correlation output is also input to carrier detection circuit 24 and synchronization control circuit 25. The carrier detection circuit 24 detects the presence or absence of a carrier based on the correlation output, and provides the detection signal to the synchronization control circuit 25. The presence or absence of a carrier is determined by the received signal RX.
This is used to determine whether or not I is being received. The synchronous control circuit 25 is.

When a carrier is being detected, a timing signal for demodulation and carrier detection is created based on the correlation output and is provided to the demodulator 23 and the carrier detection circuit 24.

As described above, in the CSK communication system, two correlation outputs are compared on the receiving side, and the output of the received data is determined depending on the magnitude.
Since the Manchester M sequence on the receiving side does not need to be strictly synchronized with that on the transmitting side, data recovery': Js errors do not occur. Furthermore, if the absolute value is taken as the output of the correlator, no error will occur even in the case of a transmission line with degraded characteristics such that the transmission peak value becomes negative. Furthermore, by using the Manchester code M sequence, it is possible to reduce the low-frequency components of the received signal and suppress the coupling loss with the transmission path.

(2) Configuration example of CSK modulation device FIG. 2 shows a specific configuration example of the C3K modulation device 11. Further, output signal waveforms of each part of this circuit are shown in FIG.

In this embodiment, each Manchester M-sequence generator 31, 32
is a three-stage (n-3) shift register FF.

~FFFF-FF23, and these shift registers perform a data shift operation at the timing of the clock signal CK output from the clock generator 34. The feedback circuits of these shift registers are different from each other. In other words, in shift register FF - FF,
The codes of the cells in the second and third stages are determined by the exclusive OR circuit (EX
-OR) 31a to its input side, whereas in the shift register FF-FF23, the codes of the first and third stage cells are fed back via the EX-OR circuit 32a. The shift register and its feedback circuit are connected to an M-sequence generator (PN code generator, PN code - PseudeNoi
se Codex pseudo-noise codes). Then, the exclusive OR of the code output of the final stage of each shift register and the clock signal CK is EX-OR.
A Manchester code is created by taking the signals in circuits 37 and 38.

When one Manchester M-sequence generator 31 has a specific phase (all 1), the other Manchester M-sequence generator 32
A phase synchronization circuit is provided so that the phase always remains constant (initial phase). This phase synchronization circuit includes a NAND circuit 3B and an initial phase setter 35. The initial phase setter 35 is for setting an initial code in each stage of the shift registers FF-FF23.
(a code other than that) can be set. Shift register FF −
When the codes of all stages of the FF 13 become 1 (this state occurs once in one cycle T of the Manchester code M series), an L level signal is generated from the NAND circuit 3B.
At the next rising edge of the clock signal CK, the sign set in the initial phase setter 35 is transferred to the shift registers FF21 to FF.
23, respectively.

As mentioned above, the outputs of the Manchester M-sequence generators 31 and 32, that is, the outputs of the EX-OR circuits 37 and 38, are given to the switching circuit 33, and are transmitted every period (data interval) T of the Manchester code M-series according to the transmission data TXD. A switching operation is performed. Further, the output of the NAND circuit 36 is given to a transmission data processing section (for example, a microprocessor) as a transmission request signal. Every time this transmission request signal is input, the transmission data processing section processes one bit of the transmission data TXD (
1 or 0) and provides it to the switching circuit 33.

FIG. 4 shows a modification. Comparing with FIG. 2, we can see that EX-
The OR circuits 37 and 38 are removed, and instead, the output of the switching circuit 33 and the clock signal C are connected to the output side of the switching circuit 33.
An EX-OR circuit 39 which receives K as an input is provided to create a Manchester code.

Reference numerals 31A and 32A each refer to an M-sequence generator, and their outputs (signs of the final stage of the shift register) are provided to a switching circuit 33, respectively. This modification has the advantage that the number of EX-OR circuits can be reduced by one.

Note that the output side of the switching circuit 33 in FIG. 2 and the EX- in FIG.
It is preferable to provide a one-clock latch circuit on the output side of the OR circuit 39 to shape the waveform of the transmission signal TXO.

(3) Configuration Example of Correlator Next, the configuration of the correlators 21 and 22 will be explained in detail with reference to FIG.

The correlators 21 and 22 each have N stages of registers 41a.

41b, and these registers 41a, 41b.

Manchester M-sequence generator 31 included in modulation device 11
, 32 are respectively set in advance. The code length of the M sequence generated using an n-stage shift register is 2°-1 bit. Since the M sequence is Manchester encoded in the modulation device 11, the number of stages N of the registers 41a and 41b is N-2 (2
n-1).

On the other hand, the digital reception signal RXI manually input from the reception interface 12B is branched into two and input to shift registers 42a and 42b provided in each correlator 21 and 22. These shift registers 42a and 42b also have N stages and are driven by a clock CK having twice the frequency of the clock signal in the modulation device 11.

In the correlator 2I, the code of each set stage of the register 41a and the code of the received signal sent to the corresponding stage of the shift register 42a are respectively output to an EX-OR circuit 43.
Compare at a. The output signals of all EX-OR circuits 43a are given to an adder 44a and added. Adder 4
The output signal 4g represents the degree of coincidence between the code of each stage of the register 41a and the code of each corresponding stage of the shift register 42a, and this is the correlation output R of one correlator 21.
becomes. This is because the received signal RXI is sequentially shifted through the shift register 42a every clock signal CK.

The correlation output R also changes accordingly for each clock signal CK.

Similarly, in the other correlator 22, the register 41
The EX-OR circuit 43b checks whether the sign of each stage set in b matches the sign of the received signal sent to the corresponding stage of the shift register 42b. The output signals of all EX-OR circuits 43b are sent to the adder 4
4b and is added. The adder 44b outputs a correlation output R indicating the degree of correlation between the Manchester M sequence set in the register 41b and the input digital received signal RXI.
6 will be output.

FIG. 6 shows a modification of the correlator 21. register 4
1a and the shift register 42a, the number of stages is Nxm.
(rn is a positive integer of 2 or more) register 41A and shift register 42A are provided. The shift register 42A is driven by a clock signal CK having a frequency m times that of the clock signal CK. NXm pieces of EX-OR circuits 43A are also installed,
The codes of the corresponding stages of the register 41A and shift register 42A are input to each EX-OR circuit 43A.

The adder 44A adds the output signals of all the EX-OR circuits 43A and outputs the result as a correlation output R. In this way, by increasing the number of stages of registers and shift registers by m times, the accuracy of correlation calculation is improved.

It goes without saying that the correlator 22 can also be modified in the same way.

FIG. 7 shows yet another embodiment. Here, the shift register 42 to which the received signal RXI is input is the correlator 21.
and 22. By doing so, the number of shift registers can be reduced and the configuration can be simplified. It goes without saying that a shift register with the number of stages multiplied by m as shown in FIG. 6 can also be used as the correlators 21 and 22 in the same way.

(4) Demodulator and carrier detection circuit FIG. 8 shows an example of the structure of the demodulator 23 and the carrier detection circuit 24. Also, the signal waveforms of each part in FIG.
As shown in the figure. In this figure, correlation outputs R, Rb
is drawn in analog form for easier understanding.

Correlation outputs R and R output from a pair of correlators 21 and 22
First, the principle of demodulating data based on 6 and 6 will be explained. Referring to FIG. 9, one data interval T (this is equivalent to one period of the Manchester M series) is defined as the window part (referred to as the W part) in the center of rl and the parts before and after it (this is referred to as the E part). Divide into. The front and rear E portions are set at equal intervals.

However, it is not necessary to set the E sections before and after the W section equally, and the W section does not need to be set at the center of the data section. O<
Using d that satisfies d<T.

The W part is an area from (T-d)/2 to (T+d)/2.

Part E is the section from 0 to (T-d)/2 and from (T+d)/2 to T.

It can be expressed as The W section is also called the observation section.

When data is being transmitted, a correlation peak appears in one of the correlation outputs R and Rb within the data interval T. In the synchronization control circuit 25, this correlation peak is detected, and a data section end signal ED is created which defines the end point of the data section so that the correlation peak is located at the center of the data section T. Then, based on this data section end signal ED, the synchronization control circuit 25 creates a window competition start pulse WL and a window stop pulse WH that define the start point and end point of the W section, respectively.

The meanings of the symbols P, P, AA are as follows: ay by
aE' bE.

P: Peak value av of correlation output R at W part
a (maximum value) P: Peak value y (maximum value) of the correlation output Rb in the W part (maximum value)
a calculation value) A - summation (addition bE' calculation value) of the correlation output R6 in the E section Demodulated data (received data RXD) is generated as follows.

If P fist A > P −A, the data is 1゜by
a[E ay bEP −A <P
-A then the data is 0° by aE
ay bE Theoretically speaking, if Pby>Pay, the data may be determined to be 1°, and if the opposite is true, the data may be determined to be O. however,
Considering the case where noise is included, demodulation errors may occur when comparing peak values in correlation outputs.

Generally, in a correlation output that has a correlation peak, the levels before and after the peak are smaller than the correlation level of a correlation output that does not have a correlation peak. For example, when the correlation output Rb has a correlation peak, the sum AbE before and after it is smaller than the sum AaE of the correlation outputs R without a correlation peak. Utilizing this property, in order to prevent demodulation errors as much as possible, the product of the peak value and the sum of mutually separate correlation outputs, that is, P
-A and P -A by aE
This means that demodulated data is created by performing ay bE small comparison.

This makes it possible to perform stable demodulation even when the transmission characteristics of the transmission path are poor and noise is likely to occur.

Next, the principle of carrier detection will be explained. That is,
The absolute value of (P −A −P −A ) is b
Carrier detection is performed when y aE ay LIIE exceeds a predetermined threshold level Th. The presence of a carrier means that a correlation peak appears on either one of the correlation outputs. Therefore, the absolute value of the difference between the products of the peak values and the sums of the mutually separate correlation outputs exhibits a large value. On the other hand, when there is no carrier, the absolute value of the product difference is very close to zero.

As a result, the presence or absence of a carrier can be determined without being affected by noise or the like, as in the case of data demodulation.

Since the circuit shown in FIG. 8 is a digital circuit, it operates in synchronization with the clock signal CK or CK, but the illustration of the clock signal is omitted to simplify the explanation.

In this circuit, the correlation output R is 1 in the latch circuit 51a.
After being latched for a clock period, the signal is converted into an absolute value by an absolute value circuit 52a, and further provided to an adder circuit 55a and a maximum value hold circuit 54a. on the other hand.

A window start pulse WL and a window-stop number pulse WH are input to the window generating circuit 53, and a window signal ws which becomes H level at the W portion is outputted from this circuit 53. This window signal W
S is given as an operation control signal to the latch circuit 48 of the adder circuit 55a and the latch circuit 4B of the maximum value hold circuit 54a.In the adder circuit 55a, the latch circuit 48 operates only in the E section where the window signal WS is at L level.

Latch timing is of course defined by the clock signal. The correlation output R converted into an absolute value, which is inputted sequentially, is added to the previous addition result provided from the latch circuit 48 for each clock signal by the adder 47, and this addition result is latched again by the latch circuit 48. In this way, data representing the total sum AaE is obtained from the adder circuit 55a and is applied to the 9 multiplier 56a.

The latch circuit 4B of the maximum value hold circuit 54a operates only in the W portion where the window signal WS is at H level. The previous maximum value latched in the latch circuit 4B and the absolute value of the correlation value R input this time are compared with a specific aperture amount of 45, and if the current correlation value is larger, this current correlation value is new. The maximum value is latched in the latch circuit 46. In this way, the peak value Pa is output from the maximum value hold circuit 54a.
Data representing w is obtained and applied to 1 multiplier 56b.

The same goes for the other correlation output Rb.

A latch circuit 51b, an absolute value circuit 52b, a maximum value hold circuit 54b, and an adder circuit 55b are provided. Then, the peak value P is obtained from the maximum value hold circuit 54b, and the sum AbE is obtained from the adder circuit 55b, and is applied to the 1 multipliers 56a and 56b.

In the multiplier 56a, the multiplication of P −A is performed by 1 multiplier
In aE 513b, the multiplication of P - A is performed respectively.

ay bE The multiplication result is sent to the comparator 57 and the subtraction/absolute value circuit 59.
are given to each.

The comparator 57 compares the magnitude ratio by aE ay bE of P -A and P -A, outputs a signal representing 1 or O according to the comparison result, and outputs a signal representing 1 or O at the timing of the data interval end signal ED. latched to.

It is output as received data RXD. Addition circuits 55a and 55b are activated by this data section end signal ED.

Maximum value hold circuits 54a and 54b are reset.

On the other hand, in the subtraction/absolute value circuit 59, (P −Aby
aB P - A) is subtracted and converted to its absolute value.

ay bE This calculation result is compared with a threshold Th in the ninth comparator circuit 60, and if it is larger than Th, the carrier detection signal P
AS is output.

(5) Configuration example of synchronous control circuit FIG. 1O shows an example of the configuration of the synchronous control circuit 25.

The synchronous control circuit 25 includes a peak position detection circuit 213A,
Peak position determination circuit 26B, synchronization establishment determination circuit 28.
It includes an out-of-synchronization determination circuit 29 and the like.

The peak position detection circuit 26A is a circuit for detecting at which position within the data interval T the peak of the correlation output is located, and as shown in FIG. 11, the peak position PP is the point at which the maximum value of the correlation output appears. It is measured as the time from to the data section end signal ED.

In this embodiment, the peak position is the position where the absolute value of the sum of the two correlation outputs R and R6 has the maximum value.

The two correlation outputs R and R6 are each given to an adder B1, and after being added, are converted into absolute values in an absolute value circuit B4.

This absolute value signal is applied to one input terminal of comparator 62 and latch circuit 63. When the signal ED indicating the end of the previous data section is applied to the latch circuit 63 as a latch timing signal via the OR circuit 65A, the output of the absolute value circuit 64 is latched as an initial value. The value latched in the latch circuit 63 is given as another input to the comparator 62. Therefore, from then on, the latch circuit 6
3 and the output value of the absolute value circuit 64 are compared sequentially (every clock pulse of the clock signal CK) in the comparator circuit B2, and the output value larger than the latched value is determined as the absolute value. When obtained from the circuit 64, the output of the comparator 62 is given to the latch circuit 63 via the OR circuit 85A, so the output of the absolute value circuit 64 is latched into the latch circuit 63 as a new value. In this way, the maximum value is always latched in the latch circuit B3.

On the other hand, the counter 66 that counts the clock signal CK is
Reset (clear) by data section end signal ED input via R circuit 65B or comparison output of comparator 62
and starts counting again from zero. The count output of the counter 6B is latched by the latch circuit 67 when the next data period end signal ED is applied. The counter 6G counts the clock signal CK from the time when the peak value appears in the data interval T until the time when the signal ED indicating the end of the data interval T is applied. This count value is then latched by the latch circuit 67 and represents the peak position PP.

Data P representing the peak position detected in this way
P is then given to the peak position determination circuit 21iB. This determination circuit 26B determines whether the detected peak position is within the set W section. As described above, in both demodulation processing of received data and carrier detection processing, it is necessary that the correlation peak exists in the W portion, otherwise correct demodulation processing and carrier detection processing cannot be performed.

In the peak position determination circuit 26B, the comparator 68°69
A window type digital comparator circuit is provided, which is composed of an AND circuit 70 and an AND circuit 70.

One comparator 68 contains data representing the start position of the W part, and the other comparator 69 contains data representing the stop (end) position of the W part.
The data representing the positions are set respectively, and only when the data representing the peak position PP is between the start position and the stop position, the AND circuit 70 outputs the peak position determination signal PH of H level. be done.

Next, the configuration and operation of the synchronization establishment circuit including the synchronization establishment determination circuit 28 will be described with reference to FIG.

Two registers 72 and 73 are provided. Data representing the peak position PP is given to the register 72, and data representing (3/2)T-PP is set in this register 72. T is data representing the length (time) of the data section. On the other hand, data T is set in the register 73. The selector 74 selects one of the setting data of these registers 72 and 73 according to the state of the peak position determination signal PH, and applies it to one input of the digital comparator 75.

On the other hand, the counter 71 counts the clock signal CK and provides the count output to the other input of the digital comparator 75. Comparator 75 generates a data period end signal (match signal) ED when the count value of counter 71 becomes equal to the setting data applied through selector 74. The counter 71 is reset by this signal ED and starts counting again from zero.

Now, since the correlation output and the data section are not synchronized when the power is turned on, there may be no correlation peak in the W section. At this time, the peak position determination signal PH becomes L level, and the selector 74 selects the setting data of the register 72 and supplies it to the comparator 75. This configuration data (
3/2) T-PP.

The primary data interval end signal ED is set so that the length (time) from the next peak to the next data interval end signal is T/2.
It is intended to generate. In this way, when the peak position is located within the W section, the peak position determination signal PH becomes H level, and the selector 74
Since the setting data T of No. 3 is selected, the data section end signal ED will be generated at the period T from then on.

Synchronization is said to be established when a state in which the peak position exists within the W part of the data interval continues for a predetermined number of times. The counter 82 is set to a clock enable state by the H level peak position determination signal PH inputted through the AND gate 81, and counts the inputted data section end signal ED. This counter 82 outputs NO when the signal PH is at L level.
It is reset by this L level signal via a T circuit 84 and an OR circuit 85. The count output of the counter 82 is given to a digital comparator 83. On the other hand, this comparator 8
3 is set as a predetermined number of times X at which it should be determined that synchronization has been established. When the count value of the counter 82 reaches this X, a match signal is generated from the comparator 83, the flip-flop 19 is set, and the synchronization establishment circuit DSR (L level) is output. The match signal from comparator 83 passes through OR circuit 85 and resets counter 82 . In addition, the synchronization establishment signal D
Since the AND gate 81 is closed by SR, the peak position determination signal PH is no longer input.

Note that if the peak position determination signal PH becomes L level even once while the counter 82 is counting the signals ED, the counter 82 is reset, so when the signal PH is at the H level, X signals ED are counted. It is determined that synchronization has been established only if the input is continuous. When the signal PH is at the L level before it is determined that synchronization is established, the selector 74 selects the register 72 as described above, and the generation timing of the data section end signal ED is adjusted again.

The out-of-synchronization determination circuit 29 determines that out-of-synchronization occurs when the carrier detection signal PAS is not continuously output over a predetermined plurality (Y times) of data sections.

Referring to FIG. 13, once synchronization is established, NAND gate 91 is opened by synchronization establishment signal DSR at L level. If a carrier is detected, carrier detection signal PAS is at H level. When the carrier is no longer detected, the carrier detection signal PAS becomes L level, and the NAND
Through gate 91.

An H level enable signal is applied to the clock enable terminal CE of the counter 92. The counter 92 is activated by the NAND gate 91 in response to the H level carrier detection signal PAS.
．． It has already been reset via the N, OT circuit 94 and 0R95. When the counter 92 is enabled, it counts the input data period end signal ED and provides the counted value to the digital comparator 93. Data representing a predetermined number Y is set in advance in this comparator 93. Therefore, when the count value of the counter 92 reaches Y, a match signal is generated from the comparator 93, the flip-flop 19 is reset, and the synchronization establishment signal DSR becomes H level. NAND gate 91 is closed by signal DSR at H level. Also, by the output signal of the 9 comparator 93, the OR
Counter 92 is reset via circuit 95.

When the carrier detection signal PAS becomes H level while the counter 92 is performing a counting operation, the counter 92 is reset. That is, it is determined that the synchronization is out of synchronization only when a state in which no carrier is detected continues for Y data intervals.

As a result, temporary carrier non-detection due to fluctuations in transmission characteristics of the transmission path, etc., and carrier non-detection due to termination of one communication (
It is possible to clearly distinguish between correct and out-of-synchronization).

FIG. 14 shows another example of the peak position detection circuit 28A and the peak position determination circuit 26B.

In the peak position detection circuit 26A shown in FIG. 10, two correlation outputs R and R1 are added, and the peak position of the absolute value thereof is detected. In the circuit shown in FIG. 14, the peak positions of the correlation outputs R and R6 are detected separately, and their peak values are also detected separately. Then, the peak position of the peak with the largest peak value is determined as the final peak position.

The correlation outputs R, R, are input to maximum value hold (peak value detection) circuits 100a, 100b, respectively. This maximum value hold circuit is compared with Fig. 1θ.
Absolute value circuit 64. Latch circuit 63° comparator 62 and O
It is constituted by an R circuit 85A.

The maximum value for each data section is held in the latch circuit 63. The maximum values (peak values) of these correlation outputs R and R6 for each data section are provided to a comparison circuit 102 and compared.

On the other hand, peak position hold circuits 101a and 101b are provided for each of the two correlation outputs R and R6. These peak position hold circuits are composed of an OR circuit 1i5B, a counter 6B, and a latch circuit 67 in comparison with FIG. The hold peak positions of the peak position hold circuits 101a and 1o1b are given to a changeover switch 103.

The changeover switch 103 selects the peak position of the larger peak value according to the comparison result of the peak values by the comparator 102, and this selected peak position is latched at the time when the data interval end signal ED is output. It is latched into circuit 104.

Compared to the peak position determination circuit shown in FIG. 1θ, the peak position determination circuit shown in FIG. 14 has a comparator 10G added and an AN
D game) 107, 108 are provided. Comparator 10
Data representing the center position of the window portion (W portion) is set in advance in G. Since the detected peak position PP is also given to this comparator 10B, this comparator 10B determines whether the detected peak value fifPP is to the left of the center of the W portion (a portion closer to the start position).
It is determined whether it is on the right side (the part closer to the stop position). If it is on the left side, the AND gate 107 opens and the output of the comparator 68 is output as the left side determination signal.

If it is on the right side, the output of the comparator 69 is output through the AND gate 108 as the right side determination signal Rh. Also, these signals R and Rh are OR circuits! 09, the OR circuit 109 outputs a signal C4 corresponding to the peak position determination signal PH. This signal C5 is given to the synchronization establishment determination circuit.

Effects of the Invention According to the present invention, a correlation peak of a correlation signal between a received signal and a code sequence of a predetermined code length is detected, and the position of this correlation peak within a data interval of a cycle corresponding to the code length is detected. Then, it is determined whether this peak position is within the observation interval set within the data interval. Therefore, based on this determination result, it becomes possible to perform synchronization establishment processing to set the data interval so that the peak position always exists within the observation interval, and correct demodulation of data in the receiving device is achieved. In particular, in this invention, an observation interval with a certain width is set within the data interval, and it is determined whether a peak position exists within this observation interval.

Some fluctuations in the peak position are allowed, and changes in the transmission characteristics of the transmission path can be adequately coped with.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the overall configuration of a C8K communication system. FIG. 2 is a circuit diagram showing an example of the configuration of the modulation device, and FIG. 3 is a time chart showing its operation. FIG. 4 is a circuit diagram showing another example of the modulation device. FIG. 5 is a circuit diagram showing an example of the configuration of a pair of correlators. FIG. 6 is a circuit diagram showing a modification thereof, and FIG. 7 is a circuit diagram showing another example of the configuration of the correlator. FIG. 8 is a circuit diagram showing an example of the configuration of the demodulator, and FIG. 9 is a waveform diagram showing its operation. FIG. 10 is a circuit diagram showing a configuration example of a synchronous control circuit. FIG. 11 is a waveform diagram showing the peak position detection operation, FIG. 12 is a waveform diagram showing the synchronization establishment determination operation, and FIG. 13 is a waveform diagram showing the synchronization loss determination operation. FIG. 14 is a circuit diagram showing another example of the peak position detection circuit and the peak position determination circuit. 15 and 16 show a conventional SS communication system, FIG. 15 is a circuit diagram showing the configuration, and FIG. 18 is a time chart showing its operation. 26A...Peak position detection circuit. 213B...Peak position determination circuit. that's all

Claims (2)

[Claims] (1) A peak position detection circuit that detects a correlation peak of a correlation signal between a received signal and a code sequence of a predetermined code length, and detects the position of this correlation peak within a data interval with a cycle corresponding to the code length, and detection A peak position determination device for a correlation signal, comprising: a peak position determination circuit that determines whether a peak position is within an observation interval set within the data interval. (2) Claim (1), wherein the peak position determination circuit determines whether the detected peak position is located before or after the center of the observation interval, in addition to determining whether the detected peak position is within the observation interval. A peak position determining device for a correlation signal according to.