JPH02246111A - Plasma treatment device - Google Patents
Plasma treatment deviceInfo
- Publication number
- JPH02246111A JPH02246111A JP1066525A JP6652589A JPH02246111A JP H02246111 A JPH02246111 A JP H02246111A JP 1066525 A JP1066525 A JP 1066525A JP 6652589 A JP6652589 A JP 6652589A JP H02246111 A JPH02246111 A JP H02246111A
- Authority
- JP
- Japan
- Prior art keywords
- substrates
- substrate
- susceptor
- plasma
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000009832 plasma treatment Methods 0.000 title claims abstract 4
- 239000000758 substrate Substances 0.000 claims abstract description 72
- 238000006243 chemical reaction Methods 0.000 claims abstract description 27
- 239000000463 material Substances 0.000 claims description 3
- 238000000576 coating method Methods 0.000 abstract description 3
- 230000015572 biosynthetic process Effects 0.000 abstract description 2
- 239000011248 coating agent Substances 0.000 abstract description 2
- 239000010408 film Substances 0.000 description 24
- 239000010409 thin film Substances 0.000 description 9
- 239000004065 semiconductor Substances 0.000 description 7
- 238000009826 distribution Methods 0.000 description 6
- 239000011521 glass Substances 0.000 description 6
- 238000000034 method Methods 0.000 description 5
- 239000013078 crystal Substances 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 239000012808 vapor phase Substances 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 238000009412 basement excavation Methods 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005755 formation reaction Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 239000012071 phase Substances 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 229910001220 stainless steel Inorganic materials 0.000 description 1
- 239000010935 stainless steel Substances 0.000 description 1
Classifications
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
Landscapes
- Drying Of Semiconductors (AREA)
- Photovoltaic Devices (AREA)
Abstract
Description
【発明の詳細な説明】
(イ)発明の利用分野
本発明は珪素を主成分としたアモルファス及び多結晶の
非単結晶半導体からなる光電変換装置または珪素を主成
分とする非単結晶半導体からなる薄膜電界効果トランジ
スタ等大型基板上の素子形成に応用することができるプ
ラズマ処理装置に関するものである。Detailed Description of the Invention (a) Field of Application of the Invention The present invention relates to a photoelectric conversion device made of an amorphous or polycrystalline non-single crystal semiconductor mainly composed of silicon, or a non-single crystal semiconductor mainly composed of silicon. The present invention relates to a plasma processing apparatus that can be applied to forming elements such as thin film field effect transistors on large substrates.
(ロ)従来の技術
プラズマ化学気相堆積法(以下プラズマ処理装置という
)により形成される珪素を主成分とした非単結晶半導体
薄膜や酸化珪素、窒化シリコン等の絶縁体薄膜は、太陽
電池、イメージセンサ等の光電変換装置、液晶表示装置
等に使用する薄膜電界効果トランジスタなどの材料とし
て巾広く応用されている。これらの電子装置は性質の異
なる複数の薄膜を積層したものから構成され、これらの
装置の大型化および低価格化に伴い、これら積層膜を工
業的に大面積にかつ大量に作製する目的で行われていた
従来のプラズマ処理装置を以下に示す。(b) Conventional technology Non-single-crystal semiconductor thin films mainly composed of silicon and insulator thin films such as silicon oxide and silicon nitride formed by plasma chemical vapor deposition (hereinafter referred to as plasma processing equipment) are used for solar cells, It is widely applied as a material for photoelectric conversion devices such as image sensors, thin film field effect transistors used in liquid crystal display devices, etc. These electronic devices are composed of laminated layers of multiple thin films with different properties, and as these devices become larger and lower in price, efforts are being made to industrially manufacture these laminated films over large areas and in large quantities. The conventional plasma processing equipment is shown below.
第2図に最も一般的な平行平板電極を用いたプラズマC
VD装置の概略断面図を示す。Figure 2 shows plasma C using the most common parallel plate electrodes.
A schematic cross-sectional view of a VD device is shown.
この場合、1つの真空予備室(26)と1つの反応室(
23)が示されている。基板(1)は基板支持体(21
)上に設置され、支持体(21)と−緒に仕切り弁(2
2)を通じて反応室(23)へ搬送される。該反応室(
23)にて基板(1)はヒーター(24)により加熱さ
れ、所定の温度に達した後、放電電極(25)により反
応性気体を分解、活性化させて基板上に薄膜を形成する
ものである。In this case, one vacuum pre-chamber (26) and one reaction chamber (
23) is shown. The substrate (1) is attached to the substrate support (21
), and the gate valve (2) is installed together with the support (21).
2) to the reaction chamber (23). The reaction chamber (
In step 23), the substrate (1) is heated by a heater (24), and after reaching a predetermined temperature, the reactive gas is decomposed and activated by a discharge electrode (25) to form a thin film on the substrate. be.
この方式は図より明らかな如く、基板と電極とが平行で
あるので、大面積基板上に薄膜を形成する際には電極面
積を大きくする必要があった。As is clear from the figure, in this method, the substrate and the electrodes are parallel, so when forming a thin film on a large-area substrate, it was necessary to increase the area of the electrodes.
さらに−回の薄膜形成工程にて電極面積にほぼ等しいだ
けの面積にしか形成できないため、基板の大量処理には
不十分であった。Furthermore, since the thin film can be formed only in an area approximately equal to the electrode area in the second thin film forming process, it is insufficient for processing a large amount of substrates.
これらを解決する1つの方法として、本出願人らによる
プラズマ気相反応装置(特願昭59−79623)があ
る、この装置反応室の概略断面図を第3図に示す。As one method for solving these problems, there is a plasma gas phase reactor (Japanese Patent Application No. 59-79623) proposed by the present applicant, and a schematic sectional view of the reaction chamber of this device is shown in FIG.
図面のように、平行平板電極(31)間に被膜形成用基
板(1) ?jl数枚を電極に対し垂直となるように配
設し、−度の処理にて従来の10倍以上の基板処理枚数
を達成し、同時に装置の床面積は従来の装置とほぼ同等
であった。上下の放電電極(31)間隔を広げていくに
従い、より大きい基板上に被膜を作製することが可能と
なるが、実際は上下の電極間隔が広くなるに従い、プラ
ズマ放電が不安定となるので、通常は電極の一辺の二倍
以内にその電極間隔をとっている。このような大面積、
大量基板処理のプラズマ気相反応法にもいくつかの欠点
が存在する。As shown in the drawing, the film forming substrate (1) is placed between the parallel plate electrodes (31)? By arranging several substrates perpendicular to the electrodes, we were able to process more than 10 times as many substrates as before, and at the same time, the floor space of the equipment was almost the same as the conventional equipment. . As the distance between the upper and lower discharge electrodes (31) increases, it becomes possible to produce a film on a larger substrate, but in reality, as the distance between the upper and lower electrodes (31) increases, plasma discharge becomes unstable. The electrode spacing is within twice the length of one side of the electrode. Such a large area,
Plasma vapor phase reaction methods for bulk substrate processing also have some drawbacks.
即ち、電極間の距離が相当長いため、基板上に形成され
た被膜は特定の製膜条件の場合以外は電極間方向に膜厚
分布を持ってしまう。その様子を第4図(^)、 (B
) 、 (C) 、 (D)に示す。これは第3図のプ
ラズマ気相反応装置にて非単結晶珪素半導体を硝子基板
上に作製した場合の被膜の付き方の概略図を示す、第4
図(A)のIの領域で示すように、反応圧力が高めで高
周波電力の投入電力が低い場合は、第4図(B)に示す
ように基板の電極方向の上部及び下部に形成される被膜
が多くなり、このような膜厚分布を有する。この被膜を
作製中、プラズマ反応を行っている反応室内のプラズマ
発光領域は、上下の電極近傍に集まっているのが観察さ
れた0次に反応圧力が低く、高周波電力の投入電力が高
い場合は、第4図(^)の■の領域、第4図(0)のよ
うに基板の電極方向に対し中央部付近に形成される被膜
が多く、このような膜厚分布を有する。That is, since the distance between the electrodes is quite long, the film formed on the substrate has a film thickness distribution in the direction between the electrodes except under specific film forming conditions. The situation is shown in Figure 4 (^), (B
), (C), and (D). This is the fourth diagram showing a schematic diagram of how a film is formed when a non-single crystal silicon semiconductor is produced on a glass substrate using the plasma vapor phase reactor shown in Figure 3.
As shown in area I in Figure 4(A), when the reaction pressure is high and the input power of high-frequency power is low, formations are formed on the upper and lower parts of the substrate in the direction of the electrodes as shown in Figure 4(B). The number of coatings increases and the film thickness distribution is like this. During the production of this film, the plasma emission region in the reaction chamber where the plasma reaction is occurring was observed to be concentrated near the upper and lower electrodes. , the area marked ■ in FIG. 4(^), and the coating formed near the center of the substrate in the direction of the electrodes, as shown in FIG. 4(0), are often formed and have such a film thickness distribution.
また狭い範囲ではあるが、第4図(^)の領域■では第
4図(C)に示すようなほぼ均一な膜厚分布を得ること
が可能であった。Furthermore, although it was a narrow range, it was possible to obtain a substantially uniform film thickness distribution as shown in FIG. 4(C) in region (2) of FIG. 4(^).
このように大面積基板上において不均一な膜厚分布を有
すると同一基板上に構成される各半導体素子の特性、特
に物理的及び電気的特性にひどいばらつきを生じ、大面
積基板上にTPTや光電変換装置を作製しても工業的な
価値はなかった。Such non-uniform film thickness distribution on a large-area substrate causes severe variations in the characteristics, especially the physical and electrical characteristics, of each semiconductor element configured on the same substrate, and it is difficult to Even if a photoelectric conversion device was produced, it had no industrial value.
(ハ)発明の目的
本発明は、前記の従来法の欠点を補うものであり、大量
の大面積基板上に均一な膜厚分布を有する被膜を幅広い
条件下で作製する装置に関する。(c) Object of the Invention The present invention compensates for the drawbacks of the conventional method described above, and relates to an apparatus for producing a film having a uniform thickness distribution on a large number of large-area substrates under a wide range of conditions.
(ニ)発明の構成
本発明は前述の問題を解決するプラズマ処理装置に関す
るものであり、反応室内壁と放電用電極(3)の間に一
対の電極シールド(4)を設け、前記電極シールド(4
)は、放電用電極(3)間にこの電極とは非平行な状態
で複数の基板(1)を配置するための基板サセプター(
5)とで閉空間を形成し、この基板サセプターは一方向
に可動でき、反応室内の所定の位置に設置された際に前
述の電極シールドと閉空間を形成するものであります。(d) Structure of the Invention The present invention relates to a plasma processing apparatus that solves the above-mentioned problems, and includes a pair of electrode shields (4) provided between the inner wall of the reaction chamber and the discharge electrode (3), and the electrode shield ( 4
) is a substrate susceptor (1) for arranging a plurality of substrates (1) between discharge electrodes (3) in a non-parallel manner with these electrodes.
5) to form a closed space, this substrate susceptor can move in one direction, and when installed at a predetermined position in the reaction chamber, forms a closed space with the electrode shield mentioned above.
このような構成によって、一対の放電電極及び複数の基
板は、すべて電極シールドと基板サセプターによって取
り囲まれており、プラズマ放電もこれら取り囲まれた空
間より外部にもれず各基板間にも、はぼ等しい密度のプ
ラズマ雰囲気が形成され、大面積基板においても均一性
のよい被膜成形が可能となるものである。With this configuration, a pair of discharge electrodes and a plurality of substrates are all surrounded by an electrode shield and a substrate susceptor, and plasma discharge does not leak outside of these enclosed spaces and is distributed almost equally between each substrate. A dense plasma atmosphere is formed, making it possible to form a film with good uniformity even on large-area substrates.
また、基板サセプターは、一方向に可動可能で、かつ所
定の位置では、電極シールドと閉空間を形成する。この
ため複数の基板が保持されたサセプターをプラズマ処理
の前後で移動させることで、プラズマ処理を連続的に行
なえるという特徴を持つ。Further, the substrate susceptor is movable in one direction and forms a closed space with the electrode shield at a predetermined position. Therefore, by moving a susceptor holding a plurality of substrates before and after plasma processing, plasma processing can be performed continuously.
この電極シールドと基板サセプターの構造の一例を第1
図示す。An example of the structure of this electrode shield and substrate susceptor is shown in the first example.
Illustrated.
第1図(A)においては基板サセプター(5)は図面の
右方向に可動でき、電極シールド(4)とで閉空間を構
成する。In FIG. 1(A), the substrate susceptor (5) is movable to the right in the drawing, and forms a closed space with the electrode shield (4).
この基板サセプター(5)と、電極シールド(4)との
重なり部分は同図(B)にその拡大概略図が示してあり
、このような構造をとって基板サセプターは可動し、電
極シールドと閉空間を構成する。An enlarged schematic view of the overlapping portion of the substrate susceptor (5) and the electrode shield (4) is shown in Figure (B). With this structure, the substrate susceptor is movable and close to the electrode shield. Configure space.
また、第5図にその他の電極シールドと基板サセプター
との組み合わせ例を示す。Further, FIG. 5 shows examples of combinations of other electrode shields and substrate susceptors.
本発明においては特にこれらに示した構造のみに限定さ
れることなく、その他の構造でも本発明の思想を反映さ
せることが可能である。The present invention is not particularly limited to the structures shown above, and the idea of the present invention can be reflected in other structures.
以下に実施例を示し本発明を説明する。The present invention will be explained below with reference to Examples.
r実施例」
本実施例においては、第6図に示すプラズマ気相反応装
置を使用し、硝子基板上に非単結晶半導体被膜を形成し
た。同図において、300mm X 400mmの大き
さのガラス基板(1)を電極に対して垂直に配置するよ
うに基板サセプター(5)にセツティングする。本実施
例の場合、同サセプター(5)に硝子基板(1)を10
枚装着しであるが、硝子基板(1)の向かい合う間隔が
201以上であれば放電が再現性よく発生し、より多く
の基板上に被膜形成は可能であるが、基板上の膜厚の均
一性を考えるならば、本実施例の場合、10〜15枚程
度が良い。面この基板間隔は、被膜作製時の圧力等他の
要素によって変化するので、−に固定することは適当で
はない。r Example In this example, a plasma vapor phase reaction apparatus shown in FIG. 6 was used to form a non-single crystal semiconductor film on a glass substrate. In the figure, a glass substrate (1) with a size of 300 mm x 400 mm is set on a substrate susceptor (5) so as to be arranged perpendicularly to the electrodes. In the case of this example, ten glass substrates (1) are placed on the same susceptor (5).
However, if the distance between the glass substrates (1) facing each other is 20 mm or more, discharge will occur with good reproducibility, and it will be possible to form a film on more substrates, but the film thickness on the substrates will not be uniform. Considering the performance, in the case of this embodiment, about 10 to 15 sheets is good. It is not appropriate to fix the plane to - because the distance between the substrates changes depending on other factors such as the pressure during film production.
また、電極シールド(4)と基板サセプター(5)は、
第1図に示す構造を有しており、これら電極シールド、
基板サセプターは金属材料であるニッケル。In addition, the electrode shield (4) and the substrate susceptor (5) are
It has the structure shown in Figure 1, and these electrode shields,
The substrate susceptor is made of nickel, a metal material.
ステンレス、アルミニュームやセラミックス等の表面に
導電材料を形成した物が使用可能である。It is possible to use stainless steel, aluminum, ceramics, etc. with a conductive material formed on the surface.
本実施例ではこれらを10m1φのパンチング穴加工が
なされたアルミニューム材で構成した。このパンチング
による穴は反応性気体の流れをよくする為と初期排気の
時間短縮の為に設けたものであるがこのパンチングの穴
よりプラズマが漏れることは無かった。In this embodiment, these are made of aluminum material with punched holes of 10 m1φ. This punched hole was provided to improve the flow of reactive gas and to shorten the initial exhaust time, but no plasma leaked through this punched hole.
さらに本実施例では、電極シールドと基板サセプターを
接地し、より均一なプラズマが放電電極間のみに発生す
るようにした。これにより各基板は、より均一なプラズ
マ雰囲気下に置かれることになった。Furthermore, in this example, the electrode shield and the substrate susceptor were grounded so that more uniform plasma was generated only between the discharge electrodes. As a result, each substrate was placed under a more uniform plasma atmosphere.
この硝子基板がセットされたサセプター(5)を予備室
(62)よりプラズマ反応室に入れ、真空排気を行った
後、ゲイト弁(63)を開き、搬送機構(図示せず)に
より第1の反応室(64)へ移動した後、図では描けな
いので省略しであるが、第6図の紙面と平行で手前側と
奥側にある基板加熱用ヒーターにより被膜形成温度であ
る200〜300℃程度にまで加熱できる。The susceptor (5) with the glass substrate set thereon is put into the plasma reaction chamber from the preliminary chamber (62), and after evacuation is performed, the gate valve (63) is opened, and the first After moving to the reaction chamber (64), the heaters for heating the substrate located on the front and back sides parallel to the paper surface of Fig. 6 are heated to a film forming temperature of 200 to 300°C, although they are not shown in the figure. It can be heated to a certain degree.
この状態で反応室(64)内にシランガスを50SCC
Hの流量で導入し排気系のコンダクタンスを制御して反
応室内圧力を0.01〜0.1torrに保持できる。In this state, 50 SCC of silane gas is added into the reaction chamber (64).
By introducing H at a flow rate and controlling the conductance of the exhaust system, the pressure inside the reaction chamber can be maintained at 0.01 to 0.1 torr.
次に、上下の平行平板電極(61)間に13.56M1
lzの高周波電力を印加し、プラズマ放電は上下の電掘
シールド(4)及び基板支持サセプター(5)の側面に
て構成される空間中に閉じ込められ、反応室(@の内壁
まで到達はしていない。よって形成される被膜も、前記
の空間内部にしか形成されず、反応室内壁をクリーニン
グする必要がないか、またはクリーニングの回数を非常
に少なくすることが可能となっている。Next, 13.56M1 is placed between the upper and lower parallel plate electrodes (61).
A high-frequency power of 1z is applied, and the plasma discharge is confined in the space formed by the upper and lower electric excavation shields (4) and the side surfaces of the substrate support susceptor (5), and does not reach the inner wall of the reaction chamber (@). Therefore, the film formed is only formed inside the above-mentioned space, and there is no need to clean the inner wall of the reaction chamber, or the number of times of cleaning can be greatly reduced.
本発明の装置を用いて、300+u+ X 400a+
mの基板上にP、1.N構造を有する太陽電池(素子面
積1.05cm”)を500個作製した。その特性を以
下の表1に示す。Using the device of the present invention, 300+u+ X 400a+
P on the substrate of m, 1. 500 solar cells having an N structure (element area: 1.05 cm") were manufactured. Their characteristics are shown in Table 1 below.
表に
のように、光電変換効率のばらつきが非常に小さくなっ
ている。これは特にPIN型太陽電池の夏型半導体層の
膜厚のばらつきが非常に少ないことと深い関係があるた
めである。As shown in the table, the variation in photoelectric conversion efficiency is extremely small. This is particularly because there is a deep relationship with the extremely small variation in film thickness of the summer type semiconductor layer of the PIN type solar cell.
(ホ)効果
本発明の構成によりプラズマ発生空間を基板が置かれた
電極間のみに限定でき、より均一なプラズマを発生でき
た。(e) Effects With the configuration of the present invention, the plasma generation space can be limited to only between the electrodes where the substrate is placed, and more uniform plasma can be generated.
また、このようなプラズマ発生空間を限定でる基板サセ
プターは移動可能であるため、大量の基板を連続的に処
理できた。Furthermore, since the substrate susceptor that limits the plasma generation space is movable, a large amount of substrates can be continuously processed.
また、本発明の装置を用いて被膜を作製すると、大面積
基板上に非常に均一な被膜を形成することが可能となる
。これにより大面積基板よりとり出せる素子数が増加し
、さらにその特性も均一なものが得られるようになる。Moreover, when a film is produced using the apparatus of the present invention, it becomes possible to form a very uniform film on a large-area substrate. This increases the number of elements that can be taken out from a large-area substrate, and also makes it possible to obtain uniform characteristics.
また大面積の素子、例えば太陽電池等は、基板上の膜質
が均一となるので、全体として特性の向上が得られる。Furthermore, in large-area devices such as solar cells, the quality of the film on the substrate is uniform, so that overall characteristics can be improved.
第1図及び第5図は本発明の電極シールドと基板サセプ
ターの組み合わせの様子を示す。
第2図は従来のプラズマCVD装置を示す。
第3図は本発明で用いたプラズマCVD装置を示す。
第す凶は不兄明U市処理製直。
・基板
・電極
・電極シールド
・基板サセプター1 and 5 show the combination of the electrode shield and substrate susceptor of the present invention. FIG. 2 shows a conventional plasma CVD apparatus. FIG. 3 shows a plasma CVD apparatus used in the present invention. The worst part is that it is directly manufactured by Fuenai U City.・Substrate, electrode, electrode shield, substrate susceptor
Claims (1)
極間に複数の基板の表面を前記電極とは平行でない位置
に配置し、前記複数の基板上にプラズマ処理を行うプラ
ズマ処理装置であって、前記反応室の内壁と、前記電極
の間に設けられた一対の電極シールドと、前記複数の基
板を保持するサセプターとは閉空間を構成し、前記閉空
間内には前記電極と前記複数の基板が設けられており、
前記電極によって発生されるプラズマは前記閉空間内の
みに存在し、前記サセプターは一方向に引き出し可能な
ことを特徴とするプラズマ処理装置。 2、減圧状態に保持可能な反応室内の一対の平行平板電
極間に複数の基板の表面を前記電極とは平行でない位置
に配置し、前記複数の基板上にプラズマ処理を行なうプ
ラズマ処理装置であって、前記複数の基板を保持するサ
セプターを所定の方向より移動させて所定の位置に配置
することにより、前記反応室の内壁と前記電極の間に設
けられた一対の電極シールドと、前記サセプターとによ
って、プラズマを閉じ込める空間を構成するプラズマ処
理装置。 3、特許請求の範囲第1項および第2項において、前記
電極シールドと前記サセプターは導電性表面を有する材
料よりなり、それぞれは反応室と同様に接地されている
ことを特徴とするプラズマ処理装置。[Claims] 1. Plasma treatment is performed on the plurality of substrates by arranging the surfaces of the plurality of substrates between a pair of parallel plate electrodes in a reaction chamber that can be maintained in a reduced pressure state at positions not parallel to the electrodes. In the plasma processing apparatus, an inner wall of the reaction chamber, a pair of electrode shields provided between the electrodes, and a susceptor that holds the plurality of substrates constitute a closed space, and in the closed space, is provided with the electrode and the plurality of substrates,
A plasma processing apparatus characterized in that plasma generated by the electrode exists only in the closed space, and the susceptor can be drawn out in one direction. 2. A plasma processing apparatus in which the surfaces of a plurality of substrates are arranged at positions not parallel to the electrodes between a pair of parallel plate electrodes in a reaction chamber that can be maintained in a reduced pressure state, and plasma processing is performed on the plurality of substrates. By moving the susceptor holding the plurality of substrates from a predetermined direction and placing it at a predetermined position, a pair of electrode shields provided between the inner wall of the reaction chamber and the electrodes and the susceptor A plasma processing device that creates a space that confines plasma. 3. A plasma processing apparatus according to claims 1 and 2, characterized in that the electrode shield and the susceptor are made of a material having a conductive surface, and each is grounded similarly to the reaction chamber. .
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1066525A JP2562686B2 (en) | 1989-03-18 | 1989-03-18 | Plasma processing device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1066525A JP2562686B2 (en) | 1989-03-18 | 1989-03-18 | Plasma processing device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH02246111A true JPH02246111A (en) | 1990-10-01 |
JP2562686B2 JP2562686B2 (en) | 1996-12-11 |
Family
ID=13318378
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1066525A Expired - Fee Related JP2562686B2 (en) | 1989-03-18 | 1989-03-18 | Plasma processing device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2562686B2 (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05144748A (en) * | 1991-11-22 | 1993-06-11 | Semiconductor Energy Lab Co Ltd | Plasma treatment apparatus |
JPH07122502A (en) * | 1993-10-21 | 1995-05-12 | Nec Corp | Plasma machining device |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60111415A (en) * | 1983-11-22 | 1985-06-17 | Semiconductor Energy Lab Co Ltd | Plasmic vapor-phase reaction equipment |
JPS60213020A (en) * | 1984-04-07 | 1985-10-25 | Konishiroku Photo Ind Co Ltd | Glow discharge decomposition device |
JPS63237409A (en) * | 1987-03-25 | 1988-10-03 | Shimadzu Corp | Plasma cvd system |
-
1989
- 1989-03-18 JP JP1066525A patent/JP2562686B2/en not_active Expired - Fee Related
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60111415A (en) * | 1983-11-22 | 1985-06-17 | Semiconductor Energy Lab Co Ltd | Plasmic vapor-phase reaction equipment |
JPS60213020A (en) * | 1984-04-07 | 1985-10-25 | Konishiroku Photo Ind Co Ltd | Glow discharge decomposition device |
JPS63237409A (en) * | 1987-03-25 | 1988-10-03 | Shimadzu Corp | Plasma cvd system |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05144748A (en) * | 1991-11-22 | 1993-06-11 | Semiconductor Energy Lab Co Ltd | Plasma treatment apparatus |
JPH07122502A (en) * | 1993-10-21 | 1995-05-12 | Nec Corp | Plasma machining device |
Also Published As
Publication number | Publication date |
---|---|
JP2562686B2 (en) | 1996-12-11 |
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