JPH02246091A - Semiconductor storage device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Summary of the Invention] Regarding divided wiring for reducing the chip area of a semiconductor memory device, in particular, for the purpose of reducing the data bus width and the sense amplifier drive signal line width, a plurality of word lines are provided. In a semiconductor memory device that has a bit line, a row of sense amplifiers provided for each bit line, and a data bus line running parallel to each sense amplifier row, the data bus line is divided in the direction of the sense amplifier rows to create a plurality of independent Each group is connected to a second data bus extending over the cell array or over the cell array and the sense amplifiers in a direction orthogonal to the sense amplifier array.

(Industrial Application Field) The present invention relates to a semiconductor memory device, particularly to a divided wiring for reducing the chip area thereof.

In recent semiconductor memory devices, as the bit capacity increases, it is desired to reduce the area required for each part. Although miniaturization is effective in reducing the required area, efficient wiring is also important.

(Prior art) Semiconductor storage devices use word lines, bit lines, data buses,
A large capacity memory uses a large number of wiring such as a sense amplifier drive line, a column selection line, a power supply line, etc., and the number of these wirings becomes enormous as the capacity memory becomes larger, and they cannot be accommodated in one layer and are multilayered.

Figure 5 shows a conventional example.WL running vertically is a word line, BL running horizontally, BL is a bit line, and there are many of these, and a memory is placed at the intersection of each word line and bit line. A cell MC is provided. A pair of bit lines BL, B
Block L, its memory cell MC, line SA, etc.
, MQI, -..., these are arranged in a vertical direction (M 00 ).

Mo1. ...), and the same items are also arranged horizontally (Moo and MIO, etc.). Since these have the same configuration, only M00 and MIO are shown in detail in the figure, and the others are omitted. Data buses DB2. DB3 runs, column game) G2,0
3, the bit lines BL, BL are connected to data buses DB2, D
Connected to the corresponding pair of B3. This memory is of a 4-bit simultaneous read type, and, for example, four blocks of BL of MDO'=M03 are connected to corresponding lines of eight data buses DB2 through column gates. data bus D
The data read out to B2 is latched by the data latch DL, passed through the gate G1, and then taken out to the outside through eight data buses DB running in the horizontal direction.

Lines J, 72 running in the vertical direction are sense amplifier drive signal lines, and E! is connected to the power supply Vce line through the gate (GIO), and I12 is connected to the power supply Vss line through the gate (GIO) to control the operation/non-operation of the sense amplifier. Game)G
4 and G6, G6 and G7 are cut gates, Ql and G2
And G3 and G4 are bit line BL, short circuit (reset) transistors of B, 15 and ffi? , is the transistor on/off signal line i6. io is a power supply line for the bit line and seat. The same applies to other blocks. The X decoder 10 performs word line selection,
The Y decoder 20 selects bit lines, in this example, selects four pairs at a time, and DR is a gate driver.

The memory cells are on the left and right of the sense amplifier, but when selecting the left memory cell, the right cut gate G6,
The right memory cell group is separated by G7, and when selecting the right memory cell, the left memory cell group is separated by the left cut gate.

Bit lines are generally constructed from polycrystalline silicon and a diffusion layer formed in a substrate. The word line, together with the gate of the memory cell transistor, is made of polycrystalline silicon and is lined with metal (aluminum) wiring to reduce resistance. The cell is
In the case of a stack type, it is composed of two layers of polycrystalline silicon. Note that the memory in this example has seven layers of wiring including four layers of polysilicon, two layers of aluminum, and a diffusion layer. Data buses DB2, DB3, etc. running in the vertical direction and column selection lines 13 running in the horizontal direction
．． For 14th grade, use the 1st and 2nd layers of aluminum 2-layer wiring,
Column selection lines 13, 14, etc. are left and right blocks M o
It is shared by O, M, 10, etc. to reduce the required area.

[Problem to be solved by the invention]

However, in the semiconductor memory device shown in FIG. 5, data buses DB2. 8 DB3 each (
(4 pairs), and even if the pitch is 3 μm, 4 pairs x 2 x 3
μm-24 μm is required. Large capacity e.g. 16MDR
In AI'l, as shown in FIG. 4, 16 IM cell blocks are arranged in parallel, and each block consists of 2 sense amplifier rows and 512 cell blocks placed on the left and right sides of the rows of sense amplifiers. If there are 16 sets of 24 μm wide data buses, the total will be 24 μm×16-384 μm, and the required area will be considerably large.

In addition, the sense amplifier is connected to a power source V through a pair of lines (sense amplifier drive signal line) running in the direction of the sense amplifier column and the gate.
ccSvss, but in every second row of sense amplifiers, the current flowing through the chain line becomes large, and if the current density in the wiring is considered, the line width is about 40 μm. In Figure 4, there are 16 pairs, so the total is 40μmX2X16
-1280 μm, which requires a considerable area.

The present invention is an attempt to improve these points, and aims to reduce the data bus width and the sense amplifier drive signal line width.

[Means to solve the problem]

As shown in FIG. 1, in the present invention, a data bus bear running parallel to the sense amplifier array is divided to form multiple independent groups of DB 21.
and DB22 < DB31 and DB32. These data buses DB21, DB31 *DB22
, DB 32 are interconnections (second data buses) I1, II2, and I1 extending on the cell array or on the cell array and the sense amplifiers in the horizontal direction (direction perpendicular to the sense amplifier array).
121 and 122 to input and output data to and from the outside.

Furthermore, the sense amplifier drive signal lines 11 and z2 running in the direction of the sense amplifier columns are connected to horizontal wiring lines 131 and z2 at multiple locations.
132, l141 and 142 provide power supply V ss,
For example, if the sense amplifier row includes 2 sense amplifiers, divide it into 2 groups of IK sense amplifiers each, and connect the sense amplifier drive signal lines trt and 12 of each group to wiring l13.
1 and 132. Power supply V ss by l141 and 142,
Connect to Vcc.

[For production]

In this way, it is possible to reduce the data bus width.
For example, if this memory is a 4-bit simultaneous read type as shown in FIG. 5, and the data buses DB2 and DB3 each consist of eight lines, it is divided into two as shown in FIG. and D'B
22, DB 31 and DB 32, each needs to receive 2 bits, so these DB21, DB
22 , . . . need only 4 pieces each.

Thereby, the required area can be reduced to 1/2.

It is also possible to reduce the line width of the sense amplifier drive signal lines 11 and 12. For example, if the sense amplifier row is divided into two and each
If only K sense amplifiers are included, the number of signal lines 1. ．． Since the current flowing through 12 is halved, the line width can also be halved, thereby making it possible to halve the required area.

The sense amplifier drive signal line can be divided to make each part independent, and power can be supplied to each independent part from each horizontal wiring, or alternatively, as shown in the figure, power can be supplied from multiple locations without being divided. The effect is similar.

〔Example〕

FIG. 2 shows an embodiment of the present invention. As in all figures, parts similar to those in other figures are given the same reference numerals.

This memory is also the 16MDRAM shown in FIG. 4, and has two sense amplifier columns, but in this example, it is divided into two columns each having IK sense amplifiers. As expected, it is a 4-bit simultaneous read type, so there are 8 data buses.
Books (4 pairs) are required, but since they are divided into 2 pieces, each has 4 pairs (2 pairs).
vs) is fine.

Second data bus 111. j+21・j! 12・12
2 is connected to data latches DL1 to DL4 via a switch SW which is opened and closed by a selector 30, and is connected to the outside through a circuit not shown.

When the sense amplifier row on the left side of FIG. 2 operates, the sense amplifier row on the right side does not operate, and when the sense amplifier row on the right side operates, the sense amplifier row on the left side does not operate.
The data latches DL can be used alternately in the left and right sense amplifier columns, and the data launch can be shared.

Sense amplifier drive signal line 1 for left and right sense amplifier rows.
．． 12 is horizontal wiring 1131.132°141.14
2 and the power supply V ss through the gates Gll and GIO,
Connect to Vcc line. Since there are a plurality of horizontal wiring lines (131, etc.) and power is supplied to each of the sense amplifier drive signal lines i1, 12 from a plurality of locations, the width of the signal lines #, 72 may be reduced to one-half of the width of the signal lines #, 72.

In this way, when a 16MDRAM is divided into two in the sense amplifier column direction, the data bus width is 384/2-192 μm, and the sense amplifier drive signal line width is 1280/2-640 μm.
savings can be made.

FIG. 3 shows the layout of various horizontal wirings when a set of 16 sense amplifiers is used. S.A.

~5A16 are the 16 sense amplifiers, BL1~BL1
Reference numeral 6 indicates 16 pairs of bit lines to which these sense amplifiers are connected. CI, C2,... are column selection lines, G
21*022+... is a column selection gate, and in FIG. 2, it is lV3. G2. This is shown in G3. DBa and DBb are four data buses DB21°...
Each pair of... is shown.

One column selection line CI, C2, . . . connects two pairs of bit lines to the corresponding data bus pair DBa, DBb, and together with those of the other 16 sense amplifier columns (not shown), there are four Performs bit-to-bit time read/write. In this example, column selection line C1 connects bit line pair BLI and BL3 to data bus pair DBa, DBb, and column selection line C2 connects bit line pair BL2 and BL4 to data bus pair DBa, DB.
b, and the following will apply accordingly.

If one horizontal wiring (column selection line) runs on one sense amplifier, 16 horizontal wiring will run on 16 sense amplifiers, but one column selection line will run 2 Since we are dealing with pairs of bit lines, eight lines are sufficient, leaving space for the remaining eight lines. Therefore, in this example, there are 4 column selection lines 01 to C4 on the top and 4 lines 05 to C8 on the bottom, leaving 8 lines in the middle, and use these lines as power supply lines or other signal lines (!31 in Figure 2). etc.) and a data bus DBc (this is the lth line in FIG. 2, etc.).

[Effects for the entire town]

As explained above, according to the present invention, it is possible to reduce the width of the data bus running parallel to the sense amplifier columns and the width of the sense amplifier drive signal line running in the direction of the sense amplifier columns.
Particularly in large-capacity memories, a large effect of reducing the required area can be obtained.

[Brief explanation of drawings]

Fig. 1 is an explanatory diagram of the principle of the present invention, Fig. 2 is a detailed explanatory diagram of the present invention, Fig. 3 is an explanatory diagram showing the layout of various horizontal wiring, Fig. 4 is a schematic explanatory diagram of 16MDRAM, and Fig. The figure is an explanatory diagram of a conventional example. In Figure 1, WL is a word line, BL is a bit line, SA is a sense amplifier, MC is a memory cell, DB is a data bus, and j'
11111'21+... is the second data bus,
g,,z2 are sense amplifier drive signal lines, 131°It3
2. . . . is a plurality of wirings. Chest 1

Claims (1)

[Claims] 1. In a semiconductor memory device having a plurality of word lines and bit lines, a column of sense amplifiers provided for each bit line, and a data bus line running parallel to each column of sense amplifiers, in a row selection circuit: In a sense amplifier column connected to a cell array having the same row selection line to be selected, the data bus line is divided in the direction of the sense amplifier column to form multiple independent groups, and each group is connected to the cell array in the direction orthogonal to the sense amplifier column. A semiconductor memory device characterized in that the semiconductor memory device is connected to a second data bus extending above the cell array or the sense amplifier. 2. In a semiconductor memory device having a plurality of word lines and bit lines, a column of sense amplifiers provided for each bit line, and a data bus line running parallel to each column of sense amplifiers, the same row selection is selected by a row selection circuit. In a sense amplifier row connected to a cell array having a sense amplifier row, the sense amplifier drive signal line running in the direction of the sense amplifier row is connected to the sense amplifier drive signal line running in the direction of the sense amplifier row through a plurality of wires extending on the cell array or on the cell array and the sense amplifiers in a direction perpendicular to the sense amplifier row. A semiconductor memory device characterized in that it is connected to a power source at a certain point.