JPH02244747A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH02244747A JPH02244747A JP1065617A JP6561789A JPH02244747A JP H02244747 A JPH02244747 A JP H02244747A JP 1065617 A JP1065617 A JP 1065617A JP 6561789 A JP6561789 A JP 6561789A JP H02244747 A JPH02244747 A JP H02244747A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- thermal resistance
- semiconductor
- heat resistance
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/1015—Shape
- H01L2924/10155—Shape being other than a cuboid
- H01L2924/10158—Shape being other than a cuboid at the passive surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Die Bonding (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
［概要］
半導体チップを電極となる放熱板上に載置して下面に電
極を引き出す構造の半導体装置に関し。DETAILED DESCRIPTION OF THE INVENTION [Summary] This invention relates to a semiconductor device having a structure in which a semiconductor chip is placed on a heat sink serving as an electrode, and electrodes are drawn out from the bottom surface.
半導体チップ表面の熱源から放熱板までの熱抵抗を小さ
くして、放熱効果を高めることを目的とし。The purpose is to reduce the thermal resistance from the heat source on the surface of the semiconductor chip to the heat sink, thereby increasing the heat dissipation effect.
半導体チップを電極となる放熱板上に載置して下面に電
極を引き出す構造の半導体装置において。In a semiconductor device with a structure in which a semiconductor chip is placed on a heat sink that serves as an electrode, and the electrode is drawn out from the bottom surface.
半導体チップの裏面に１個または複数個の穴を形成し、
この穴の中に、半導体チ・ノブを構成する半導体材料の
熱抵抗よりも小さい熱抵抗を存する低熱抵抗物質を充填
するように構成する。Forming one or more holes on the back side of the semiconductor chip,
This hole is configured to be filled with a low thermal resistance material having a thermal resistance smaller than that of the semiconductor material constituting the semiconductor chi-nob.
［産業上の利用分野〕
本発明は、半導体装置、特に、半導体チ・ノブを電極と
なる放熱板上に載置して下面に電極を引き出す構造の半
導体装置に関する。[Industrial Field of Application] The present invention relates to a semiconductor device, and particularly to a semiconductor device having a structure in which a semiconductor chip/nob is placed on a heat sink serving as an electrode and an electrode is drawn out from the bottom surface.
第４図は、従来例を示す図である。 FIG. 4 is a diagram showing a conventional example.
同図において、１１は半導体チップ、１２はＡｇペース
ト １３はリードフレームである。In the figure, 11 is a semiconductor chip, 12 is an Ag paste, and 13 is a lead frame.
第４図に示すように、従来、ＩＣ，ＬＳＩ、ＶＬＳＩな
どの集積回路や個別半導体素子は、半導体チップ１１と
して、 Ａｇペースト１２などの接着剤によりリードフ
レーム１３などの電極兼放熱板となる部材の上に載置し
ていた。As shown in FIG. 4, conventionally, integrated circuits and individual semiconductor elements such as ICs, LSIs, and VLSIs are made by forming a semiconductor chip 11 into a member such as a lead frame 13 that serves as an electrode and a heat sink using an adhesive such as Ag paste 12. It was placed on top.
半導体チップ１１は、導電性であり９例えば。The semiconductor chip 11 is electrically conductive, for example.
接地電橋は、その下面から取り出される構造である。The grounding bridge is a structure that is taken out from the underside.
そして、この状態で金属、セラミックス１樹脂などから
なるパンケージに封入する。さらに、放熱のために、パ
ッケージの表面あるいは裏面に放熱板が取り付けられる
。Then, in this state, it is sealed in a pan cage made of metal, ceramics, resin, or the like. Furthermore, a heat sink is attached to the front or back surface of the package for heat radiation.
従来のように、パフケージの表面あるいは裏面に放熱板
を取り付ける方法は、パンケージ全体の寸法が大きくな
り１表面実装用など、１．＜、小さくすることを要求さ
れるパッケージには、不適当である。という問題があっ
た。The conventional method of attaching a heat sink to the front or back side of the puff cage increases the size of the entire pan cage, making it difficult for 1. surface mounting applications, etc. <, unsuitable for packages that are required to be small. There was a problem.
本発明は４この問題点を解決するためになされたもので
あり、半導体チップ表面の熱源から放熱板までの熱抵抗
を小さくして１放熱効果を高めた半導体装置、特に５半
導体チップを電極となる放熱板上に載置して下面に電極
を取り出す構造の半導体装置を提供することを目的とす
る。The present invention has been made in order to solve this problem (4), and provides a semiconductor device which improves the heat dissipation effect (1) by reducing the thermal resistance from the heat source on the surface of the semiconductor chip to the heat sink. It is an object of the present invention to provide a semiconductor device having a structure in which the semiconductor device is placed on a heat sink and electrodes are taken out from the bottom surface.
上記の目的を達成するために１本発明に係る半導体装置
は、半導体チップを電極となる放熱板上に載置して下面
に電極を引き出す構造の半導体装置において、半導体チ
ップの裏面に１個または複数個の穴を形成し、この穴の
中に、半導体装ツブを構成する半導体材料の熱抵抗より
も小さい熱抵抗を有する低熱抵抗物質を充填するように
構成する。In order to achieve the above object, a semiconductor device according to the present invention has a structure in which a semiconductor chip is placed on a heat sink serving as an electrode and an electrode is drawn out from the bottom surface. A plurality of holes are formed, and the holes are filled with a low thermal resistance material having a thermal resistance lower than that of the semiconductor material constituting the semiconductor chip.
（作 用〕
第２図は従来例の熱抵抗図、第３図は本発明の熱抵抗図
である。(Function) FIG. 2 is a thermal resistance diagram of the conventional example, and FIG. 3 is a thermal resistance diagram of the present invention.
以下、第２図および第３図を用いて、半導体チップ表面
のトランジスタや抵抗などの熱源からり−１フレームな
どの放熱板までのトータルの熱抵抗を示す計算式を従来
例および本発明について導く。Below, using FIGS. 2 and 3, calculation formulas showing the total thermal resistance from heat sources such as transistors and resistors on the surface of the semiconductor chip to heat sinks such as the RI-1 frame will be derived for the conventional example and the present invention. .
（ａ）従来例のトータルの熱抵抗を示す計算式の導出第
２図に示すように、半導体チップ１１の熱抵抗をθｓ
、 Ａｇペースト１２の熱抵抗をθ１１．リードフレー
ム“１３の熱抵抗をθ、とする。(a) Derivation of the calculation formula showing the total thermal resistance of the conventional example As shown in FIG. 2, the thermal resistance of the semiconductor chip 11 is
, the thermal resistance of the Ag paste 12 is set to θ11. The thermal resistance of lead frame "13" is assumed to be θ.
θ、１ θＡ、およびθ、は直列接続されているから１
従来例のトータルの熱抵抗をθ、。、′とすると。θ, 1 θA and θ are connected in series, so 1
The total thermal resistance of the conventional example is θ. ,′.
θ１゜、′＝θ、＋θ。十θ、 ・・・・・
・（１）と表すことができる。θ1°, ′=θ, +θ. 10θ, ・・・・・・
・It can be expressed as (1).
（１））本発明のトータルの熱抵抗を示す計算式の導出
第３図に示すように、熱源６から低熱抵抗ｅＡ質３に至
る半導体チップ】の熱抵抗をθ５９．熱ａ６からＡｇペ
ースト４に至る半導体チップ１の熱抵抗をθ、２．低熱
抵抗＠ＩＪ賞の熱抵抗をθ、、Ａｇペーストの熱抵抗を
θ、９．リードフレーム５の熱抵抗をθ、とする。(1)) Derivation of the calculation formula showing the total thermal resistance of the present invention As shown in FIG. The thermal resistance of the semiconductor chip 1 from the heat a6 to the Ag paste 4 is θ, 2. Low thermal resistance @ IJ award thermal resistance is θ, Ag paste thermal resistance is θ, 9. Let the thermal resistance of the lead frame 5 be θ.
低熱抵抗物１ｔ′３が埋め込まれた半導体チップ１の熱
抵抗をθ。、ｔとすると。The thermal resistance of the semiconductor chip 1 in which the low thermal resistance material 1t'3 is embedded is θ. , t.
θ３１＋θ−〇ｓｚ （θ３．十〇、） ・θ、２ と表すことができる。θ31+θ−〇sz (θ3.10,) ・θ, 2 It can be expressed as.
したがって１本発明のトータルの熱抵抗をθ、。、とす
ると。Therefore, the total thermal resistance of the present invention is θ. , then.
・・・・・・（２） と表すことができる。・・・・・・(2) It can be expressed as.
次に、従来例のトータルの熱抵抗と本発明のトータルの
熱抵抗とを比較する。Next, the total thermal resistance of the conventional example and the total thermal resistance of the present invention will be compared.
（１）式および（２）式において、 Ａｇペーストの熱
抵抗θ４．およびリードフレームの熱抵抗θ、は等しい
ので、半導体チップの熱抵抗を比較する。In equations (1) and (2), the thermal resistance of Ag paste θ4. Since the thermal resistances θ and the lead frame are equal, the thermal resistances of the semiconductor chips will be compared.
（以下余白） θ３ｔ０ｔ／θ。(Margin below) θ3t0t/θ.
（θ、１＋θ、）十〇。(θ, 1+θ,) 10.
θ８．＋θ。θ8. +θ.
（θ□十〇、）＋θ、２ （，°θ、２−θ、） 〈１ （°、°θ５ｉｌｏ） 、°、θＳｔｏ＄＜θ３ したがって。(θ□10,)+θ,2 (,°θ, 2−θ,) <1 (°, °θ5ilo) ,°, θSto$<θ3 therefore.
θい、〈θｔ６＆
となり１本発明のトータルの熱抵抗の方が、従来例のト
ータルの熱抵抗よりも小さいことがわかる。θ, <θt6 & It can be seen that the total thermal resistance of the present invention is smaller than that of the conventional example.
すなわち１本発明のように、半導体チップの裏面に１個
または複数個の穴を形成し、この穴の中に、半導体チッ
プを構成する半導体材料の熱抵抗よりも小さい熱抵抗を
有する低熱抵抗物質を充填すると、熱源から放熱板にい
たるトータルの熱抵抗を小さくすることができる。In other words, according to the present invention, one or more holes are formed on the back surface of a semiconductor chip, and a low thermal resistance material having a thermal resistance smaller than that of the semiconductor material constituting the semiconductor chip is placed in the holes. When filled with , the total thermal resistance from the heat source to the heat sink can be reduced.
第１図は９本発明の一実施例を示す図である。 FIG. 1 is a diagram showing one embodiment of the present invention.
同図において、１は半導体チップ、２は半導体チップの
裏ｌに形成された穴、３は穴２の中に充填された半導体
チップ１を構成する材料の熱抵抗よりも小さな熱抵抗を
有する低熱抵抗物質、４は接着剤としてのＡｇペースト
、５は放熱板としてのリードフレームである。In the figure, 1 is a semiconductor chip, 2 is a hole formed on the back side of the semiconductor chip, and 3 is a low-temperature material having a thermal resistance smaller than that of the material constituting the semiconductor chip 1 filled in the hole 2. A resistive material, 4 an Ag paste as an adhesive, and 5 a lead frame as a heat sink.
半導体チップ１は、 Ｓｉ、化合物半導体などからなる
ＩＣ，ＬＳＩ、ＶＬＳＩなどの集積回路や個別半導体素
子である。The semiconductor chip 1 is an integrated circuit or individual semiconductor element such as an IC, LSI, or VLSI made of Si, a compound semiconductor, or the like.
穴２は、半導体チップ１の裏面に、エツチングなどによ
り１個または複数個形成される。One or more holes 2 are formed on the back surface of the semiconductor chip 1 by etching or the like.
低熱抵抗物ｆ３としては、半導体チップｌの材料がＳｔ
の場合、 Ａｕ、 Ａｇ、 Ｃｕ、 Ａ１などが選ばれ
る。As the low thermal resistance material f3, the material of the semiconductor chip l is St.
In this case, Au, Ag, Cu, A1, etc. are selected.
以下、具体的な数値を用いて、従来例のトータルの熱抵
抗と本実施例トータルの熱抵抗とを計算してみる。Hereinafter, using specific numerical values, the total thermal resistance of the conventional example and the total thermal resistance of the present example will be calculated.
条件を次のように定める。The conditions are set as follows.
従来例 半導体チップの材料 Ｓｔ 半導体チップの厚さ ４００．ｃｒｍ Ａｇペーストの厚さ ４μｍ リードフレームの ４２７０イ 材料 リードフレームの 厚さ 低熱抵抗物質の 材料 低熱抵抗物質の 厚さ （ａ）従来例のトータルの熱抵抗の計算（１）式より。Conventional example Semiconductor chip material St Thickness of semiconductor chip 400. crm Ag paste thickness 4μm Lead frame 4270 material lead frame thickness of low heat resistance material material low heat resistance material thickness (a) Calculation of total thermal resistance of conventional example from equation (1).
２００μｍ ２００１１ｍ
本実施例
４００μｍ
４μｍ
４２７Ｏイ
４ｇ
００１１ｍ
０．８
４．０７
０．５６
一５００ｘ１０−’＋０．９８２ＸＩＯ−’＋３５７ｘ
ＩＱ”
−８５８Ｘ １０−’ （’Ｃ／Ｗ）
（ロ）本実施例のトータルの熱抵抗の計算・・・・・・
（３）
０．８
４．１
０．８
したがって。200μm 20011m This example 400μm 4μm 427Oi4g 0011m 0.8 4.07 0.56 -500x10-'+0.982XIO-'+357x
IQ" -858X 10-'('C/W) (b) Calculation of total thermal resistance of this example...
(3) 0.8 4.1 0.8 Therefore.
（θ３．＋θ、）十θ、！ −０，０２２（’Ｃ／Ｗ） となるから。(θ3.+θ,) 10θ,! -0,022 ('C/W) Because it becomes.
θ１゜％−２２０Ｘ１０−’＋０．９８２Ｘ１０−’＋
３５７Ｘ１０−’
−５８８Ｘ １０−’ （’Ｃ／Ｗ） ・・・−
（４）となる。θ1゜%-220X10-'+0.982X10-'+
357X10-' -588X 10-'('C/W) ...-
(4) becomes.
（３）の値と（４）の値とを比較すると１本実施例のト
ータルの熱抵抗の方が、従来例のトータルの熱抵抗より
も約り０％小さいことがわかる。Comparing the values of (3) and (4), it can be seen that the total thermal resistance of this embodiment is approximately 0% smaller than that of the conventional example.
本発明によれば、従来のようにパンケージの表面や裏面
に放熱板を取り付けなくとも、同等あるいはそれ以上の
放熱効果を得ることができる。According to the present invention, it is possible to obtain the same or better heat dissipation effect without attaching a heat dissipation plate to the front or back surface of the pan cage as in the conventional case.
第１図は本発明の一実施例を示す図。 第２図は従来例の熱抵抗図。 第３図は本発明の熱抵抗図。 第４図は従来例を示す図 である。 第１図において に半導体チップ ２：穴 ３：低熱抵抗物質 ４：Ａ、ペースト ５；リードフレーム 本 φσ 明 ０− プし 才１ジ イタリ）ＩＪ１図 ４″！、 １ミ イ」り 第 ４ 図 FIG. 1 is a diagram showing an embodiment of the present invention. Figure 2 is a thermal resistance diagram of a conventional example. FIG. 3 is a thermal resistance diagram of the present invention. Figure 4 shows a conventional example It is. In Figure 1 semiconductor chip 2: Hole 3: Low heat resistance material 4: A, Paste 5; Lead frame Book φσ Ming 0-Pip 1st year Italian) IJ1 diagram 4″!, 1 mi i”ri Figure 4
Claims (1)
して下面に電極を引き出す構造の半導体装置において、 半導体チップ（１）の裏面に１個または複数個の穴（２
）を形成し、この穴（２）の中に、半導体チップ（１）
を構成する半導体材料の熱抵抗よりも小さい熱抵抗を有
する低熱抵抗物質（３）を充填した ことを特徴とする半導体装置。[Claims] In a semiconductor device having a structure in which a semiconductor chip (1) is placed on a heat sink (5) serving as an electrode and an electrode is drawn out from the bottom surface, one or more semiconductor chips are provided on the back surface of the semiconductor chip (1). hole (2
) and insert the semiconductor chip (1) into this hole (2).
A semiconductor device characterized in that it is filled with a low thermal resistance material (3) having a thermal resistance lower than that of a semiconductor material constituting the semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1065617A JPH02244747A (en) | 1989-03-17 | 1989-03-17 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1065617A JPH02244747A (en) | 1989-03-17 | 1989-03-17 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02244747A true JPH02244747A (en) | 1990-09-28 |
Family
ID=13292160
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1065617A Pending JPH02244747A (en) | 1989-03-17 | 1989-03-17 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02244747A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPWO2007138771A1 (en) * | 2006-05-26 | 2009-10-01 | 株式会社村田製作所 | Semiconductor device, electronic component module, and method of manufacturing semiconductor device |
-
1989
- 1989-03-17 JP JP1065617A patent/JPH02244747A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPWO2007138771A1 (en) * | 2006-05-26 | 2009-10-01 | 株式会社村田製作所 | Semiconductor device, electronic component module, and method of manufacturing semiconductor device |
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