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JPH02244666A - Manufacture of hybrid integrated circuit substrate - Google Patents

Manufacture of hybrid integrated circuit substrate

Info

Publication number
JPH02244666A
JPH02244666A JP6550889A JP6550889A JPH02244666A JP H02244666 A JPH02244666 A JP H02244666A JP 6550889 A JP6550889 A JP 6550889A JP 6550889 A JP6550889 A JP 6550889A JP H02244666 A JPH02244666 A JP H02244666A
Authority
JP
Japan
Prior art keywords
substrate
resist
metal substrate
pattern
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6550889A
Other languages
Japanese (ja)
Inventor
Akira Kazami
風見 明
Masakazu Yamagishi
正和 山岸
Yuusuke Igarashi
優助 五十嵐
Yoshiyuki Kobayashi
義幸 小林
Sumio Ishihara
石原 純夫
Kiyoshi Takahashi
清 高橋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP6550889A priority Critical patent/JPH02244666A/en
Publication of JPH02244666A publication Critical patent/JPH02244666A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0266Marks, test patterns or identification means
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/02Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/06Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
    • H05K3/061Etching masks

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To form resist only on metal substrate of the same pattern to prevent the occurrence of a defective by a method wherein a symbol mark is provided to a blank part of the metal substrate where a conductive pattern is not formed, and the symbol mark is recognized before a resist process. CONSTITUTION:Resist is printed on a blank part of a metal substrate 1 other than a region where a conductive pattern is formed for the formation of a symbol mark 2. Therefore, the symbol mark 2 is formed on the blank part of the substrate 1 after a nickel plating treatment. The symbol mark 2 formed on the substrate 1 is recognized by a prescribed recognition device before an etching resist film is screen-printed, and etching resist is printed only when a pattern to be printed on the substrate 1 is identical to the resist pattern. By this setup, even if a board provided with a different pattern is transferred, a resist process is not executed onto the substrate concerned, so that a defective product is prevented from occurring.

Description

【発明の詳細な説明】 (り産業上の利用分野 本発明は混成集積回路基板の製造方法に関する。[Detailed description of the invention] (Industrial field of use) The present invention relates to a method of manufacturing a hybrid integrated circuit board.

く口)従来の技術 従来の混成集積回路はアルミニウム等の金属基板上に所
望形状の導電路を形成し、その導電路上に印刷抵抗、ト
ランジスタ、IC等の複数の回路素子を付着して所定の
機能を有する混成集積回路が提供されている。
Conventional technology In conventional hybrid integrated circuits, a conductive path of a desired shape is formed on a metal substrate such as aluminum, and multiple circuit elements such as printed resistors, transistors, and ICs are attached to the conductive path to form a predetermined pattern. A hybrid integrated circuit with functionality is provided.

断る混成集積回路を製造する場合1.第2図Aに示す如
く、短冊状の金属基板(11)上に導電金属箔を有する
樹脂層を貼着し、導電金属箔上の所定の位置にNiメッ
キ層を形成した後、第2図Bに示を如く、前記導電金属
箔を所望形状のパターンにエツチングして複数の導電パ
ターン(12)を形成する。前記導電パターン(12)
が形成される領域は個別基板〈13)となり、前記金属
基板(11)の個別基板り13)領域をプレス抜きして
個々の基板に分割する。斯る基板は図示しないが専用の
組立ラインに搬送して所定の組立り程を行い混成集積回
路が完成される。
When manufacturing hybrid integrated circuits: 1. As shown in FIG. 2A, a resin layer having a conductive metal foil is pasted on a strip-shaped metal substrate (11), and a Ni plating layer is formed at a predetermined position on the conductive metal foil. As shown in FIG. 1B, the conductive metal foil is etched into a desired pattern to form a plurality of conductive patterns (12). The conductive pattern (12)
The area where the metal substrate (11) is formed becomes an individual substrate (13), and the area of the individual substrate (13) of the metal substrate (11) is punched out and divided into individual substrates. Although not shown, such a board is transported to a dedicated assembly line and subjected to predetermined assembly steps to complete a hybrid integrated circuit.

(ハ)発明が解決しようとする課題 上述した従来の製造方法では以下に示す様な問題があっ
た。
(c) Problems to be Solved by the Invention The conventional manufacturing method described above has the following problems.

ここで、短冊状の金属基板上に複数の導電パターンを形
成するときの工程についてもう少し詳細に説明する。金
属基板上には複数の同一パターンを形成する様にあらか
じめ設定されており、この金属基板上の所定位置にボン
ディング用のNiメッキ層が形成される。Niメッキ層
形成後、金属基板上にはエツチング用のレジストがスク
リーン印刷され、導電金属箔を−】〜ツチングして複数
の同一の導電パターンが形成される。
Here, the process of forming a plurality of conductive patterns on a rectangular metal substrate will be described in more detail. A plurality of identical patterns are preset on the metal substrate, and a Ni plating layer for bonding is formed at a predetermined position on the metal substrate. After forming the Ni plating layer, an etching resist is screen printed on the metal substrate, and the conductive metal foil is etched to form a plurality of identical conductive patterns.

斯るエツチング用のレジストをスクリーン印刷する際に
は通常同一パターンの金属基板のみを搬送するが必らず
しも同一パターンを有する短冊状の金属基板がレジスト
工程に搬送されず、ときには異なったパターンの金属基
板が搬送されるときがある。この場合、異なったパター
ンの金属基板上にはそのパターンにあったレジストが印
刷されず、レジスト後ただちにエツチングされて不良品
が発生する問題があった。
When screen-printing resist for etching, usually only metal substrates with the same pattern are transported, but strip-shaped metal substrates with the same pattern are not necessarily transported to the resist process, and sometimes different patterns are transported. metal substrates are sometimes transported. In this case, there is a problem in that a resist that matches the pattern is not printed on a metal substrate with a different pattern, and that the resist is etched immediately after the resist is applied, resulting in defective products.

(ニ)課題を解決するための手段 本発明は上述した課題に鑑みて為されたものであり、短
冊状の金属基板の一主面上に導電金属箔を有する樹脂層
を貼着し、導電金属箔上に所望形状の金属メッキ層を形
成し、金属基板の一カ所に標識記号を形成して、標識記
号を所定の認識装置で認識した後、前記導電金属箔上に
所望形状のレジスト膜を形成して、前記導電金属箔をエ
ツチングして解決する。
(d) Means for Solving the Problems The present invention has been made in view of the above-mentioned problems, and is made by pasting a resin layer having a conductive metal foil on one main surface of a strip-shaped metal substrate to create a conductive material. A metal plating layer with a desired shape is formed on the metal foil, a sign symbol is formed in one place on the metal substrate, and the sign symbol is recognized by a predetermined recognition device, and then a resist film with a desired shape is formed on the conductive metal foil. The problem is solved by etching the conductive metal foil.

(*)作用 この様に本発明に依れば、短冊状の金属基板の余白部分
に標識記号を形成し、エツチングレジスト膜形成前に標
識記号を認識してそのデータに基づいてレジスト膜を形
成することにより、異種パターンを有する金属基板が搬
送されてたとしてもレジスト膜は形成されず、同一パタ
ーンを有した金属基板のみにレジスト膜が印刷される6
(へ)実施例 以下図面に示した実施例に基づいて本発明の詳細な説明
する。
(*) Effect As described above, according to the present invention, marking symbols are formed in the margins of a strip-shaped metal substrate, and the marking symbols are recognized before forming an etching resist film, and a resist film is formed based on the data. By doing this, a resist film is not formed even if metal substrates having different patterns are being transported, and a resist film is printed only on metal substrates having the same pattern6.
(f) Examples The present invention will be described in detail below based on the examples shown in the drawings.

先ず第1図Aに示す如く、短冊状の金属基板(1)を用
意する。金属基板(1)としては0.5〜2゜0田厚の
アルミニウム基板を用い、そのアルミニウム基板の表面
は周知の陽極酸化技術によって酸化アルミニウム膜を形
成する。この金属基板(1)の−主面上に導電パターン
を形成するための導電金属箔を有した絶縁樹脂を貼着す
る。導電金属箔としてはCu箔が用いられ、絶縁樹脂と
してはエポキシ系あるいはポリイミド系の樹脂を用いる
First, as shown in FIG. 1A, a strip-shaped metal substrate (1) is prepared. As the metal substrate (1), an aluminum substrate having a thickness of 0.5 to 20° is used, and an aluminum oxide film is formed on the surface of the aluminum substrate by a well-known anodic oxidation technique. An insulating resin having a conductive metal foil for forming a conductive pattern is pasted on the main surface of the metal substrate (1). Cu foil is used as the conductive metal foil, and epoxy or polyimide resin is used as the insulating resin.

尚、点線で囲まれた領域は個別基板領域であり、この領
域内に導体パターンを形成する。
Note that the area surrounded by dotted lines is an individual substrate area, and a conductor pattern is formed within this area.

次に第1図Bに示す如く、複数の導電パターンを形成す
る金属基板り1)上に金属メッキを必要としない領域に
金属メッキ用のレジスト膜をスクリーン印刷する。斯る
スクリーン印刷後に、ニッケルメッキの1気メッキを行
いレジストを剥離してニッケルメッキの必要な領域にニ
ッケルメッキ層を形成する。ニッケルメッキは半田付着
される以外の領域に通常形成される。
Next, as shown in FIG. 1B, a resist film for metal plating is screen printed on areas where metal plating is not required on the metal substrate 1) on which a plurality of conductive patterns are to be formed. After such screen printing, one-step nickel plating is performed, the resist is peeled off, and a nickel plating layer is formed in the area where nickel plating is required. Nickel plating is typically applied to areas other than those to be soldered.

本工程で大切な点はメッキ用レジストをスフノーン印刷
する際に基板(1〉の周端部、即ち、導電パターンを形
成する領域以外の余白部分に標識記号(2)を形成する
ために標識記号用のレジストを印刷するところにある。
An important point in this process is that when printing the plating resist in a continuous pattern, the marking symbol (2) is formed on the peripheral edge of the substrate (1), that is, in the margin area other than the area where the conductive pattern is to be formed. It's where you print the resist for your computer.

ニッケルメッキ処理後、基板(1)・の余白部分にはC
u箔が露出されて所望形状の標識記号(2)が形成され
ることになる。
After nickel plating, the blank area of the board (1) is marked with C.
The u-foil will be exposed to form a marker symbol (2) of the desired shape.

8I識記号(2)の形状は任意に設定でき、同一バター
ンを形成するものは同一の形状の標識記号(2)を形成
すればよい。
The shape of the 8I identification symbol (2) can be set arbitrarily, and those forming the same pattern may form the identification symbol (2) of the same shape.

次に第1図Cに示す如く、標識記号(2)を形成した金
属基板(1)上にエツチング用のレジスト膜をスクリー
ン印刷する。この場合、本発明では第1図Cに示す如く
、金属基板(1)上に形成した標識記号(2)の形状を
所定の認識装置(3)で認識し、その基板(1)に形成
するパターンとエツチングレジストパターンとが同一で
あるかないかを判別してOKと判別されたもののみに所
定パターンのエツチングレジストをスクリーン印刷する
0判別がNOとされたときは、その基板にはレジスト印
刷は行われずその工程から削除される。エツチングレジ
スト膜をスクリーン印刷した後、直に金属基板(1)は
エツチング工程に搬送されエツチング処理されて複数の
導電パターン〈4)が形成される。
Next, as shown in FIG. 1C, a resist film for etching is screen printed on the metal substrate (1) on which the marking symbol (2) is formed. In this case, in the present invention, as shown in FIG. It is determined whether the pattern and the etching resist pattern are the same or not, and a predetermined pattern of etching resist is screen-printed only on those that are determined to be OK.0 When the determination is NO, the resist printing is not performed on that board. It is not performed and is removed from the process. After the etching resist film is screen printed, the metal substrate (1) is immediately transported to an etching process and etched to form a plurality of conductive patterns (4).

金属基板(1)上に複数の同一パターンを形成した後、
プレス金型工程でプレス抜ききれ個別の混成集積回路基
板に分離する。斯る混成集積回路基板は複数の組立を有
した組立工程へ搬送され所定の組立が行われ混成集積回
路が完成きれる。
After forming multiple identical patterns on the metal substrate (1),
It is punched out in the press mold process and separated into individual hybrid integrated circuit boards. Such a hybrid integrated circuit board is transported to an assembly process having a plurality of assemblies, and predetermined assemblies are performed to complete a hybrid integrated circuit.

この様に本発明に依れば、エツチングレジスト印刷前に
必らず標識記号の形状を認識することで、異なったパタ
ーンを有した金属基板が搬送されてもレジスト工程は行
われず不良を防止することができる。
As described above, according to the present invention, by always recognizing the shape of the marking symbol before printing the etching resist, even if a metal substrate with a different pattern is transported, the resist process is not performed and defects are prevented. be able to.

(ト〉発明の効果 以上に詳述した如く、本発明に依れば、金属基板の導電
パターンを形成しない余白部分に標識記号を形成し、エ
ツチングレジスト工程前に必らず認識装置により標識記
号を認識することにより、確実にレジストパターンを形
成する基板上にレジストが形成され、従来の不良を完全
に防止することができる。
(G) Effects of the Invention As described in detail above, according to the present invention, the marking symbol is formed in the blank area of the metal substrate where the conductive pattern is not formed, and the marking symbol is always recognized by the recognition device before the etching resist process. By recognizing this, the resist is reliably formed on the substrate on which the resist pattern is formed, and conventional defects can be completely prevented.

また、本発明は従来の製造工程をそのまま利用すること
ができる利点を有する。
Furthermore, the present invention has the advantage that conventional manufacturing processes can be used as they are.

【図面の簡単な説明】[Brief explanation of drawings]

第1図A乃至第1図Cは本発明の製造工程を示す工程図
、第2図A及び第2図Bは従来例を示す工程図である。 図A 第 図B
1A to 1C are process diagrams showing the manufacturing process of the present invention, and FIGS. 2A and 2B are process diagrams showing a conventional example. Figure A Figure B

Claims (4)

【特許請求の範囲】[Claims] (1)短冊状の金属基板を準備する工程と、前記金属基
板の一主面上に導電金属箔を有する絶縁樹脂を貼着する
工程と、 前記導電金属箔上に所望形状の金属メッキ層を形成する
工程と、 前記金属基板の少なくとも一カ所に標識信号を形成する
工程と、 前記標識信号を所定の認識装置で認識した後、前記導電
金属箔上に所望形状のレジスト膜を形成する工程と、 前記導電金属箔を所望形状にエッチングし前記金属基板
上に複数の導電パターンを形成する工程と、 を備えたことを特徴とする混成集積回路基板の製造方法
(1) A step of preparing a strip-shaped metal substrate, a step of pasting an insulating resin having a conductive metal foil on one main surface of the metal substrate, and a metal plating layer of a desired shape on the conductive metal foil. forming a mark signal on at least one location of the metal substrate; and after recognizing the mark signal with a predetermined recognition device, forming a resist film in a desired shape on the conductive metal foil. A method for manufacturing a hybrid integrated circuit board, comprising: etching the conductive metal foil into a desired shape to form a plurality of conductive patterns on the metal substrate.
(2)前記標識記号は前記金属基板上に形成される複数
の導体パターン以外の余白部分に形成することを特徴と
する請求項1記載の混成集積回路基板の製造方法。
(2) The method for manufacturing a hybrid integrated circuit board according to claim 1, characterized in that the marking symbol is formed in a blank area other than the plurality of conductor patterns formed on the metal substrate.
(3)前記標識記号は前記導電金属箔あるいは前記金属
メッキ層で形成されることを特徴とする請求項1記載の
混成集積回路基板の製造方法。
(3) The method of manufacturing a hybrid integrated circuit board according to claim 1, wherein the sign symbol is formed of the conductive metal foil or the metal plating layer.
(4)前記導電金属箔は銅箔であり、前記金属メッキ層
はニッケルメッキ層であることを特徴とする請求項1記
載の混成集積回路基板の製造方法。
(4) The method of manufacturing a hybrid integrated circuit board according to claim 1, wherein the conductive metal foil is a copper foil, and the metal plating layer is a nickel plating layer.
JP6550889A 1989-03-16 1989-03-16 Manufacture of hybrid integrated circuit substrate Pending JPH02244666A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6550889A JPH02244666A (en) 1989-03-16 1989-03-16 Manufacture of hybrid integrated circuit substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6550889A JPH02244666A (en) 1989-03-16 1989-03-16 Manufacture of hybrid integrated circuit substrate

Publications (1)

Publication Number Publication Date
JPH02244666A true JPH02244666A (en) 1990-09-28

Family

ID=13289077

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6550889A Pending JPH02244666A (en) 1989-03-16 1989-03-16 Manufacture of hybrid integrated circuit substrate

Country Status (1)

Country Link
JP (1) JPH02244666A (en)

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