JPH02244656A - Semiconductor circuit device - Google Patents

Abstract

PURPOSE:To effectively reduce the deviation of signals from each other among chips by a method wherein a clock feed section and a clock buffer of two or more chips are separated into two parts, one for a data input-output section and the other for an inner latch. CONSTITUTION:A signal line CL1 from a chip CK2 which generates a clock signal serves as a common input line for clock terminals of latches F1, F4, F5, and F6 and also as an input line for buffers C11 and C12. The latches F1, F4, F5, and F6 are equal to each other as loads from the signal line CL1 side, so that the clock signals of the latches are kept from the deviation from each other in phase. Therefore, data transfer synchronizing with both clocks can be made through a data line P2. Loads are the same from the view point of a clock line CL2 on the output side of the buffer C11, so that inner latches are prevented from deviating from each other in phase. By this setup, signals in two or more chips can be effectively reduced in deviation from each other.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention is directed to a semiconductor circuit device that enables good signal transmission between a plurality of semiconductor chips.
In particular, the clock signal for data transmission and reception is designed so that no phase shift occurs in the data transmission and reception latch.

(Prior Art) Generally, in a circuit in which the transfer of arbitrary data between a plurality of semiconductor chips is controlled by at least one in-phase clock signal, the shift between the data signal and the clock signal is eliminated.

In particular, if there is a lag between the data transfer clocks of the latch circuit between data transmission and data reception, data transfer will not be performed successfully.

FIG. 4 shows a method of using a signal delay chip to reduce the phase shift between clock signals. In the figure, CKI is a chip that generates a clock signal, CH, 1/CH14- is a chip, Bl, B2 are latch circuits, C1,
C2 is a clock buffer, and DISD2 is a chip with a built-in delay circuit.

By the way, as a method of transmitting signals between a plurality of chips, the gate delay times of the clock buffer ClSC2 inside the chip are set as C1 and C2, and the gate delay times of the clock buffer ClSC2 inside the chip are set as 2, and the cells (latches) B1, . , the delay time to B2 is β1,
Let β2 be 1, and the latch delay time be γ15γ2, then α1+β1+γ■ α2+β2toγ2 In the case of α2+β2 and γ2, insert a chip Di with a built-in delay circuit between the data signal wiring between latch BISB2.
In the case of 1+71〉α2+β2+72, between the wiring between chip CKI and buffer C2,
A chip D2 with a built-in delay circuit is inserted to reduce the phase shift between the data signal and the clock signal.

In another conventional example, instead of using the delay elements DI and D2, the wiring lengths of the respective parts may be changed to adjust the phase.

(Problem to be solved by the invention) However, in the case of FIG. 4, the chip CHIO1CIll
In addition to , chips Di and D2 are required. Also, as the number of chips increases in this way, the board size increases.

This makes chip placement difficult.

Further, as the number of chips increases, the area occupied by the chips on the board increases, so that the wiring between the latch B1 and 82, the wiring between the chip CKI and the buffer 02, and other signal wiring become complicated. Furthermore, the method of reducing the phase shift of the signal by changing the wiring length has the possibility that the wiring length becomes very long. In that case, the area occupied by the wiring on the board 1- becomes large, making it difficult to arrange each chip. Moreover, in any case, since the delay time for each chip and data is not constant, it is very difficult to adjust the phase corresponding to each chip and data.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to make it possible to satisfactorily reduce deviations in signals applied to a plurality of chips.

[Structure of the Invention] (Means and Effects for Solving the Problems) The present invention provides a circuit in which transfer between a plurality of semiconductor chips is controlled by at least one in-phase clock signal. In the semiconductor circuit device, the clock signal is commonly inputted to the latch circuit in the first stage from the data input terminal and the data output terminal of the chip, respectively, and is separated from the system for other latch circuits. be.

That is, the present invention makes the respective loads seen from the clock signal supply terminals the same by making the clock signal paths from the clock signal input section to the input terminal section and output terminal section of the chips the same in a plurality of chips. , the data output side in data transfer between chips,
This is to prevent a phase shift of the clock signal on the input side.

(Embodiment) An embodiment of the present invention will be described below with reference to the drawings. Figure 1 shows the composition of jl-・l 21j, % example, and CK
2 is a chip that generates a clock signal, CHI, CH
2 is a chip, F1 to FB are latch circuits, C1l, CI2
is a clock amplification buffer, P1 to P3 are interchip data lines, and CLI to CL3 are clock signal lines.

Clock signal line CLI is latch FI, F4, F5, F8
1) Buffer C1
1, C1, 2 manpower. The buffers C1l and C12 are used to improve the driving ability of the latch on the output side, and are not involved in clock phase shift compensation d-.

In the configuration of FIG. 1, latches Fl, F4 . F5 and F8 are the same (
(the load is the same), so there is no phase shift between the clock signals of these latches. Therefore, data transfer synchronized with both these clocks (in phase with each other) is transferred to the data line P2 (
The same can be done for PL and P3). Further, since the clock line CL2 on the output side of the buffer C11 is a common internal launch, the load seen from Cl3 is the same and no clock phase shift occurs between the internal latches.

In the embodiment shown in FIG. 2, CK 3 iJ is a clock generation chip, CH, 3, and CH4 are chips, and FIO to F80.
are latches, C21 to C24 are l1ilff block amplification buffers, and Cl4 to CL8 are L7 block signal lines.

In the circuit shown in Figure 2, the buffer is connected to the signal line CL4.
Through C21, the negative 8N that saw the latch FIO, the load that saw the latch F40, and the buffer C2 from the signal line CL4.
3, the load looking at latch F50 and the load looking at latch F80 are the same in ten thousand, so gore latches F40 and F5
050 No mutual phase shift occurs (PL.

The same applies to the P3 portion.

Furthermore, since the output sides of the buffers C22 and C24 have the same load, no clock phase shift occurs. Note that buffers C22 and C24 have the same load as seen from Cl4, and no problem will occur even if buffers C22 and C24 are absent.

In the embodiment shown in FIG. 3, CK4 is a clock generation chip, CH5 and CH6 are chips, F100 to F1A0 are latches, C31 to C34 are clock amplification buffers, C1,
9 to CL13 are clock signal lines.

In FIG. 3, from the signal line CL9 through the buffer C31, the load looking at the latch F100, the load looking at the latch F130, and the load looking at the latch F130 from the signal line CL9 through the buffer C33,
Since the load looking at latch F 140 and the load looking at latch F 170 are the same, these latches F HO and F 14
There is no phase shift between zeros (the same applies to Pl and P3, respectively).

Here, each latch from the Cl3 point via the buffer C31,
It is assumed that each latch load via the buffer C33 is the same. From the output of buffer C32, latch FILO~F12
The load that looks at 0 is the same, and the load that looks at the latches F150 to F160 from the output of the buffer C34 is also the same, so the problem of phase shift inside each chip does not occur.

[Effects of the Invention] As explained above, according to the present invention, the clock supply section or clock buffer in each chip is divided into one for data input/output section and one for other internal latches, so that load adjustment can be performed independently and identically for each. This allows the delay time from the clock signal pin to the data input/output section to be mutually adjusted to a constant value. Therefore, when a plurality of chips are operated with the same phase clock, there is no need to consider clock skew in data transfer between chips. Therefore, there is no need to provide a conventional skew adjustment delay element, and there is no need to increase the wiring length. Furthermore, the area of the board can be reduced, and development time and costs can be reduced.

[Brief explanation of drawings]

1 to 3 are circuit configuration diagrams of each embodiment of the present invention,
FIG. 4 is a circuit diagram of a conventional device. CK2 to CK4...Clock signal generation chip,
CH1~CH(i...chip, F1~Fg, F
IO~・F'80, F100~F+, 70...Latch, C1l, C10, C21~C24, C3L~C34
...Clock buffer, CLI to CL13...
...Clock signal line, P1 to P3...Data line.

Claims (2)

[Claims] (1) In a circuit in which data transfer between a plurality of semiconductor chips is controlled by at least one in-phase clock signal, the clock signal is transmitted inside the plurality of chips from a data input terminal and a data output terminal of the chips, respectively. A semiconductor circuit device characterized in that a latch circuit in the first stage has a common input and is separated from a system for other latch circuits. (2) The clock signal inputted from the external lead-out pins of the plurality of chips is passed through at least one stage of buffer circuits to a latch circuit in the first stage from the data input terminal and data output terminal of the chip, and other stages. 2. The semiconductor circuit device according to claim 1, wherein loads passing through each of the buffer circuits can be considered to be the same when viewed from the pin.