JPH02242363A - Shared resource control system - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Summary] Regarding a shared resource control method in an information processing system in which a plurality of processing units each share a shared resource, it is possible to prevent the occurrence of shared resource waiting without complicating the control of processing units. The purpose is to reduce the chances of this happening as much as possible by dividing the shared resource into multiple division units, setting a blockage flag for each division unit, and when each processing unit requests the use of the shared resource, An address indicating a position to be used is specified, and each processing unit is provided with a flag determining means for determining a flag corresponding to the division unit including the position to be used based on the use request and the address, and the flag determined by the flag determining means is By transmitting the flag to the test and set instruction execution means, the test and set instruction execution means is configured to block only the divided unit corresponding to the flag and make it usable for its own processing unit.

[Industrial application field]

The present invention relates to an information processing system, and particularly to a shared resource control method in an information processing system in which a plurality of processing units each share a shared resource.

When processing units such as multiple processors or multiple processes operating within a single processor share shared resources such as shared memory or various input/output devices, if one processing unit is using the shared resources. , If other processing units use the shared resource in parallel, confusion will occur in the processing results of both.

Test and set instructions are widely used as a means to prevent such confusion.

[Prior Art] FIG. 4 is a diagram showing an example of a conventional information processing system.

In FIG. 4, two sets of processors (CPU) (individual processors (CPU) are referred to as 1-0 and 1-1, hereinafter the same) operate as a processing unit to process a shared memory IJ (CM ) 2 is commonly used.

Each processor (CPU) 1 is equipped with a test and set setting section (TSS) 11 and a test and set cancellation section (TSR) 12, and also has a shared memory.
(For CM>2, a flag F0 indicating the blockage state of the storage area A is provided.

For example, in processor (CPU) 1-0, storage area A,
When a request is made to read data dx stored at address ax in , perform necessary processing, and write to address ax again, processor (CPU) 1-0 sets test and set setting unit (TSS) 11-0. and flag F
A test and set setting command TS specifying the location of address 0 (address ao) is transmitted.

Started test and set setting section (TSS) 11-
0 analyzes the setting state of the flag F0 provided at the address a0 specified by the received test and set setting command TS, and if it is set to an empty state, the corresponding storage area A0 is Processor (CPU) 1
-1, it is judged that it is not used, and immediately flag F
After setting 0 to the blocked state, processor (CPU) 1-
Allow 〇 to use storage area A.

In this state, the other processor (CPU) 1-1 receives data d, which is stored at address a in storage area A0.
When a request is made to perform the necessary processing and write to address a again, processor (CPU) L-1 starts test and set setting section (TSS) 11-1,
A test and cent setting command TS specifying the location (address as) of the flag F0 is transmitted.

Started test and set setting section (TSS) 11-
1 analyzes the setting state of the flag F0 set at the address aQ specified by the received test and set setting command TS, and when it is confirmed that the flag F0 is set to the blocked state, the corresponding storage area A0 is set to another address. processor (C
It is determined that it is in use based on PU) l-0, and it waits until the flag F0 becomes empty.

When the processor (CPU) I-0 completes the read and write processing for the data dX, it activates the test-and-sent release unit (TSR) 12-O and sets the flag F.
6 is located at address a. ) is transmitted.

Activated test-and-sent release unit (TSR-) 12
-0 is the flag F0 set at the address a0 specified by the received test and set release command TR.
is set to free status, and the storage area A0 is set to be used by other processors (
CPU) 1-1 can also be used.

[Problem to be solved by the invention]

As is clear from the above explanation, in a conventional information processing system, processors (CPUs) 1-0 and 1-
Storage area A0 in shared memory (CM) 2 shared by 1
A flag Fo is set corresponding to the storage area A0, and the processor (CPU) 1-0 that uses the storage area A0 sets the flag F0 to the blocked state, so that other processors (CPU) l-1
During this time, the processor (CPU)
1-1 needs to wait for the use of storage area A0,
There was a risk that processing efficiency would be reduced.

In order to reduce the probability of occurrence of such a wait as much as possible, it is also considered to divide the storage area A0 into a plurality of partial storage areas and set a flag for each partial storage area, thereby making the partial storage area a blockage unit. However, in such a case, each processor (CPU) 1 determines which partial storage area the target address belongs to and which flag is set in each test and set setting section (TSS) 11 or test and set cancellation section (TSR) 12. It is necessary to determine whether it should be specified as
There was a problem that the control was complicated.

An object of the present invention is to reduce the chances of shared resource queuing occurring as much as possible without complicating the control of processing units.

[Means to solve the problem]

FIG. 1 is a diagram showing the principle of the present invention.

In FIG. 1, 100 is a plurality of processing units provided in the information processing system, 200 is a shared resource shared by each processing unit 100, and 101 is a test and set instruction execution means provided in each processing unit 100.

102 is a flag determining means provided in each processing unit 100 according to the present invention.

201 is a plurality of division units provided by dividing the shared resource 200 according to the present invention.

Reference numeral 300 is a blockage flag provided corresponding to each division unit 201 according to the present invention.

[Effect]

When each processing unit 100 requests the use of the shared resource 200, it specifies an address a indicating the location to be used.

The flag determining means 102 determines a flag 300 corresponding to the division unit 201 including the position to be used, based on the use request and address a.

The test and set instruction execution means 101 blocks only the division unit 201 corresponding to the flag 300 determined by the flag determination means 102 and makes it usable for its own processing unit 100.

Therefore, when a processing unit requests the use of a shared resource, it only specifies the location to be used, and only the division unit that includes the location to be used is blocked from other processing units. In this case, other processing units can be used in parallel, and without complicating the control of the processing units, the chances of waiting for shared resources are significantly reduced, and the processing efficiency of the information processing system is improved.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 2 is a diagram showing an information processing system according to an embodiment of the present invention, and FIG. 3 is a diagram illustrating the flag determination process in FIG. 2. Note that the same reference numerals indicate the same objects throughout the figures.

In FIG. 2, two sets of processors (CPUs) 1 are shown as the processing unit 100 in FIG.
A storage area A0 is shown in the shared memory IJ (CM) 2 as a shared resource 200 in the figure, and a test and set setting section (TSS) 11 and a test and set cancellation section are shown as the test and send instruction execution means 101 in FIG. (TSR) 12 is shown in each processor (CPU) 1, and a flag determining section (FDC) 13 is provided in each processor (CPU) 1 as the flag determining means 102 in FIG. Just as the shared resource 200 in FIG. 1 is divided into a plurality of division units 201, the storage area A is divided into four sets of partial storage areas AI to A4, and the flags 300 in FIG. to F4 correspond to each partial storage area A+ to A4, and control wJ area b1 in the shared memory (CM) 2.
It is provided from b4 to b4.

In FIGS. 2 and 3, processor (CPU) l
-0, when a request is generated to read data dX stored at address ax in storage area A0, perform necessary processing, and write it again to address ax, the processor (CPU
) 1-0 activates the flag determination unit (FDC) 13-0,
Storage area A.

A test and set setting command TS is transmitted that specifies a flag F0 that is virtually provided corresponding to the flag F0 and an address a8 to be accessed.

The activated flag determination unit (FDC) 13-0 extracts the flag F from the received test and set setting command TS (step S1 in FIG. 3), and the flag F0 is registered in the processor (CPU) 1-0. When it is confirmed that the address a8 is registered (step S3), the address aX is extracted from the test and set setting command TS (step S4).
Analyzes which partial storage area Ai (where i is 1 to 4) exists in which partial storage area Ai (step S5), and confirms that it exists in partial storage area A+ (step S5).
6) After determining the flag F1 provided corresponding to the partial storage area A1 (step S8), analyze whether the received command is a test and set setting command TS or a test and cent cancellation command TR (step S8). , when it is confirmed that it is the test and set setting command TS, the test and set setting section (TSS) 11-0 is activated (step S9), and the flag F+ determined in step S7 is set.
The control area in the shared memory (CM) 2 is specified.

Started test and cent setting section (TSS) 11-
0 is the flag F set in the constraint area designated by the received test and set setting command TS through the same process as described above.

Analyzes the setting state of A, and if it is set to free state, the corresponding partial storage area A is used by another processor (CP
LJ) 1-1 determines that it is not being used, and immediately sets flag F to a blocked state.
U) Allow use of partial storage area A for 1-0.

Note that if the flag F0 is confirmed to be unregistered in step S2 (step S3), or if the address ax is determined to be storage area A in step S5.

If the partial storage area Ai is outside the range and the partial storage area Ai is not determined, a message indicating that the received test and set setting command TS is abnormal is displayed (step S6).
ll).

In this state, the data dy stored at address a in storage area A is stored in another processor (CPU) 1-1.
When a request is made to read out, perform the necessary processing, and write to address a again, the processor (CPU) 1-1 activates the flag determination unit (FDC) 13-1 in the same way as described above.
Flag F0 virtually provided corresponding to storage area A0
and the address a to be accessed.

Activated flag determination unit (FDC) 13-N! After confirming that the flag F specified in the received test and set setting command TS has been registered in the processor (CPU) 1-1 (steps S1 to S3), the flag F specified in the test and set setting command TS is address a
Step S4) to extract y, and analyze in which partial storage area Ai the address a exists in step S5.
), for example, exists in the partial storage area A (step S6), and after determining the flag F provided corresponding to the partial storage area A3 (step S8)
When it is confirmed that the received command is a test and set setting command TS (step S8), the test and set setting section (TSS) 11-1 is activated in step S9.
), the control region S of the flag F determined in step S7 is specified.

Started test and set setting section (TSS) 11-
1 analyzes the setting state of the flag F3 set in the control area specified by the received test and set setting command TS through the same process as described above, and if it is set to an empty state, , corresponding partial storage area A,
After determining that the partial storage area A is not being used by another processor (CPU) 1-0 and immediately setting the flag F3 to the blocked state, the processor (CPU) 1-1 is allowed to use the partial storage area A.

When the processor (CPU) 1-0 eventually completes the read and write processing for the data d8, the processor (CPU) 1-0 selects the flag determination unit (FD) as described above.
C) 13-0 is activated and a flag F is virtually provided corresponding to the storage area A0. and the accessed address ax
A test and set release command TR is transmitted specifying the following.

The activated flag determination unit (FDC) 13-0 confirms that the flag F specified in the received test and set cancellation command TR has been registered in the processor (CPU) 1-0 (step S1 to S3), the address a specified in the test and set release instruction TR
Step S4) to extract x, and step S5 to analyze which partial storage area At the address aX exists in.
), and confirming that it exists in the partial storage area AI (
Step S6), after determining the flag F provided corresponding to the partial storage area A1 (Step S8), and confirming that the received command is the test and set cancellation command TR (Step S8), the test Activate the AND set release unit (TSR) 12-0 (step 5IO),
Control region b of flag F1 determined in step S7
Specify 1.

Activated test and set release unit (TSR) 12-
0 sets the flag F1 provided in the control <u SR area b1 to an empty state, and makes the partial storage area A available to another processor (CPU) l-1. It can also be used for

As is clear from the above description, according to this embodiment, the processor (CPU) 1-0 uses the address ax of the storage area A0.
A flag F is virtually provided corresponding to the storage area A0 when requesting access to the storage area A0. By simply transmitting the test and set setting command TS that specifies the address "all" and the address "all" to be accessed to the flag determination unit (FDC) 13-0, it is possible to block and use only the partial storage area AI where the address ax exists. Therefore, there is no need to be aware of the partial storage area A where the address ax to be accessed is located, so control is simple, and other processors (CP
U) 1-1 is another partial storage area A in the same storage area A0
It is possible to access another address a existing in , without waiting.

Note that FIGS. 2 and 3 are only one embodiment of the present invention, and for example, storage area A is divided into four sets of partial storage areas AI.
It is not limited to those classified into A4 to A4, and many other modifications may be considered, but the effects of the present invention remain the same in any case.

Furthermore, the processing unit 100 and the shared resources 200 that are the object of the present invention are not limited to the illustrated processor (CPU) 1 and shared memory (CM) 2, but if the processing unit belongs to multiple processors, a single processor However, in any case, the effects of the present invention will be does not change.

〔Effect of the invention〕

As described above, according to the present invention, in the information processing system, when a processing unit requests the use of a shared resource, it only specifies the position to be used, and only the divided unit including the position to be used is transferred to other processing units. Since other processing units can be used in parallel for other partitioned units, the chances of waiting for shared resources are greatly reduced without complicating the control of processing units. , the processing efficiency of the information processing system is also improved.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the principle of the present invention, FIG. 2 is a diagram showing an information processing system according to an embodiment of the present invention, FIG. 3 is a diagram illustrating the flag determination process in FIG. 2, and FIG. 1 is a diagram showing an example of a conventional information processing system. In the figure, ■ is the processor (CPU), 2 is the shared memory (CM), l1 is the test and set setting section (TSS), and 12 is the test and set cancellation section (TSS).
R), 13 is a flag determining unit (FDC), 100 is a processing unit, 101 is a test-and-sent instruction execution means, 102
is a flag determination means, 200 is a shared resource, 201 is a division unit, 300 is a flag, Kihatsu gAIζ

Claims (1)

[Scope of Claims] Information that a plurality of processing units (100) are each equipped with a test-and-set instruction execution means (101) that blocks shared resources (200) from each other and makes them usable by the own processing unit (100). In the processing system, the shared resource (200) is divided into a plurality of division units (201), a blockage flag (300) is provided corresponding to each division unit (201), and each of the processing units (100) is provided with a blocking flag (300). ) requests the use of the shared resource (200), the address (a
__x), and determines a flag (300) corresponding to the divided unit (201) including the usage target position for each processing unit (100) based on the usage request and address (a_x); (102) is provided, and the flag (30
0) to the test and set instruction execution means (101)
The test and set instruction execution means (101) blocks only the division unit (201) corresponding to the flag (300) and makes it usable for its own processing unit (100). shared resource control method.