JPH02240968A - Manufacturing method of semiconductor device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention relates to a method of manufacturing a semiconductor device having an MO8 structure.

(Prior Art) When manufacturing a semiconductor device, a step of introducing impurities into a semiconductor substrate or the like is essential.

A conventional method for manufacturing a memory cell with a floating gate will be described with reference to FIG. A gate oxide film 2, which is an insulating film, is formed on a semiconductor substrate 1, and a floating gate 3 is formed on the gate oxide film 2. ((a) in the same figure) Next, a resist 12 is formed to cover a region of the MO5 structure that should be 5 sources, and an impurity having a conductivity type opposite to that of the semiconductor substrate 1 is introduced to form a diffusion layer 4.

((b) in the same figure) Next, after removing the resist 12, a control gate 6 is formed on the floating gate 3 on which an insulating film 5, which is an insulating film, is formed on the floating gate 3. However, a portion of the floating gate 3 is also formed on the gate oxide film 2 on the semiconductor substrate 1. ((C) in the same figure) Next, using the control gate 6 as a mask, the semiconductor substrate 1 is
A diffusion layer 7 is formed by introducing an impurity of a conductivity type opposite to that of the first dopant.

((d) in the same figure) From the diffusion layer 4 to the diffusion layer 7 of the floating gate 3
Let the length from the edge of the floating gate 3 on the side of the diffusion layer 7 to the diffusion layer 7 be F (offset length F). In this method, the effective length could be controlled by taking into consideration the expansion of the diffusion layer 4 due to the subsequent thermal process. However, since the diffusion layer 7 is formed by introducing impurities using the control gate 6 formed on the floating gate 3 as a mask, the accuracy of the offset length F is not good due to misalignment between the floating gate 3 and the control gate 6. There was a drawback.

The characteristics of a semiconductor device are shown in Figure 3 (a) when the length of L is constant.
) As shown in (b), it depends largely on the length of F. That is, if F is long, the amount of writing to Ce1l, vth, decreases, and as shown in 31, the program characteristics deteriorate. Furthermore, as shown in 32, the access time during reading becomes longer, and the operating speed of the semiconductor device becomes slower. On the other hand, if F is short, the problems of deterioration of program characteristics and increase of access time will be solved, but if the length of F becomes smaller than a certain value (0.5 μm in this example), bunch through occurs as shown in 33. The voltage drops suddenly. Therefore, if the value of F is too long or too short, problems will occur in the characteristics of the semiconductor device, and a method of manufacturing a semiconductor device that can accurately obtain a desired length of F has been desired for some time.

(Problems to be Solved by the Invention) As described above, in the conventional semiconductor device manufacturing method, the size under the floating gate can be controlled, but the size under the control gate varies, and the semiconductor device It was not possible to obtain stable properties.

Therefore, it is an object of the present invention to eliminate variations in the offset length F and to manufacture a semiconductor device with stable properties.

[Structure of the Invention] (Means for Solving the Problems) A method for manufacturing a semiconductor device according to the present invention includes a step of forming a floating gate and a dummy gate at a predetermined interval on an insulating film on a semiconductor substrate, and burying a filling material between the gate and the dummy gate; removing the dummy gate; introducing impurities into the semiconductor substrate using the filling material as a mask; and forming a second insulating film on the floating gate. and a step of forming a control gate on the second insulating film.

(Function) The characteristics of a semiconductor device depend on the length between the diffusion layers under the control gate. If the effective length is constant, it depends on the offset length F. In the method for manufacturing a semiconductor device of the present invention, when forming a floating gate on an insulating film on a semiconductor substrate, a dummy gate is formed at the same time separated by a desired length F, and a filling material is embedded between the floating gate and the dummy gate. After that, remove the dummy gate.

Further, impurities are introduced into the semiconductor substrate using the filling material having a length of F as a mask to obtain a desired length F between the edge of the floating gate and the diffusion layer.

Using the above method, the length of F can be controlled by the interval between the control gate and the dummy gate,
A highly accurate length of F can be obtained.

(Example) An example of a method for manufacturing a semiconductor device using the present invention will be described with reference to FIG. A gate oxide film 2, which is an insulating film, is formed on a P-type semiconductor substrate 1. Furthermore, a poly-8i film containing impurities, for example, is deposited on the gate oxide film 2 using a CVD method or a sputtering method. Next, after forming a mask using a photoresist method, RIE (React
Poly
The -8i film is selectively etched to form floating gates 3 and dummy gates 8, which are electrodes, and then the mask is removed. At this time, the offset distance F between the floating gate 3 and the dummy gate 8 is set to a desired size. (
(a)) Next, at least the portion where the diffusion layer 7 is formed is covered with a resist 12, and the drain portion is filled with, for example, As(
Arsenic) ions are implanted. (FIG. 2(b)) Next, after removing the resist 12, a filling material 9 such as TEOS (tetraexitosilane) or 5o-G (spin-on glass) is deposited on the entire surface including the offset portion. (
(C) of the same figure) Next, the embedded material 9 is etched back using the RIE method, and the etching is stopped so that the side wall portion 10 remains. (
(d) of the same figure) Next, a resist 11 is formed on the floating gate 3, and then CD E (Chemical Dry Etchl) is applied.
The dummy gate 8 is removed using the ng) method or the RIE method.

((e) in the same figure) Further, using the side wall portion 10 as a mask, an ion implantation method is used to implant, for example, As (arsenic) to form a diffusion layer 7 having a thickness of 5 sources. (The same figure (')) Next, using the CDE method, the side wall part 10 consisting of the resist 11 and the filling material is removed. (The same figure (g)) Next, the oxidation is applied on the floating gate 3 using the conventional method. A film 5 is formed, and a control gate 6 made of, for example, silicon containing impurities is formed on the oxide film 5.

When the semiconductor device manufacturing method of the present invention is used, the length of the offset F depends only on the accuracy of the spacing between the floating gate 3 and the dummy gate 8, and does not depend on the alignment accuracy between the floating gate 3 and the codon roll gate 6. On the other hand, when conventional semiconductor device manufacturing methods are used, the dimensional accuracy of the floating gate 3 and the control gate 6 are
The dimensional accuracy of F and the alignment accuracy of the floating gate 3 and control gate 6 are factors that cause variations in the size of F.

For example, dimensional accuracy is ±0.2μm9 alignment accuracy is ±082
μm, and if the value of F is set to 0.8 μm, the size of the offset F using the conventional manufacturing method will be 0.8 to 1.0 μm due to dimensional variations, and the floating gate 3 and control gate If the misalignment of 6 is included, the size will vary from 0.4 μm to 1.2 μm. However, when the semiconductor device manufacturing method of the present invention is used, only the formation error when forming the floating gate 3 is F.
Because it contributes to the variation in length, the value of F is at worst 0.
It falls within the range of 6 μm - 1.0 μm.

As shown in FIG. 3, the fiber characteristics of a semiconductor device depend on the length of F. As shown in figure (a), the program characteristics (Ce
The write amount to l1) and the access time deteriorate as the value of F is large, and improve as the value of F becomes small, but as shown in FIG. 12(b), when the value of F is small, the punch-through voltage drops rapidly.

In this example, if the value of F is less than 0.5 μm, the semiconductor device will not operate, so with conventional semiconductor device manufacturing methods, it is difficult to set the value of F to 0.8 μm, considering the factors of processing variations. Therefore, it is necessary to manufacture the semiconductor device by setting the length of F to be long, which causes deterioration in the programming characteristics of the semiconductor device and increase in access time.However, using the method for manufacturing the semiconductor device of the present invention, and F
Since semiconductor devices can be manufactured by setting the length of F as small as 0.8 μm, it is possible to improve the programming characteristics of the semiconductor device and shorten access time, and the accuracy of the length of F is good. A semiconductor device with stable characteristics can be manufactured.

[Effects of the Invention] According to the method for manufacturing a semiconductor device of the present invention, variations in the properties of the semiconductor device can be suppressed, and improvements in yield and characteristics can be achieved.

[Brief explanation of drawings]

FIG. 1 is a process diagram showing an embodiment of the semiconductor device manufacturing method of the present invention, FIG. 2 is a process diagram of a conventional semiconductor device manufacturing method, and FIG. 3 is the dependence of various semiconductor device characteristics on the value of F. shows. 1... Semiconductor substrate 2... Gate oxide film 3...
・Floating gate 4...Diffusion layer 5...Oxide film 6...Control gate 7...-Diffusion layer 8...Dummy gate 9...
・Embedded material lO...Side wall portions 11, 12.13
・・・Resist off and FOt piece) Should be

Claims (1)

[Claims] forming a floating gate and a dummy gate at predetermined intervals on an insulating film on a semiconductor substrate; embedding a filling material between the floating gate and the dummy gate; and removing the dummy gate. , a step of introducing an impurity into the semiconductor substrate using the filling material as a mask, a step of forming a second insulating film on the floating gate, and a step of forming a control gate on the second insulating film, A method for manufacturing a semiconductor device, comprising: