JPH02239349A - Circuit for detecting exception of virtual computer - Google Patents

Abstract

PURPOSE:To facilitate the detection of an exception at one step by previously holding a value obtained by subtracting a base address from an upper limit address on the real address of a virtual computer and comparing the address on the virtual computer with the value which has previously been held before the address on the virtual computer is converted into the address on a real computer. CONSTITUTION:An exception detection circuit consists of a first register 1 which previously sets the base address of the virtual computer, a second register 2 which inputs the address on the virtual computer and a third register 3 which sets the value obtained by subtracting the base address from the upper limit address on the real address of the virtual computer. The exception detection circuit is constituted in such a way. When the address on the virtual computer is inputted to the register 2, an adder 6 executes addition with the base address and outputs the address on a real storage to a fourth register 4. At the same time, a comparator 7 compares the value of the register 2 and that of the register 3, and exception information is reported from a fifth register 5 when the address on the virtual computer of the register 2 is large.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an exception detection circuit for a virtual machine, and particularly to an exception detection circuit for a virtual machine that allocates addresses on the virtual machine in real main memory in a continuous resident manner.

[Conventional technology]

Conventionally, this type of exception detection circuit for a virtual machine has been configured to store the second register 2 on the virtual machine when converting an address on the virtual machine to an address on the real main memory, as shown in block sections in FIG. The adder 4 adds the base address of this virtual machine in the first register 1 to the address of
The real address of the 4th register 4 calculated as a result and the 6th register
The comparator 7 compares the upper limit of the address on the real memory of the virtual machine, which is preset in the register 8, and if the real address in the fourth register 4 is larger, exception information is stored in the fifth register 5. is set and reported.

[Problem to be solved by the invention]

The conventional exception detection circuit of the virtual machine described above first
As a step, calculate the address on the real main memory by adding the address on the virtual machine and the base address,
Next, as a second step, we detect whether an exception has occurred by comparing the address calculated in the first step with the upper limit address of the virtual machine prepared in advance. This method requires two steps and has the drawback of reducing processing performance.

[Means to solve the problem]

The exception detection circuit for a virtual machine according to the present invention provides a value obtained by subtracting a base address value from the upper limit address value of the virtual machine on the real main memory in a computer that allocates addresses on the virtual machine in real main memory in a continuous resident manner. When the value accessed by the virtual machine is converted to a real address, the value accessed by the virtual machine is compared with the register that holds the register to see if it is larger than the value held in the register, and if it is larger, outputs exception information. It is constructed by having a comparator for

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention, in which the first register 1 is a register in which the base address of virtual calculation is set in advance, and the second register 2 is a register for setting the virtual calculation base address in advance. The third register 3, which is a register into which the address on the computer is input, is a register that sets the value obtained by subtracting the base address from the upper limit address on the virtual machine's real address, and the value of the first register 1 and the second The value of register 2 is input to adder 6, and the addition result is output to fourth register 4. On the other hand, the value of the second register 2 and the value of the third register 3 are input to a comparator 7, and when the value of the second register is large, exception information is set in the fifth register 5 and reported. ing.

With the above configuration, when an address on the virtual machine is input to the second register 2, the adder 6 performs addition with the base address, and the address on the real memory is output to the fourth register 4. On the other hand, at the same time, the value of the second register 2 and the value of the third register 3 are compared by the comparator 7, and when the address on the virtual machine of the second register 2 is large, the exception information is transmitted from the fifth register 5 to the system. Reported.

〔Effect of the invention〕

As explained above, in the present invention, the value obtained by subtracting the base address from the upper limit address on the real address of the virtual machine is held in advance, and before converting the address on the virtual machine to the address on the real computer, Since an exception is detected in one step by comparing the address on the virtual machine with the above-described subtracted value held, there is an effect that processing performance is not degraded.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a block diagram of a conventional exception detection circuit for a virtual computer. 1...First register, 2...Second register, 3...
・3rd register, 4...4th register, 5...5th register
Register, 6... Adder, 7... Comparator, 8...
6th register. male IQ

Claims (1)

[Claims] In a computer that allocates addresses on a virtual machine to real main memory in a continuous resident manner, there is a register that holds the value obtained by subtracting the base address value from the upper limit address value of the virtual machine on the real main memory, and a register that is accessed by the virtual machine. when the accessed value is converted to a real address, compare whether this accessed value is greater than the value held in the register;
1. An exception detection circuit for a virtual computer, comprising: a comparator that outputs exception information when the exception is larger.