JPH02238556A - Process scheduling methods and multiprocessor systems - Google Patents

Abstract

PURPOSE:To execute the processes via the prescribed processors respectively by obtaining a system where a process scheduler actuates a selected process to be executed next via a processor designated by the processor allocation information on the processes and by reference to a process control table. CONSTITUTION:The processor identifiers 321-2 of a processor 2 is set at 1 and therefore the process 2 is executed by a processor P1. A process 1 can be executed by the processors except a processor P2 since the processor identifier 321-1 of the process 1 is set at 2. The idle processors are limited to the processors P2 and P3 and therefore the process 1 is executed by the processor P3. The processor identifier 321-3 of a process 3 is set at 0 and therefore the process 3 can be executed by any processor. In this case, the idle processor 2 is used. As a result, the processes can be executed by the prescribed processors respectively even in a uniform multiprocessor system.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a multiprocessor operating system that runs multiple processes in parallel in a multiprocessor system consisting of multiple processors. Concerning a process scheduling method suitable for building a system, for running a program created for a single processor without any changes on a multiprocessor system, and when there is a process that includes instructions that can only be executed by a specific processor. .

[Prior Art] A system that uses a plurality of processors to execute a plurality of processes in parallel to improve system performance is well known as a multiprocessor system. Such a multiprocessor system was developed in Japanese Patent Application Laid-Open No. 56-12
As disclosed in Japanese Patent No. 7261, a plurality of processors are connected to each other and to a shared memory via a bus.

Furthermore, in order to effectively and efficiently operate a multiprocessor system, a multiprocessor operating system plays an important role.

In a multiprocessor operating system, unlike a single processor system, it is necessary to allow multiple processes to be executed simultaneously on different processors. For this reason, it is necessary to have a strategy for determining which processor a process is assigned to. The most commonly used strategy is to
In order to maximize the utilization efficiency of the processor, it is assigned to the processor with the least load. This strategy is generally easy to implement and is therefore widely adopted. This is because the process scheduler of the operating system running on each processor can select the next process to be executed according to the priority of the process, as in the case of a single processor system. In a heavily loaded processor, processes take a long time to execute and the process scheduler is activated less frequently. Conversely, a processor with a light load often enters an idle state without any processes to process, and therefore there are many times when a process scheduler is activated to determine whether or not to transition to an idle state. Therefore, processors with light loads are given more opportunities for process scheduling, and the loads among the processors are automatically balanced.

Such a strategy for allocating processes to processors is a reasonable method in a homogeneous multiprocessor system in which each processor has the same function. On the other hand, as a method for allocating processes in a multiprocessor system in which processors with different functions coexist, Japanese Patent Laid-Open Nos. 62-123552 and 1982-123553 have been proposed. What is called a "task" in these prior art corresponds to the "process" referred to in this specification, and has the same meaning. In these prior art techniques, for example, when an attempt is made to execute a process that uses floating-point accelerator-specific instructions on a processor that does not have a floating-point accelerator, the operating system detects an exception and runs an alternative processor. This method refers to a management table and switches execution to a processor that has a floating-point accelerator, and represents one method for allocating processes in a heterogeneous multiprocessor system.

The advantage of this method is that the programmer does not have to be aware that the system is a heterogeneous multiprocessor.

[Problems to be Solved by the Invention] Incidentally, in real-time systems such as chemical plants, transportation, and power control systems, detailed recovery processing for failures is built into the system in advance in accordance with the required reliability. Among these, processor failures are strictly controlled because they have a serious impact on the system. The basic idea for ensuring reliability in such systems is to localize the range of influence of failures. In the conventional multiprocessor systems described above, sufficient consideration has not always been given to this point.

It is also desirable that existing software developed for a single processor be able to run on a multiprocessor system without any changes. In a multiprogramming environment, as is well known, contention for access to shared data can occur between multiple processes. To solve this problem, it is usually necessary to perform exclusive control using a semaphore mechanism etc. when accessing shared data, but the processing overhead of the semaphore mechanism becomes a problem, so it is necessary to make processes have the same priority, or to In many cases, measures such as raising the interrupt mask of a processor whose processing time is shorter than that of the mechanism to disable interrupts are taken.

These means utilize the fact that when viewed from a microscopic perspective on a single processor, processing on the processor is always performed sequentially. In reality, many software programs do not perform exclusive control over shared data for performance reasons. Therefore, when existing software is executed as is on a multiprocessor system, there is a problem in that normal operation is not necessarily guaranteed.

As a problem in system construction, when starting up a multiprocessor, it is necessary to perform processing related to only one resource in the system, such as initializing a shared memory and loading an operating system program. Performing this process using multiple processors will only unnecessarily complicate the process, so it is preferable to perform this process using one processor in advance, and then start up the other processors to initialize the processor-specific resources. You need to take steps. The same applies when the system is stopped, and the process of stopping an individual processor may require accessing hardware resources such as registers that can only be accessed by that processor.

In addition, in multiprocessor systems, in order to maximize processor performance, it is customary for each processor to have its own cache memory, but when the operating processor changes during the execution of a process (this is called process migration), , since the cache memory that was used immediately before can no longer be referenced, a cache memory mishint occurs on the newly operating processor. Furthermore, it is also necessary to invalidate the cache memory on the processor that was running immediately before, and multiprocessor processing is actually a factor in reducing the performance of the process compared to when it is executed on a single processor. Become.

JP-A-62-123552 and JP-A-62-123 mentioned above
Although the multiprocessor system disclosed in No. 553 uses the occurrence of exceptions to deal with a non-uniform multiprocessor system, it cannot solve the above-mentioned problems in a homogeneous multiprocessor system.

On the other hand, Japanese Patent Application Laid-Open No. 62-251867 discloses that a processor identification code is attached to each instruction code of the main memory program itself, and each time an instruction code is read, the processor that should execute the instruction is identified. A multi-processor system is disclosed that determines a processor identification code according to its processor identification code. In this multiprocessor system, it is necessary to modify the program to add a processor identification code to each instruction unit of the program, and existing software cannot be used as is. Another problem is that it is necessary to change hardware such as the word width of the main memory and the instruction decoder. Furthermore, it is not possible to dynamically change the processor identification code, and it is difficult to deal with changes in the number of processors.

An object of the present invention is to provide a process scheduling method that allows a specific process to be executed on a predetermined processor regardless of the occurrence of an exception, not only in a heterogeneous multiprocessor system but also in a homogeneous multiprocessor system. An object of the present invention is to provide a processor system and a method of using the same.

Another object of the present invention is to provide a process scheduling method, a multiprocessor system, and a method for using the same, in which existing software for a single processor system can be used as is without any modification.

Still another object of the present invention is to provide a process scheduling method, a process scheduler, and a multiprocessor system that enable efficient use of multiple processors while preventing process migration. be.

[Means for Solving the Problems] In order to achieve the above object, a process scheduling method according to the present invention includes a plurality of processors and a shared memory that stores programs and data and is shared by the plurality of processors. , multiple processors above,
In a multiprocessor system controlled by a single operating system, programs and data are processed using a process scheduling method in which a process scheduler of the operating system allocates one of the processors to a process according to a process management table that manages processes, The process management table describes processor allocation information that indicates which processors each process can operate on, and the process scheduler refers to the process management table to determine the process selected to be executed next. The process is run on the processor specified by the processor allocation information.

From another point of view, the process scheduling method according to the present invention is a process scheduling method in which a processor is assigned to each process in a multiprocessor system in which a main memory is shared by a plurality of processors, and in which each process is Processor allocation information specifying possible processors is stored in the storage device, and when a process waiting to be executed is allocated to a processor, the processor allocation information of the process is referred to, and according to the processor allocation information, It is configured to determine whether or not to allocate the processor to the process.

Instead of the processor assignment information that specifies, for each of the processes, a processor on which the process can run, process assignment information that specifies, for each of the processors, a process that the processor can execute may be used.

According to yet another aspect, the process scheduling method of the present invention associates each process with a processor on which the process can operate in advance, and when allocating an empty processor to a process waiting to be executed, Based on the correspondence relationship, it is determined whether or not the processor can be assigned to the process.

The processor allocation information may include a general-purpose code indicating that it can operate with any processor, or a code indicating that it can operate with a processor other than a specific processor.

As another process scheduling method of the present invention, for a process in which the above-mentioned general-purpose code is set as the above-mentioned processor allocation information, after the processor that executes the process is determined and before the execution of the process starts, It is also possible to change the processor allocation information to a code that specifies the processor, and then return the process allocation information to the general-purpose code after the execution of the process is completed. Regarding this operation method, an area is provided in the process management table to store a control mode for each process, and as one of the control modes,
A code specifying this method may be defined.

Furthermore, as one of the control modes, a code indicating that the processor allocation information is always fixed is defined,
For the process to which the code is specified, the processor allocation information may not be changed before and after the process is executed.

According to another aspect, the process scheduling method according to the present invention is a process scheduling method in a multiprocessor system having a plurality of numbered processors and a shared memory shared by the plurality of processors, the method is A process management table for managing the processes to be executed is provided in the shared memory, processor allocation information indicating the number of operable processors for each process is stored in the process management table, and the process scheduler executes the next process. The process management table is referred to for the selected process, and the process is operated on the processor corresponding to the number specified by the processor allocation information of the process.

In numbering the processors, it may be possible to allow the same number to be assigned to a plurality of processors more than once.

In addition, a general-purpose code is defined as one of the processor numbers mentioned above, and each process is executed on the processor with the number specified in the processor allocation information of the process or on the processor assigned the number of the general-purpose code. You can also

Still another process scheduling method according to the present invention determines, for each process, the degree to which execution on a processor other than the one designated by the processor allocation information is refused as a numerical value indicating the degree of affinity between the process and the processor. The value is determined in advance, and compared with the numerical value related to the execution waiting state of the process, and according to the comparison result,
The process is run on a processor other than the processor specified above. As the numerical value related to the execution waiting state of this process, for example, the number of times the allocation to the processor has been rejected or the amount of data waiting for execution of the process can be selected.

Processor allocation information used when specifying a processor from the above process is a logical processor identifier, and a table is provided in the shared memory that associates the logical processor identifier with a physical processor identifier corresponding to an actual processor. Scheduling may be performed by converting it into a physical processor identifier.

The process scheduling method of the present invention that utilizes process priorities determines in advance the priority range of processes that can be executed by each of the plurality of processors, and the priority range of processes that each processor should execute next. As the process, the one with the highest priority is selected from among the processes waiting to be executed that have priorities within the range of priorities determined for the processor.

Another process scheduling method of the present invention that utilizes process priorities determines the priority for each of the plurality of processors for each process, and selects a process that is waiting to be executed as the process that each processor should execute next. Among these, the one with the highest priority of each process determined for the processor is selected.

A multiprocessor system according to the present invention has at least two processors, and in a multiprocessor system in which a specific process can be executed on any of the processors, a processor that executes the specific process is connected to the at least two processors. By fixing to any one of the
This allows the software to be used without modification.

According to another aspect, the multiprocessor system according to the present invention has at least two processors and is capable of executing a specific process on any of the processors, at least starting execution of the specific process. The processor on which the specific process is executed is fixed to one of the at least two processors from the time to the end, thereby preventing the execution processor from being changed during the execution of the specific process. This is how it was done.

According to yet another aspect, the multiprocessor system according to the present invention has at least two processors, and in a multiprocessor system in which a specific processor can execute various processes, a process that is executed by the specific processor is provided. By limiting the number of processors, the response time of the processor is reduced to within a certain value.

According to another aspect, the multiprocessor system according to the present invention has at least two processors, and in a multiprocessor system in which a specific processor can execute various processes, one of the processes to be executed by the specific processor is By limiting the types, the range of influence of a processor failure is localized.

According to yet another aspect, the multiprocessor system according to the present invention includes a plurality of processors and a shared memory that stores programs and data and is shared by the plurality of processors, the programs and the data. In a multiprocessor system controlled by a single operating system, a process management table is provided in the shared memory to maintain the state of each process, and the process management table indicates whether each process is operable. A storage area is provided to store processor allocation information specifying processors.

Another multiprocessor system according to the present invention includes at least two processors, each of which can execute a specific process, and a shared memory that stores programs and data and is shared by the at least two processors, The processor, program, and data are stored in the shared memory in a multiprocessor system controlled by one operating system, such that only a specific processor of the at least two processors can execute the specific process. A storage area is provided to store processor allocation information.

In a system having a storage area for storing processor allocation information, a storage area may be further provided for storing a control mode for controlling dynamic change of processor allocation information for each process. This control mode includes, for example, a first mode that allows operation with any processor, and a second control mode that allows operation only with a specific processor from the start of process execution to the end of execution. In the control mode, a general code that specifies an arbitrary processor is set as processor allocation information, and in the second control mode, before starting a process on a specific processor,
The specific processor is specified as processor allocation information for the process, and the processor allocation information is returned to the general-purpose code after execution of the process is completed. In addition to both control modes, a third control mode may also be provided in which processor allocation information specifying a particular processor is not changed after the process is created.

A method of using a multiprocessor according to the present invention is a method of using a system that specifies the processor allocation information, wherein the processor allocation information is set to be the same for a group of processes that require exclusive control over the shared memory. This allows the above process group to operate on a single processor. Similarly, separate processor allocation information is set for a process group of high importance and a process group of low importance, and both process groups are assigned separate processors.
You can also run it in two steps.

Another method of using a multiprocessor according to the present invention is a method of using a system using a control mode, in which by setting the second control mode, it is possible to change the executing processor during execution of one process. It is intended to prevent Similarly, by setting the third control mode for a process group that requires exclusive control over the shared memory, the process group can be operated by a single processor. Furthermore, the processes are classified into a process group of high importance and a process group of low importance, and the above-mentioned third control mode is set for both process groups, and different processor allocation information is set for the above-mentioned both processes. , it is also possible to have both of the above process groups executed on separate processors.

[Operation] The process scheduling method of the present invention is intended to intentionally limit the number of processors that execute a process that can be executed by any of the plurality of processors to a specific processor ratio in a multiprocessor system consisting of a plurality of processors. It is.

This makes it possible to run a group of processes that require exclusive control on the same processor, and to use existing single-processor processors that do not consider exclusive control over shared memory without modifying them. normal operation can be guaranteed. This does not mean that other processors are not used, but for processes other than the above process group, any (or any processor other than a specific processor) can be used without such restrictions.
Since it can be executed by a processor, the functions of a multiprocessor can be effectively utilized.

In addition, by limiting the processors that execute the program according to its reliability rank, the system will not go down even if a processor that is executing offline processing such as program development that does not require high reliability fails. (i.e., localize the fault).

Furthermore, when trying to run software that includes a group of programs that are not subject to regular exclusive control on a multiprocessor system, the program can be modified by having only that program group run on a specific processor. Normal operation can be guaranteed without any problems.

In addition to the method of specifying a specific processor as described above, in addition to the method of specifying it in a fixed manner at all times, the method of specifying a specific processor from the start of execution to the end of execution of a process can be done by assigning it to a specific processor, suspending or
A method that prevents the operating processor from being changed even when restarting is also useful. In other words, according to this method of temporarily fixing the processor, once a process has started execution,
Since the operating processor is not changed during execution, it is possible to prevent the cache hit rate from decreasing in a system using a cache memory. On the other hand, since this method does not permanently fix the executing processor, it does not significantly impede efficient use of multiple processors.

Methods for permanently fixing a specific processor for each process, or for temporarily fixing (dynamically specifying), include introducing the above-mentioned control mode, limiting the priority range of executable processes for each processor, Various methods can be used depending on the purpose, such as setting priorities for each process for each processor and introducing the concept of affinity between processes and processors.

(Hereafter, margin) [Example code] The system configuration according to the present invention is shown in FIG. 1(a).

Three processors, processors Pi, P2 and P3, are connected to each other and to a shared memory 5 by a connection bus 4. Each processor has a processor number 11-1~
They each have 11-3. In this embodiment, processors PI, P2, and P3 each have a processor number Zl.
l II, II 2 II, II 3 I
It has I. In this embodiment, the processor number is set using a hardware switch, but other methods include storing the change in the hardware ROM, or setting it using a program at startup. .

Each process runs on a processor. shared memory 5
includes an operating system program 31 and a process scheduler 3 that is part of this program 31.
11. Program 31 of this operating system
There is a process management table 32 (32-1 to 32-3) that is a part of the tables managed by . This process management table 32 includes process priorities (not shown).
etc., processor identifiers specific to the present invention 3 2 1 (
321-1 to 321-3), a processor control mote 3 that controls the dynamic change or fixed period of the processor identifier;
22 (322-1 to 322-3) are placed.

Note that in this embodiment, the existing process management table 32
However, a separate table may be provided for each processor to store process identifiers that specify the processors that can be executed by that processor.

FIG. 1(.) shows a case where process 1 is executed by processor P3, process 2 by processor P1, and process 3 by processor P2. Note that although processes are shown in the blocks of each processor in the figure, this only shows the state in which the process is being executed on a specific processor, and does not show the actual location of the process. In this example, since the processor identifier 321-2 of process 2 is "1", this process 2 is
It is being executed on processor P1. Since the processor identifier 321-1 of process 1 is II 2 II, it can be executed by a processor other than processor P2. The free processor is
Since there are processors P2 and P3, process 2 is being executed by processor P3.

Processor identifier 321-3 of process 3 is tt O
n, so it can be executed on any processor. Therefore, the processing is executed by the remaining free processor P2. In this example, only a single code is written as the processor identifier 321, but it is also possible to write multiple codes at the same time. In this case, a negative value is not necessarily necessary.

Processes 1 to 3 and process management table 3 for each process
2-1 to 32-3 correspond to each other, and when a process is generated, a corresponding process management table is also generated. When a system is started up, a process that is the basis of all processes is generated by the operating system program 31. The processes 1 to 3 are generated from this original process. This flow 39 will be explained using FIG. 1(b).

In FIG. 1(b), the process that is the origin of all the above processes is process O (not shown in FIG. 1(a)).
It is shown. At startup, the operating system program 31 generates process 0 based on system configuration information predefined by the user.
A specific processor number is set in the processor identifier 321-0 of process O. This is because it is necessary to initialize all data on a specific processor at startup, and after completing data initialization, process O is a system that rewrites its own processor identifier supported by the operating system. In the call, the own processor identifier 321-0 is specified so that it can be executed by any processor.
is rewritten to /IQ''. After that, processes 1 to 3 are generated, but this generation also uses a system call supported by the operating system, and the processor identifier is specified as a parameter of this system call.

There are two types of process creation system calls: one that explicitly specifies a processor identifier, and one that automatically inherits the processor identifier of the original process.

In FIG. 1(b), initially process 0 is processor P1
First, process 1 was created by specifying 11 2 I+ as the processor identifier.

As a result, process 1 can be executed on processor P1 or processor P3, but since processor P1 is already in use, it is executed on processor P3. next,
Process 2 has been created, which has processor identifier N
Since it was created in I I+, process O moved to processor P2 and started executing process 2 on processor P1. Next, since process 3 was created by a system call that automatically takes over the processor identifier of the original process, process 3's processor identifier 321
-3 became II O II. In FIG. 1(b), process O temporarily waits on shared memory 5, and processor P
2 is opened and then process 3 is started to be executed. In principle, five processes are generated as described above, and the processor identifier is also set.

FIG. 2 shows the processing of the process scheduler 311.

The process scheduler is a program that is part of the OS and can be executed by any processor, and is assigned to a processor that becomes free after the execution of a process is terminated or interrupted. When assigned to a processor, the process scheduler first selects the process to be executed next according to the priority of the process (311-1). In a conventional process scheduler, the process selected here is assigned to the processor on which the scheduler is currently running (31.1-3). Finish the process. The process scheduler according to the present invention determines the value of the processor identifier 321 in the process management table 32 of the selected process (311-2). If this value is IIO I+, it means that it can be executed by any processor, so the process 311-3 is performed and the process ends.

If the value of the processor identifier 321 is positive, it means that execution is possible only on a processor with a processor number that matches the value of the processor identifier. Therefore, the scheduler refers to the currently running processor number 11, and this is the processor identifier. Determine whether it is equal to 321 (3
11-4). At this time, if there are multiple processor identifiers, it is determined whether they are equal to each processor identifier, and if they are equal to any one of them, it is determined that they are "equal". If they are equal, the process proceeds to step 311-3; if they are not equal, the process cannot be executed by the processor on which the scheduler is currently running, so the process returns to step 311-1 in order to select the process with the next highest priority. On the other hand, if the value of the processor identifier 321 in process 312-2 is negative, it means that execution is possible only on a processor other than the processor whose processor number matches the value obtained by changing the sign of the value of the processor identifier. Processor number 11 is running
, and determines whether this is equal to the processor identifier 321 (311-4). At this time, if there are multiple processor identifiers, it is determined whether each processor identifier is equal or not, and when all of the processor identifiers are equal, it is determined as "equal". If they are not equal, proceed to process 311-3; if they are equal, the process cannot be executed by the processor on which the scheduler is currently running, so the process with the next highest priority is selected. Return to 1-]. At this time, if multiple processor numbers are assigned to one processor, the above process is repeated for each processor number before selecting the next process.

There are three methods for setting the processor identifier 321, summarized as follows.

The first method is for an original process that creates a process (hereinafter referred to as a parent process) to set a processor identifier through a system call to the operating system. This method includes explicitly setting the processor identifier using a system call, and implicitly inheriting the processor identifier of the parent process or setting the general-purpose code LL Or+. The method for setting the implicit processor identifier may be selected from one of 44 methods convenient for each system.

The second method is for the generated process to set the processor identifier itself through a system call of the operating system.

The above has been explained with reference to FIG. 1(b).

The third method is that when a process is created, it contains code that can be executed on any processor (i.e., general-purpose code), but when executed on any processor,
In this method, the processor identifier is set to the number of that processor, the code is executed only on that processor, and when it is finished, it is returned to a general-purpose code that can be executed on any processor, and the next execution process can be executed on any processor.

In particular, in order to realize this third method, the processor control mode 3 2 2 (322-0. 322-1
, 322-2, 322-3) is the process management table 32 (32-0.32-1., 32-2.
32-3). This processor control mode includes a mode in which the processor is not fixed, and a mode in which the processor is not fixed.
There is a mode that temporarily fixes the process execution from start to finish. Here, the case where the processor is not fixed is set as 110'', and the case where the processor is temporarily fixed is set as LL I I+.

Furthermore, once generated, the case where it is always fixed is defined as II 2 +1. In this case, the process management table is reserved only when the process is first created, and
This management table is not released at the end of the process, and the management table used last time is used when generating the process for the second time onwards, so that the processor identifier that has been set once is always used.

In the first method and the second method, the processor control mode is automatically set to LL Q j+. In the third method, it is necessary to be able to specify a processor control mode in addition to a processor identifier when creating a process, and a system call for this purpose is provided in the operating system. This method will be explained below using figures.

FIG. 3 shows the process generation process of this method.

The operating system is passed a processor control mode and a processor identifier through a system call, which are shown as mode and procid in the figure. When a system call is issued, the operating system first secures the process management table 32 for generation (12-2), then performs the previous process generation process 122, and finally sets the operating processor 12-2. Do step 2.

In the operation processor setting process 12-3, as shown in the flow 312 of FIG. 4, the value of the specified processor control mode mode is first checked (312-0),
”, as shown in FIG. 4, set the value of mode in the processor control mode 322 of the process management table 32 (31.2-2), and
The value of procid is set in (312-3).

In step 312-0, the processor control mode value is 11.
2”, the processor control mode 322 for the process in the process management table 32 is already 112.
” (312-1), II 2
If it is TI, the process shown in FIG.
{Set III and procid values. The process generated in this way is selected by the process scheduler shown in FIG. 2 and executed on any processor based on the processor identifier 321. FIG. 5 shows the processing when this is executed.

In the process execution process shown in FIG. 5, the parts surrounded by broken lines are the parts added according to this embodiment. First, the address of the process management table 32 of the process to be executed is obtained (313-1), and the value of the processor control mode 322 of this process management table is determined (31.3).
-2). If this value is re O rr, the processor is not fixed, so a general code "0" is set in the processor identifier 321 of the process management table (313-4).

Furthermore, when the value is rr 1 u, it is fixed from the start to the end of the process execution, so the processor identifier 3 of the process management table
21 is set to the processor number 11 of the processor determined by the scheduler (313-3). If the value is
In the case of 2'', nothing is done because the processor is always fixed.

After the above processing, the user program is executed (31
3-5).

FIG. 6 shows an example of a process termination process related to implementing the third method of setting the processor identifier.

In this example, first, the address of the process management table 32 of the process to be terminated is obtained (314-1). The value of the processor control mode 322 of the process management table is determined (314-2).

When this value is "1", the pro. Since this is a case where the process is fixed from the start to the end of execution, a general-purpose code (value is II Or +) is set in the processor identifier 321 of the process management table (314-
2). This processor control mode is 1101 and ″2
'', there is no need to change anything, so do nothing. After the above processing, terminate the previous process (314
-3).

As mentioned above, if the mode in which the processor is always fixed, that is, the processor control mode LL 2 11, is set at the time of process creation, no changes will be made during the execution, as shown in the process execution process in FIG. Also, in the process termination process of FIG. 6, step 314
Since the determination of −2 indicates that the processor is other than LL I II, the value set in the process generation process is left unchanged as the processor identifier. Since the process management table is also saved, the set processor identifier and processor control mode are saved until the next process generation. When creating the next process, search for the previously used process management table, and if the processor control mode is already set to "2", by not rewriting the processor identifier,
Save processor identifier.

As described above, a process whose processor control mode is "2" will continue to run forever on the processor once assigned, unless the control mode is changed by a user's request.

The effects of the operating processor setting method described above are as follows. The first method is to solve the system construction problems such as the reliability problem in the real-time system, the usability of existing software, system startup, etc. mentioned in the above problem, and the second method is to solve the problem in the system construction such as the reliability problem in the real-time system mentioned above. This solves system construction problems such as reliability problems and system startup. Also,
The third method is to prevent performance degradation due to the process migration.

Here, the reason why process migration can be prevented by the third method will be briefly explained. After a process that can be executed on any of the nine processors is executed on a certain processor, it goes into a wait state due to input/output device access, etc., and once that processor is handed over, the suspended state is released and execution resumes. In the past, when a task was executed, it would not always be assigned to the processor that was executing it last time. Therefore, process migration occurs if the processor is assigned to a different processor. However, in the third method, a user-specified processor identifier is set in step 3123 in FIG. 4 when a process is created, but in step 3 in FIG.
The processor number 11 set in the processor identifier 321 at the start of the process execution shown in 13-3 is maintained unchanged even if the process execution is interrupted thereafter, and the processor number 11 shown in FIG. It will not be changed until the end. Therefore, in process scheduling (Fig. 2) when resuming execution after execution is interrupted, the processor identifier 321
A specific processor number set to is used, and when execution is resumed, it will always be executed on the processor with this processor number. Therefore, no process migration occurs. Note that after the execution of the process is completed, the processor identifier is set to II, as shown in step 314-2 in FIG.
Since O I+ is set, the processor on which this processor is executed next is not limited.

FIG. 7 shows an example of application of the embodiment of the present invention. In this example, multiple processors are allowed to have the same processor number. The processing of the scheduler 311 is the same as that shown in FIG.

The processor identifiers 321 of processes 2 and 3 are both I
I I I+ and processors P1 and P2 = 5
2- Since both have processor numbers II I I+, processes 2 and 3 can run on processor P1 or P2. According to this example, processors P1 and P2
The advantage is that flexible processor assignment, such as automatic load balancing and assigning another job to processor P3, can be easily achieved without changing the operating system.

Further, FIG. 8 shows another application example of the embodiment of the present invention.

In this example, similar to FIG. 7, multiple processors are allowed to have the same processor number, but by specifying a negative value rr-1n for the processor identifier 3211 of process 1, the processor number LL The processors P1 and P2 having II+ are not operated. The specific application of this embodiment is that processors P1 and P2 are online control processors, and process 1 is a test program under development, so that it does not affect online control at all. There are cases where you want to avoid this.

This example produces effects such as the ability to easily realize flexible processor allocation without changing the operating system, similar to that shown in FIG.

Note that processor number 11 also has a general-purpose code (for example, II
O JJ ), and a processor with general-purpose code may be able to execute any process.

In this case, any process can be executed by the processor regardless of the contents of the processor identifier of each process.

Next, an example of allocation of processes to each processor when the present invention is applied to plant control will be explained using FIGS. 9 and 10. FIG. 9 shows the multiprocessor system in FIG. 1 including a plant control equipment PC, a terminal T1, a terminal T
2. This is a system configuration diagram in which online files OF are connected, and FIG. 10 shows an example of allocation of processes and processors operating in this system.

Here, the following five processes will be considered as shown in FIG. Terminal T1 control process 91 for controlling terminal T1, Terminal T2 for controlling terminal T2
Control process 92, statistical information in online file OF
Statistical information logging process 93 for logging plants, plant control process 9 for controlling plant control equipment PC
4. There is an abnormality monitoring process 95 that monitors the occurrence of abnormalities in this system. Processors PL, P2, P3 in FIG.
correspond to PL, P2, and P3 in FIG. 9, respectively, "○" indicates that the process is designated to operate on that processor, and KL ×++ indicates that the process is designated to operate on a processor other than the processor. This indicates that the operation has been specified, and no mark indicates that the operation has been specified for any processor.

In the system shown in FIG. 9, terminal control and plant control are the main processes, so the terminal T1 control process 9 is assigned to the processor P1, the terminal T2 control process 92 is assigned to the processor P2, and the plant control process 94 is assigned to the processor P3. -55= so that they do not interfere with each other's processing. The statistical information log process 93 is a process that only needs to operate in the free time of each processor.

On the other hand, since processor P3 is used for plant control, in order to ensure that this process is completed within a certain time, even if there is free time, it is desirable to avoid performing other processes during that period as much as possible. I have a request. Therefore, the statistical information log process 93 is specified to run on a processor other than processor P3. Note that since the abnormality monitoring process 95 wants to monitor each processor, it is allowed to run even on the processor P3, so that it can run on all processors.

Further, the abnormality monitoring process 95 designates the next processor to operate, and monitors each processor in turn.

By assigning each process to a predetermined processor as described above, the processing of the plant control system shown in FIG.
It becomes possible to perform the process efficiently in a manner that is optimal for the system.

(Hereafter, margin) Next, a second embodiment of the present invention will be described in detail.

FIG. 11 shows an example of the configuration of the multiprocessor system in this embodiment. In this embodiment, means 210 (210-1, 210-2,
210-3) and 2 1 1 (211-1, 211
-2, 211-3) are provided corresponding to each processor.

This priority holding means can be constructed from a special register within each processor, or by allocating a specific address on the shared memory for this purpose. On the other hand, the process management table 32 includes priority (PR) 212 (212-1, 212-2, 212) indicating the execution priority of each process.
-3) is maintained. In this embodiment, the smaller the numerical value, the higher the priority. This priority is
Although the priority may be determined dynamically or statically, this embodiment does not depend on the method of determining the priority itself. In this embodiment, the process waiting to be executed is processed by processor P1.
~The process of allocating P3 is performed by the process scheduler 215
will do. The other parts of FIG. 11 are the same as FIG. 2.

FIG. 12(.) is a detailed processing flow of the scheduler 215. In this scheduler, first, in order to obtain the priority of a process executable by the processor on which the scheduler is running, the lower limit (LPR) and upper limit (HPR) are set to the priority holding means 210, 211 of the processor. (215-1). Next, priority 212 is selected from among the processes waiting to be executed.
Select the one with the highest (minimum numerical value) (215-2
).

If the priority of the selected process falls within the priority range executable by the processor (21
5-3). The process is assigned to the selected process (215-5). Otherwise, the process with the next highest priority is selected (215-4).

The operation of this scheduler will be explained using an example.

For example, in FIG. 11, consider a case where the scheduler 215 is operating in the processor P3 and processes 1 to 4 are in a waiting state for execution. The scheduler 215 first determines that the executable priority on the processor P3 is "50".
We know that it is between “1 0 0”. Therefore,
The process with the highest priority among the processes waiting to be executed (
``2 5 '') Process 3 is selected, but since this is outside the executable priority range of processor P3, process 1, which has the next highest priority (``4 0''), is selected.

Finally, process 4 (priority value If 5 5
II) is selected, and the scheduler 215 allocates processor P3 to process 4.

With this embodiment, low priority processes 2 and 4 are always given an opportunity to execute, thereby preventing problems such as low priority processes not running at all when many high priority processes occur. becomes possible. Furthermore, by eliminating overlap in the priority ranges of executable processes of each processor, the relationship between processors and processes can be fixed.

FIG. 12(b) shows another detailed flow of the scheduler 215. In this example, step 21 in FIG. 12(a)
Step 2 1.5 - instead of 5-2 to 215-4
6 to 21.5-8 are adopted, and it is checked in order from the one with the smaller HPR value (that is, the one with the higher priority) whether there is a corresponding process waiting to be executed. The result obtained from this is the same as the flow in FIG. 12(.).

Next, a third embodiment of the present invention will be described in detail. The configuration of the multiprocessor system according to this embodiment is shown in the thirteenth section.
As shown in the figure. In this embodiment, the priority of each process in the process management table 32 is not set commonly to all processors, but the priority of each process can be set for each processor. for that,
The process management table 32 includes, for each process, priorities 231, 232, and 23 that indicate the execution priority of the process in each of the processors P1 to P3.
Hold 3.

In this embodiment as well, the method of determining the priority itself does not matter. In this embodiment, the process scheduler 234 performs the process of allocating the processors P1 to P3 to processes waiting to be executed.

The other parts of FIG. 13 are the same as FIG. 1.

FIG. 14 is a detailed processing flow of the scheduler 234. The scheduler 234 first obtains the processor number of the processor on which it is operating. (234-1
). Next, the process with the highest priority at the position corresponding to the processor number in each process management table 32 is selected (234-2). Then, the processor is assigned to the process (234-3).

Next, an example of the operation of this scheduler will be explained.

For example, in FIG. 13, consider the case where the scheduler 234 is operating on the processor P3 and processes 1 to 4 are in a waiting state for execution. The scheduler 234 first obtains the processor number and recognizes that it is operating on the processor P3.

Then, it searches the priorities 231-1 to 231-4 corresponding to the processor P3 in the process management table 32, selects the process 3 to be executed next, and assigns the processor to it. Incidentally, regardless of the type of processor, the process 1 has the highest priority among the processes 1 to 4 waiting to be executed, and its priority is 1'20''. However, this priority 231. -] is for processor P1, so it is ignored when scheduler 234 is operating on a processor other than P1.

According to this embodiment, a high priority can be set for a specific processor for each process, and that process can be fixed to approximately one processor. However, even if that processor stops, the process does not become impossible to run; it can still be executed on another processor, although its priority will be lowered.

Next, a fourth embodiment of the present invention will be described in detail.

The configuration diagram of the multiprocessor system according to this embodiment is as follows:
It is the same as Figure 1.

FIG. 15 shows an example of the structure of the process management table 32 corresponding to each process. As before, the process identifier p
The id 320 is an identification number uniquely assigned to a process within the system. Processor identifier procid 3
2 1 indicates the processor required by the process. When procid = O, request any processor; when procid = n (n is a natural number), request the processor with processor number n;
When rocit=1n, a processor other than processor number n is requested. processor control mode mo
de3 2 2 defines the dynamic change or fixed (or valid) period of the processor identifier, as described above.

When mode=o, the processor identifier is always proc
id" O. That is, pl-ocid = O is set when the process is created. In mode 1, the processor identifier procid is fixed only from the start of execution to the end of the process. That is, An appropriate procid is set at the start of process execution. In mode 2, the procid does not change when the process starts and ends.

That is, once a procid is set, it will not be changed unless an operating processor setting process as shown in FIG. 4 is performed.

This embodiment further introduces the concept of processor affinity Paf (described later), and in the case of mode=3, procid is valid only when the processor affinity Paf is a positive value, and when it is a negative value, i.e. , when the judgment result that the processor cannot be allocated to that processor occurs more than a predetermined number of times in a row due to the processor identifier judgment process, p
Assuming that rocjd=O, change the processor identifier of the process to the processor number. The priority Pr 323 indicates the priority of execution of a process, as described above, and the smaller the value, the higher the priority.

The schedule request counter Src324 indicates the number of times the process has been selected as the next process to be executed when the process is in a waiting state. The schedule request threshold Sth325 indicates the upper limit value of Src. The aforementioned processor affinity Paf is calculated as follows from the schedule request counter Src and the schedule request threshold value sth shown in FIG.

Processor affinity Paf = Sth - Src In this embodiment, Src, 8th is defined as above, but it is also possible to set Src to the execution wait state, set sth to its upper limit, or indicate Src by procid. It is also possible to set sth, the amount of data related to the process remaining in the cache memory of the processed processor, as its lower limit, and furthermore, it is also possible to set Src as the amount of data related to the process remaining in memory, and 8th as its lower limit. It is.

FIG. 16 shows the processing flow of the scheduler in this embodiment.

After the scheduler obtains the processor number P# of the running processor (261.-1), it selects the process with the highest priority from among the processes waiting to be executed (261.-1).
-2). The processor identifier procid and processor control mode mode of the process management table of this selected process are obtained (261-3). Next, the processor identifier procid is checked (26]-4).

This part is similar to the process 311-2 in FIG. At this time, if the processor is not specified and the mo
When de=3 (261-6), after incrementing Src (261-7), processor affinity Paf is checked (261-8). When the processor affinity Paf becomes a negative value, the P# is set as a new procid (261-9), Src is initialized, and the processor is assigned to the process (261-5).

If the value of Paf is not a negative value in step 261-8, the process with the next highest priority is selected (261-8).
1-10) Repeat the same process. When selecting this process, once all waiting processes have been checked, the process with the highest priority is selected again.

Next, the operation of the scheduler when mode=3 will be explained. The operation in mode=o, 1.2 is the same as in the embodiment described above, and will therefore be omitted.

Currently, there is only one process waiting to be executed, and its process management table 32 has the values shown in FIG. 1(a).
Consider a case where the scheduler is running on processor P3. At this time, since the procid determination (261-4) is not established, Src is incremented and N I
II, and calculate the processor affinity Paf (261
-8). In this case, since the value is positive, the process with the next highest priority is selected (261-10). In this example, since there is only one process waiting to be executed, the same process is selected again and the same process is performed. eventually,
At the sixth selection, the processor affinity Paf becomes a negative value,
The processor is assigned with procid "3". The initial value of the processor affinity Paf increases as the schedule request threshold sth increases, and the number of times that allocation to other processors is rejected increases.

In other words, it can be said that the larger the schedule request threshold is set, the greater the affinity between the process and the processor. If the target processor becomes free while repeatedly denying assignment to a processor other than the target processor, the process will be immediately assigned to the target processor by process scheduling on that processor. Become. Note that this control mode can be employed together with the aforementioned control modes, but it is also possible to employ only this control mode independently.

According to the new control mode of this embodiment, by setting its affinity high, a process has a high probability of operating on a processor once allocated. If the processor has a cache memory and stores a lot of data there, this has the effect of suppressing unnecessary process migration and increasing the hit rate of the cache memory. At the same time, under certain conditions, the constraints on the processor are released, making it possible to prevent the operating rate of the processor from inadvertently decreasing.

Next, a fifth embodiment will be described in which the number of processors that can be specified by the processor identifier does not match the number of real processors that can be used in the actual multiprocessor system.

Generally, when specifying a processor from a process (software), it is desirable not to depend on the number of actual processors. Therefore, as shown in FIG. 19, the processor identifier designated by the process is defined as a logical processor identifier 290-1, and the processor identifier corresponding to the processor number is defined as a physical processor identifier 290-2. Then, a correspondence table 290 is provided that associates the two. The correspondence table 290 is created on the shared memory 5 when the multiprocessor system is initialized. Generally, there are more logical processor identifiers than physical processor identifiers, so a plurality of logical processor identifiers are associated with one physical processor identifier.

In the example of FIG. 19, the logical processor identifier is II O
+1 to 119” (“0” is a general-purpose code), whereas the physical processor identifier is set to LL O including the general-purpose code because the number of real processors is 3.
There are only II to n3u. Therefore, logical processor identifiers "4" to "119" are associated with duplicate physical processor identifiers.

FIG. 17 shows a detailed processing flow when this correspondence table 290 is used in the scheduler flow (FIG. 2 or FIG. 16). If the correspondence table 290 has been created (270-1), the processor identifier in the process management table is regarded as a logical processor identifier, and the corresponding physical processor identifier 290-2 is obtained from the correspondence table 290 (270 -2). This will be used as the processor identifier from now on (270-3
, 270-4).

In addition, another detailed flow when this correspondence table 290 is used in the operation processor setting process (Fig. 4) is shown in the first part.
It is shown in Figure 8. If the correspondence table 290 has been created (280-1.), the specified processor identifier is regarded as a logical processor identifier, and the corresponding physical processor identifier 290 is determined from the correspondence table 290.
-2 (PROCID) obtained (28o2). And this is the processor identifier 321 in the process management table.
Set to . In this case, the scheduler side does not need to refer to the correspondence table 290, so the flow shown in FIG. 2 is used as is.

In this way, by dividing the processor identifier into a logical processor identifier seen from the software and a physical processor identifier depending on the hardware, and providing a correspondence table 290 that associates these, it is possible to avoid being constrained by the hardware configuration. , can create software. Therefore, even if the number of processors increases, it is only necessary to increase the physical processor identifier and update the correspondence table, and there is no need to change the existing software.

[Brief explanation of drawings]

FIGS. 1(a) and (b) are system configuration diagrams of an embodiment of a multiprocessor system according to the present invention, FIG. 2 is a processing flow diagram of an embodiment of a process scheduler according to the present invention, and FIG. 3 is a system configuration diagram of an embodiment of a multiprocessor system according to the present invention. FIG. 4 is a flow diagram of a process for setting a part of the operating processor in FIG. 3, FIG. 5 is a flow diagram of a process execution process according to the present invention, and FIG. Flowchart of process termination processing, FIG. 7 is a system configuration diagram of one application example of the embodiment of FIG. 1, FIG. 8 is a system configuration diagram of another application example of the embodiment of FIG. 1, and FIGS. FIG. 10 is an explanatory diagram of a specific system example to which the present invention is applied, FIG. 11 is a system configuration diagram of a second embodiment of the present invention, and FIG. 12 (
a). (b) is a processing flow diagram of the process scheduler in the second embodiment, FIG. 13 is a system configuration diagram of the third embodiment of the present invention, and FIG. 14 is a processing flow diagram of the process scheduler in the third embodiment. , FIG. 15 is a configuration diagram of a process management table in the fourth embodiment of the present invention,
FIG. 16 is a processing flow diagram of the process scheduler in the fourth embodiment, and FIGS. 17 to 19 are explanatory diagrams of the fifth embodiment of the present invention. 1, 2. 3... Process, 4... Connection bus, 5...
・Shared memory, 11... Processor number, 31...
OS program, 32... Processor management table, 3
DESCRIPTION OF SYMBOLS 11... Process scheduler, 321... Processor identifier, 322... Control mode. Applicant: Hitachi, Ltd. Representative: Kazuko Tomita, Patent Attorney Figure 15 Figure 17 Figure 18

Claims (1)

[Claims] 1. A shared memory that stores programs and data and is shared by the plurality of processors, wherein the plurality of processors, programs, and data are operated by a single operating system. In a controlled multiprocessor system, the process scheduler of the operating system allocates one of the processors to a process according to a process management table for managing processes, and the process management table indicates that each process is describes processor allocation information indicating possible processors,
A process scheduling method characterized in that the process scheduler refers to the process management table for the process selected to be executed next and causes the process to operate on the processor specified by the processor allocation information of the process. . 2. A process scheduling method in which a processor is assigned to each process in a multiprocessor system in which a main memory is shared by a plurality of processors, in which processor assignment information specifying a processor on which the process can operate is stored in the storage device for each process. When allocating a process waiting for execution to a processor, the processor allocation information of the process is referred to, and it is determined whether the processor can be allocated to the process according to the processor allocation information. A process scheduling method characterized by: 3. A claim characterized in that, in place of the processor allocation information that specifies a processor on which the process can run for each of the above processes, process allocation information that specifies the processes that the processor can execute for each of the above processes is used. 2. Processor scheduling method according to item 2. 4. A process scheduling method for a multiprocessor operating system in which each process is associated in advance with a processor on which the process can run, and when allocating an empty processor to a process waiting to be executed, the above predetermined method is used. A process scheduling method characterized by determining whether or not to allocate the processor to the process based on a correspondence relationship. 5. The process scheduling method according to claim 1, wherein the processor allocation information includes a general-purpose code indicating that any processor can operate. 6. The process scheduling method according to claim 1, wherein one of the processor allocation information includes a code indicating that a processor other than the specific processor can operate. 7. For a process for which the above general-purpose code is set as the processor allocation information, after the processor that executes the process is determined and before the execution of the process starts, the processor allocation information of the process is specified to specify the processor. 6. The process scheduling method according to claim 5, wherein the process allocation information is changed to the general-purpose code after execution of the process is completed. 8. A claim characterized in that the process management table is provided with an area for storing control modes for each process, and a code specifying the process scheduling method according to claim 7 is defined as one of the control modes. 1. The process scheduling method described in 1. 9. As one of the control modes, a code indicating that the processor allocation information is always fixed is defined, and for a process to which the code is specified, the processor allocation information is not changed before and after the process is executed. 9. The process scheduling method according to claim 8. 10. A process scheduling method in a multiprocessor system having a plurality of numbered processors and a shared memory shared by the plurality of processors, wherein a process management table for managing processes running on the processors is stored in the shared memory. processor allocation information indicating the number of operable processors for each process is stored in the process management table, and the process scheduler refers to the process management table for the process selected to be executed next. A process scheduling method characterized in that the process is operated on a processor corresponding to a number specified by processor allocation information of the process. 11. The process scheduling system according to claim 10, wherein in numbering the processors, the same number can be assigned to a plurality of processors redundantly. 12. A general-purpose code is defined as one of the above processor numbers, and each process is executed on the processor with the number specified in the processor allocation information of the process or on the processor assigned the above-mentioned general-purpose code number. 12. The process scheduling method according to claim 10 or 11. 13. For each process, the degree to which execution on a processor other than the processor specified by the processor allocation information is refused is determined as a numerical value indicating the degree of affinity between the process and the processor, and the execution wait of the process is determined. 11. The process scheduling method according to claim 1, wherein the process is compared with a numerical value related to the state, and the process is operated on a processor other than the designated processor according to the comparison result. 14. The process scheduling method according to claim 13, wherein the numerical value related to the execution waiting state of the process is the number of times allocation to the processor has been rejected or the amount of data waiting for execution of the process. 15. Processor allocation information used when specifying a processor from the above process is a logical processor identifier, and a table is provided in the shared memory that associates the logical processor identifier with a physical processor identifier corresponding to an actual processor. 11. The process scheduling method according to claim 10, wherein the identifier is converted into a physical processor identifier for scheduling. 16. In a process scheduling method in a multiprocessor system having a plurality of processors, for each of the plurality of processors, the priority range of processes executable by that processor is determined in advance, and each processor executes the next process. 1. A process scheduling method characterized in that a process having the highest priority is selected from among waiting processes having priorities within the priority range determined for the processor as the process to be executed. 17. In a process scheduling method for a multiprocessor system having multiple processors, a priority for each of the multiple processors is determined for each process, and each processor selects one of the processes waiting to be executed as the next process to be executed. A process scheduling method characterized in that a process with the highest priority determined for the processor is selected from among the processes. 18. In a multiprocessor system that has at least two processors and can execute a specific process on any of the processors, the processor that executes the specific process is one of the at least two processors. A multiprocessor system characterized in that software for a single processor system can be used without modification by fixing the software to a single processor. 19. In a multiprocessor system having at least two processors and in which a specific process can be executed on any of the processors, the specific process is executed at least from the start to the end of execution of the specific process. A multiprocessor system characterized in that the processor is fixed to any one of the at least two processors, thereby preventing the execution processor from being changed during execution of the specific process. 20. In a multiprocessor system that has at least two processors and can execute various processes on a specific processor, by limiting the number of processes that are run on the specific processor, the response time of the processor can be improved. A multiprocessor system characterized by shortening the value within a certain value. 21. In a multiprocessor system that has at least two processors and can execute various processes on a specific processor, the range of influence of a processor failure can be reduced by limiting the types of processes that are run on the specific processor. A multiprocessor system characterized by localization. 22. A multiprocessor system comprising a plurality of processors and a shared memory that stores programs and data and is shared by the plurality of processors, wherein the plurality of processors, programs and data are controlled by a single operating system. In the above shared memory, a process management table is provided for each process to hold the state of the process, and a storage area is provided in the process management table to store processor allocation information specifying processors on which each process can operate. A multiprocessor system characterized by: 23, comprising at least two processors each capable of executing a specific process, and a shared memory that stores programs and data and is shared by the at least two processors, the processors, programs and data comprising: In a multiprocessor system controlled by a single operating system, the shared memory stores processor allocation information that allows the specific process to be executed only by a specific processor of the at least two processors. A multiprocessor system characterized by providing areas. 24. The multiprocessor system according to claim 22 or 23, further comprising a storage area for storing a control mode for controlling dynamic change of processor allocation information for each process. 25. The above control modes include a first mode in which any processor can operate, and a second control mode in which only a specific processor can operate from the start of process execution to the end of execution. In the second control mode, a general-purpose code that specifies an arbitrary processor is set as processor allocation information, and in the second control mode, the above-mentioned specific code is set as processor allocation information for the process before starting execution on a specific processor. 25. The multiprocessor system according to claim 24, wherein a processor is specified and the processor allocation information is returned to the general-purpose code after execution of a process is completed. 26. The multiprocessor system according to claim 25, wherein the control mode further includes a third control mode in which processor allocation information specifying a specific processor is not changed after a process is generated. 27. The method of using the multiprocessor system according to claim 22, wherein the process group that requires exclusive control over the shared memory is configured to have the same processor allocation information. A method of using a multiprocessor system characterized by operating on a processor. 28. A method of using the multiprocessor system according to claim 22, wherein separate processor allocation information is set for a process group of high importance and a process group of low importance, and both process groups are placed on separate processors. A method of using a multiprocessor system characterized by running the system on a computer. 29. A method for using a multiprocessor system according to claim 25, characterized in that by setting the second control mode, changing the execution processor during execution of one process is prevented. How to use your processor system. 30. The method of using the multiprocessor system according to claim 26, by setting the third control mode for a process group that requires exclusive control over the shared memory,
A method of using a multiprocessor system, characterized in that the above process group is operated on a single processor. 31. A method of using the multiprocessor system according to claim 26, wherein processes are classified into a process group of high importance and a process group of low importance, and the third control mode is applied to both process groups. A method for using a multiprocessor system, comprising: setting different processor allocation information for both processes, and causing both process groups to be executed on separate processors.