JPH02237039A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To contrive the improvement of the easiness for manufacturing a semiconductor device on a large-sized substrate by method wherein a diffusion preventive layer for preventing a first conductor layer from diffusing in an insulator layer or a semiconductor layer is formed using a plating method. CONSTITUTION:A gold layer, which is used as a gate electrode 2 and has a very specific resistance, is formed in a desired form by a printing method. Moreover, a diffusion preventive layer 3 for preventing the gold layer from diffusion in a silicon nitride gate insulator layer 4 can be formed in a form to be required by an electrolytic plating method without using a photolithography and a pattern formation process using a conventional vacuum deposition or a photolithography can be reduced. Thereby, even in case a large-sized substrate 1, for example, a one-meter square substrate is used, the easiness of manufacture of a FET (thin film transistor) array can be improved. Moreover, as the electrode 2 is an electrode of a two layer structure consisting of the gold layer and the layer 3, there is no deterioration of the characteristics of the TFTs due to the diffusion of the gold layer and a signal voltage is never reduced even at the terminal of the substrate 1.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to semiconductor devices, particularly for forming thin film transistors (hereinafter referred to as TFTs) in a matrix to form an image display device in combination with a liquid crystal. This relates to a manufacturing method.

Conventional technology FIG. 3 shows a cross-sectional view of the main part of a conventional TFT array.

A first conductor layer, which is a gate electrode 32 made of aluminum or the like, is formed on a glass substrate 31, a diffusion prevention layer 33 made of chromium is formed on the aluminum, and an amorphous silicon semiconductor layer 35 is made of a silicon nitride gate insulator. 1134
A second conductor layer made of aluminum or the like is formed as source and drain electrodes 36a138b.

TFT arrays are formed on glass substrates of various sizes, and the larger the glass substrate, the larger the base electrode,
There is a problem in that the signal voltage supplied to each gate electrode decreases at its terminal end. To solve this problem, the gate and source electrodes are made of low resistivity conductors (e.g. gold, silver, etc.).
It is formed using materials such as platinum, aluminum, copper, etc.

However, these conductive materials tend to diffuse into the semiconductor layer or insulator layer especially during the process of heating the substrate (for example, the process of depositing the insulator layer or semiconductor layer), resulting in deterioration of TPT characteristics (heat resistance (inferior to). In order to suppress this diffusion, the above-mentioned diffusion prevention layer 33 is formed.

Next, a conventional method for manufacturing a TFT array having the above structure will be briefly described. First, aluminum and chromium are continuously sputter-deposited on the entire surface of the glass substrate 31,
A gate electrode 32 having a desired shape is formed by sequentially removing unnecessary portions of chromium and aluminum by photolithography.
A diffusion prevention layer 33 is formed. This photolithography is performed by exposing a photoresist (photosensitive resin) coated on the material through a photomask (this time it is necessary to match the shape already formed by the previous photolithography), and then developing it. Leave as desired shape,
This is a technique that etches and removes unnecessary parts of each exposed material without leaving any resist.

Next, a silicon nitride gate insulator layer 34 and a non-quality silicon semiconductor layer 35 are sequentially deposited over the entire surface by chemical vapor deposition or the like. Thereafter, the non-quality silicon semiconductor layer 35 deposited on the entire surface is removed using photolithography.
Make it 5. Finally, after aluminum is sputter-deposited over the entire surface, unnecessary portions of the aluminum are removed by photolithography to form source and drain electrodes 38a and 38b of desired shapes, thereby completing a TFT array using conventional technology.

Problems to be Solved by the Invention In the above-described TFT array manufacturing method, a diffusion prevention layer is not formed on the side surface of the gate electrode, which is the first conductive layer.
Although the amount of aluminum gradually diffuses from this side surface compared to the case where there is no diffusion prevention layer at all, the problem is that the TFT characteristics deteriorate.

In addition, photolithography used to form electrodes and the like in desired shapes has a problem in that it requires many steps such as photoresist coating, photomask alignment, exposure, development, etching, and resist removal.

Furthermore, in order to form a desired shape on a large substrate by photolithography using a photomask, it is necessary to perform exposure in several parts, which further increases the number of steps.

The present invention was made in view of the problems of the conventional technology, and it forms the conductor layer of the TFT array by a printing method, and prevents the first conductor layer from diffusing into the semiconductor layer or the insulator layer. In addition, the first conductor layer can be formed without using photolithography, and a large-sized substrate semiconductor device with excellent heat resistance can be manufactured at low cost. The purpose is to provide a method for manufacturing a semiconductor device.

Means for Solving the Problems The technical means of the present invention for solving the above problems are as follows:
After forming a gate electrode, source, or drain electrode, which is a conductor layer, using a low resistivity metal by a printing method, the conductor layer is formed in a gas phase or liquid phase so that the low resistivity metal becomes a nucleus. The first conductor layer is coated with a diffusion prevention layer made of a conductor or an insulator using a plating method such as its own reaction, electrolysis, anodic oxidation, or electrophoresis.

Function As described above, the present invention uses a printing method as a method for forming the first conductor layer, thereby forming only the necessary portions of each electrode as desired without requiring a vacuum evaporation process or photolithography. Furthermore, by using a plating method as a method for forming the diffusion prevention layer, the first conductive layer can be easily formed on the entire surface in contact with the semiconductor layer or the insulating layer. This suppresses the diffusion of the body layer into the semiconductor layer or insulator layer. I can control it.

As described above, according to the present invention, the vacuum deposition process and the photolithography process of the first conductive layer can be omitted, and the first conductive layer can have a low resistance without deterioration of TPT characteristics in a thermal process. Since a body layer can be formed, it is possible to improve the ease of manufacturing a TFT array or the like on a large substrate.

Example An embodiment of the present invention will be described below.

FIGS. 1(a) to 1(d) show process cross-sectional views of a TFT array in a first embodiment of the present invention. As shown in FIG. 1(a), gold (other materials such as silver, platinum, copper, aluminum, etc. can also be used), which will become the gate electrode 2, is deposited on a glass substrate 1 using a printing method in the shape shown in the figure. Next, as shown in Fig. 1(b), electrolytic plating is performed on the gate electrode 2 (the metal formed on the substrate is used as one electrode, and the electrode plate facing it is used as the other electrode, and these are applied to the liquid phase). The diffusion prevention layer 3 made of chromium is formed by applying electrolysis to deposit the metal.
(Cover parts that do not need to be coated with resist etc. before electrolytic plating). Next, Figure 1 (C
), a silicon nitride gate insulator layer 4 is coated on the entire surface by chemical vapor deposition, and a semiconductor layer 5 (for example, polycrystalline silicon semiconductor, non-quality silicon semiconductor, etc.) is coated on the entire surface.
to be continuously young. Then, unnecessary portions of the semiconductor layer 5 are removed using photolithography so that the semiconductor layer 5 has the shape shown in FIG. 1(d). After that, see Figure 1 (
The source and drain electrodes 6a1 are shaped as shown in d).
A metal such as aluminum or aluminum/chromium (February structure in which chromium contacts the bad side of the semiconductor) is formed as 8b, and the TFT array with the inverted staggered structure in this example is completed.

According to this embodiment, gold having an extremely low specific resistance, which will become the gate electrode 2, is formed in a desired shape by a printing method, and furthermore, diffusion prevention is performed to prevent the gold from diffusing into the silicon nitride gate insulator layer 4. The form 3 can be formed in the required shape by electrolytic plating without using photolithography, and the steps of pattern formation by vacuum evaporation and photolithography in the conventional example can be reduced. Therefore, for example, when using a large substrate 1 of 1 m square. Also, since the electrode has a two-layer structure of gold and diffusion prevention layer 3, there is no deterioration of TPT characteristics due to gold diffusion, and the signal voltage can be maintained even at the end of large substrate 1. This has the effect of not causing any deterioration.

FIGS. 2(a) to 2(d) show process cross-sectional views of a TFT array in a second embodiment of the present invention. As shown in FIG. 2(a), source and drain electrodes 28 are placed on the glass substrate 21.
Gold (other materials such as silver, platinum, copper, aluminum, etc. can be used) to form a1 28b is deposited in the shape shown in the figure by a printing method. Next, as shown in FIG. 2(b), diffusion prevention layers 23a1 to 23b made of chromium are deposited on the source and drain electrodes 26a128b by electrolytic plating. Next, as shown in FIG. 2(C), semiconductor Ji! is deposited on the entire surface by chemical vapor deposition. ! 25 (eg, polycrystalline silicon semiconductor, non-quality silicon semiconductor, etc.). After that, see Figure 2 (
Silicon nitride gate insulator layer 2 in the shape shown in d)
4, and then a metal such as aluminum or aluminum/chromium (a two-layer structure in which chromium is in contact with the insulating layer side), which will become the gate electrode 22, is formed to form the staggered TFT array in this example. Complete.

This embodiment also has the same effects as the first embodiment.

The present invention can be configured in various ways other than those shown in the above embodiments.

For example, in the above embodiment, a metal was used as the diffusion prevention layer, and an electrolytic plating method was used to form the layer, but depending on the metal that becomes the first conductor, an electroless plating method (a plating method that does not require electrolysis) The diffusion prevention report can be selectively formed by a method using electrophoresis, an insulator formation method by anodic oxidation, or the like.

Furthermore, if a low resistivity metal is used as the first conductor,
The signal voltage does not drop at the end of the electrode, and the first
Since the diffusion prevention layer is formed on the entire surface of the conductor layer, there is no deterioration of TPT characteristics due to diffusion of low resistivity metal into the insulator layer or semiconductor layer.

In addition, although the above embodiments mainly explained the method for manufacturing a TFT array, the present invention requires the formation of a diffusion prevention layer to suppress the diffusion of metal serving as an electrode into an insulating layer or a semiconductor layer. Needless to say, the present invention is also effective for manufacturing methods of semiconductor devices.

Effects of the Invention As described above, the present invention provides a diffusion prevention layer that prevents the first conductive layer from diffusing into the insulating layer or the semiconductor layer by using a plating method. The first conductor layer can be easily formed on the entire surface in contact with the insulator layer or the semiconductor layer, and furthermore, by depositing the first conductor layer by a printing method, it can be easily formed in the manufacturing process of semiconductor devices such as TFT arrays. The conventional photolithography process using a photomask and the metal vacuum evaporation process can be eliminated.

Therefore, the above-mentioned effects can improve the ease of manufacturing semiconductor devices on large substrates. It also has the effect of reducing Also,
Since the photolithography process and the vacuum evaporation process of the conductive material can be reduced, it also has the effect of reducing the manufacturing cost of semiconductor devices.

[Brief explanation of drawings]

TF in the second embodiment of the invention. FIG. 3 is a cross-sectional view of the main part of a conventional TFT array. ■, 2 1. ．． ．． glass substrate, 2. ．． ．． gate electrode,
3, 23a1 23b. 、． Diffusion prevention layer, 4. 、． gate insulator layer, 25. ．． ．． Semiconductor layer, 26a1 2E! b
．． ．． ．． Source and drain electrodes. Name of agent: Patent attorney Shigetaka Kurino

Claims (4)

[Claims] (1) A step of selectively depositing a first conductive layer on the substrate, a step of selectively forming and covering a diffusion prevention layer using the first conductive layer as a core, and A method for manufacturing a semiconductor device, comprising the step of depositing at least one of a semiconductor layer and an insulating layer so as to overlap a portion of a conductive layer. (2) Claim 1, wherein the step of selectively coating the diffusion prevention layer is a step of coating using a plating method.
A method of manufacturing the semiconductor device described above. (3) The method for manufacturing a semiconductor device according to claim 1, wherein the first conductive layer is selectively deposited by a printing method. (4) A step of depositing both an insulating layer and a semiconductor layer on a substrate, and selectively depositing a second conductive layer so as to overlap a part of the semiconductor layer. 2. The method of manufacturing a semiconductor device according to claim 1.