JPH02235441A - Binary data decoding circuit - Google Patents

Abstract

PURPOSE:To eliminate the need for the use of a ROM and to attain large scale circuit integration by using 2 programmable logic arrays and decoding a binary data string. CONSTITUTION:When a modulation clock CL is given to a shift register 5 and a modulation code CD is given from an input terminal 1, the register 5 inputs 5-bit data x0-x4 to a programmable array 6. The array 6 converts the data into 3-bit data M0-M2 by using a prescribed algorithm. The data M0-M2 are latched by a latch circuit 13 by using a 1/5 frequency division clock SS. Then each latch output of the circuits 13, 7-12 is inputted to a programmable logic array 15. The array 15 uses a prescribed algorithm to convert the data into a 3-bit data AC. The data is outputted from a shift register 17 to an FF circuit 18 in the order of Z1 and Z2, the circuit 18 outputs an output at every 1/2 frequency division clock DCL and a decoded data DDT is obtained at an output terminal 4.

Description

[Detailed description of the invention] ? INDUSTRIAL APPLICATION FIELD] The present invention is directed to a binary data decoding circuit which decodes encoded binary data reproduced from a recording medium into an original binary data string.

[Prior Art] When recording binary data on a recording medium such as an optical disk, various decoding methods have been proposed to improve the recording density. Further, in recent optical disk devices, a sample servo type tracking servo has begun to be put into practical use, which is not affected by the tilt of the optical disk and can simplify the optical head and the like.

Figure 3(a). ．． (b), (C)'. (d). (
e) is a timing chart of the format of the optical disc and the signals of each part according to the sample servo system. Third
As shown in Figure (a), there are two wople bits Pi. Servo signal extraction area (hereinafter referred to as servo by 1 area) S in which WP2 and one reference bit PS are pre-bited.
1 {8 or more are provided at equal intervals for one rotation, and the distance between each servo bite area SnA is as shown in Fig. 4 (
As shown in e), the data area is OA. When recording and reproducing data, the reproduction signal of the servo byte area SRA is obtained as shown in Fig. 3 (bi), and the repopulation signal level S1 of the wobble bit furrow 1 and WP2 is set to Wl.
, By sampling and comparing SP 2,
Controls the tracking servo mechanism. As a result, the standard pit S following the wobble pit PL and WP2
By detecting P, a base t% signal SA indicating the servo byte area SRA is created as shown in FIG. 3(C). This basic signal SA is yen. I. (Ph8seLock Loo
p) Multiply by a circuit to create the channel clock CI shown in FIG. 3(d).

By the way, in order to increase the recording capacity of optical discs and increase the transfer rate, it is necessary to improve the linear density, and the following encoding method is suitable for high-density recording. Requires consideration.

First, considering reproduction waveform interference, if the minimum recording bit interval is smaller than the optical beam diameter during recording and reproduction, adjacent pits will also be reproduced, the jitter of the detection signal will increase due to waveform interference, and the error rate will decrease.

Next, considering the increase in noise jitter due to a decrease in the S/N ratio, the S/N ratio of the reproduced signal increases due to the Takagi decrease phenomenon (resolution decrease), which is mainly caused by the optical beam spot diameter. The noise level decreases, the S/N ratio worsens, and the detection signal jitter due to noise increases, resulting in a decrease in error rate. Therefore, an encoding method with a larger minimum focus interval is desirable.

On the other hand, when considering the encoding method, the following theoretical considerations are generally made when m-bit data is converted into a 1-bit code2 and the minimum pit interval is set as Tmin. First, let d be the minimum value of the number of bits NJ and ``IJ'' of the conversion code string, k be the maximum value, and Tw be the discrimination window width, which is the allowable width of time for accurately detecting a pit. Then, the following equation holds true.

Discrimination window width Tw -X T...(
1) n Minimum pit interval TIIIin = (k+ 1
) x'rn...(2) m Maximum bit interval 1iiTmax = (k +1
) x'rn...(3) However, T is the bit length of the input data, and in the MFM encoding method or 2-7 encoding method, which has been used in the past, the minimum pi7} interval T min is 1.0T or 1.5T, respectively, and the discrimination window width Tw is 0T or 1.5T, respectively.
．． It is 5T.

By improving this encoding method, the minimum bit interval Tm
in=2. An example of the encoding algorithm with OT and discrimination window width Tw = 0.4T is shown in Special Training No. 63-6129 filed by the applicant of the present invention, and FIG. 4 is a code conversion table thereof.

Input data (data to be converted) is separated into 2, 4, and 6.8 bit lengths. A (1.
0), B (1.1), C (0.1), D (0.
0), and those with a length of 4, 6, and 8 bits are represented by a combination thereof.

On the other hand, the conversion code has a 5-bit structure, oooooo,
10000, 01000, 00100. 0001
0. ' 00 (1 (6 types of 11 are used, and each is represented in the table as 0, ], 2, 4, 8, IEi.

If the input data is CR^(01 11 1(+), 8 16 0(00010
00001 00000). Note that since the data of the servo coniliar is all 0, the conversion code is also O. This kind of encoding method, that is, 2×N (
1≦N≦4 integer)? The method of separating data into variable length data as U-position and converting it into a 5×N bit code has the following characteristics.

(1) Minimum pit interval T min = 2.
Achieve 0'F.

(2) In the case of N=1 conversion, the converted 5-bit code has, for example, one of the first three bits rlJ or . All 5 bits are rQJ codes.

(3) In the case of N≧2, the last 5-bit code of the 5-bit code x N pattern to be converted is all “0”, and the previous 5-bit 1 code is, for example, 1 bit of the latter 2 bits. is "l". In addition, for the input binary data string, the servo byte area of the optical disk device is converted by assuming a specific code that is always converted into an "O" pattern, so that the conversion is performed within this data area. The end is complete.

By adopting this encoding method, the recording density is greatly improved.

FIG. 5 is a block diagram showing an example of the code decoding circuit described above, and FIGS. 6(a), (b), . . . , (f) are timing charts of signals of each part thereof. The conversion code CD shown in FIG. 6(a) and the modulation clock CI. shown in FIG. 6(b). is input from input terminals 1 and 3 to the serial input/parallel output shift register 19, and the conversion code CI) is XO
+χzu...κz1 parallel data is 7.

As shown in Figure 4, the number of code data required for conversion is
It is 5×N bits, and when N=1 to 4, it becomes 5 bits to 20 bits. The number of digits of the shift register l9 is determined taking this into consideration. The 175 frequency divider 2l is the modulation clock C1. is divided by 5, and its clear terminal CLR
A reset signal RS is input from the reset signal input terminal 2 to the reset signal input terminal 2 . Figure 6 (C) output from the l/5 frequency divider 21
Parallel data x2 by the subcode synchronization signal SS shown in
. , X21 are latched by a latch circuit 20, and the latch circuit 20 outputs a converted signal y2. The timing signal SD shown in FIG. 6(d), which sets the timing of conversion completion when both Vt
Output from 4. With this timing signal SD, the latch circuit 22 outputs the output X of the shift register 19. −Xl'l is latched, and the conversion code at that time is X o ” X I 9
= V n - V + q is transformed by the ROM 23 having the conversion table shown in FIG. 4 to obtain the converted original binary data Z, to Z0. In other words, for every 5 bits of conversion code CI1, X Z*+ X! + is input to the latch circuit 20, and if it is "0 01" (the last two bits of the conversion code are always "O O"), the data on the input J side (κ.(q) The binary data Z, -Zo are converted as variable length data and are loaded into the shift register 25 at the falling edge of the timing signal SD.

The binary data loaded into the shift register 25 is input to the modulation clock C while the timing signal SD is falling.
The decoded clock signal 11C+, not shown in FIG. 6(e), of the divider-by-2 frequency divider 27 that divides the frequency of L by two is outputted every time it is applied to the shift register 25 as a shift clock, and is inputted to the flip-flop circuit 26. do. Every time the decoded clock signal DCL is input, the flip-flop circuit 26 outputs the stored binary data in units of l bit 1, and the decoded data I) I) T shown in Fig. 6) is output. This will be obtained at the output terminal 4.

[Problem to be solved by the invention] By the way, in the above-mentioned encoding method, the maximum constraint data length during encoding is 8 bits, and the maximum constraint data length during decoding is 20 bits.
Become a bit. Therefore, during encoding, the number of bits handled in conversion is relatively small, 8 bits, and the amount of hardware can be reduced. However, during decoding, the number of bits handled in conversion is 20.
As the number of bits increases, the decoding circuit becomes significantly larger. Therefore, in the decoding circuit described above, it is necessary to use a ROM with 20 bits of input and 8 bits of output, and a large number of ROMs are required.
must be used, making the hardware extremely thick. Apart from this, there is a problem in that it is impossible to manufacture the R (IM), which is one of the best R (IM) with 20 bits of human power and 8 bits of output, and therefore it is impossible to convert the decoding circuit into 1 and S1.

An object of the present invention is to provide a 2 i1j data decoding circuit that can perform 1,Si conversion with a simple circuit configuration.

[Failure to solve the problem]

The binary data decoding circuit according to the present invention separates a 5×N bit code string into 5 bit codes, uniquely converts them into 3 bit codes, and converts the converted 3 bit codes into the 5 bit code circuit. (c) 1α-order delay, the number of conversions is determined by the logic of the delayed signal of a specific 1 bit of the 3-bit code, and the original binary data is decoded by the logic of the remaining 2-bit code according to this number of conversions. Configure.

[Effect]

The conversion code is converted into a 5-bit code. The converted 5-bit code is converted into a 3-bit code. A delay signal related to a 3-bit code is obtained in a period of a 5-bit code, and the number of conversions N is determined based on the logic of a specific 1-bit delay signal of the 3-bit code. The original binary data is decoded using the logic of the remaining 2-bit code in relation to the obtained conversion number N. This allows decoding without using a ROM.

〔Example] The present invention will be described in detail below with reference to drawings showing embodiments thereof.

FIG. 1 is a circuit diagram of a binary data decoding circuit according to the present invention.

The conversion code CD inputted to the input terminal 1 is a serial input/parallel output and inputted to a 5-digit shift register 5. The reset signal input to input terminal 2 is applied to 1/5 frequency divider I.
4 reset terminal CI. Manpower is provided by R.

The variable 714 clock CL input to the input terminal 3 is manually inputted to the shift register 5 as a shift clock,
It is also input to the η frequency divider l6, and is further input to the inverter INV,
The signal is manually inputted to the 1/5 frequency divider 14 via the 1/5 frequency divider 14. The 5-bit data x0 to x4 output by the shift register 5 is the first
is input to the programmable logic array 6 of. The programmable logic array 6 outputs the calculation results described later, and the 3-bit data M0, M+ . M
z uses the divided clock output from the l/5 frequency divider 14 as a latch pulse to the latch circuits 13.7 and 8.9.
In the beginning, 2 bits of data M+, M
2 further includes a latch circuit 10. 11. 12 navel) 11
It is done manually in alpha order. Latch data M. of latch circuit l3.
(0), M2(0), latch data M of latch circuit 7, (1) . Mz (1), latch data of latch circuit 8 M + (2), M 2 (2), latch data of latch circuit 9 Me (3), Ml (3), M2 (3), latch data of latch circuit 10 M. (4), M2(4)
, latch data M. of the latch circuit 1l. (5), Mz(
5) and latch data M of the latch circuit 12, (6),
M2 (6) is the second programmable logic array l5
is input to. The frequency-divided clock outputted from the 1/5 frequency divider l4 is passed through the inverter TNV to the η frequency divider l6.
clear terminal CI. +? is input to. The programmable logic array l5 outputs the calculation results described later,
The back data of the 3-bit data A, B, and C to be output (Y is the output terminal of the first OR circuit @01?, data B is the output terminal of the OR circuit OR, and the second OR circuit OR2).
The data A is input to the single power terminal of the OR circuit.
2 is input to the other input terminal. OR circuit OR. , OR
The 2-bit data Z.t outputs. ,Z. is data Z
2 is inputted to the data input terminal of a two-digit shift register 17 which is a parallel manual/serial output so that it is outputted first. The load terminal 5 of this shift register 17 has
The 5-frequency divided clock outputted by the inverter INV2 is
The shift clock terminal SCI and the flip-flop circuit 18 are supplied with a 2-frequency clock output from the 2-frequency divider 16. Shift 1 register I7 outputs data Z2 first, inputs the data to flip-flop circuit l8, and decoded data D output from flip-flop circuit l8.
DT is output to output terminal 4.

The algorithm of the first programmable logic array 6 is shown in Table 1.
The algorithm is shown in Table 2. Table 1 Moxxa+xx Ml ”X3 +xt+xO M8 笥Xl”X11 Table 2 A=M7 revision X Mt(4) X Mt(5) X Mt
(6) X M+(4)
(4) Xπ buy■10M”;”ffix Mz(4)
X■7 edition + V7■x VH■xpa purchase 3) X M.
(3) B = M7■X Mt(2) X Mt(3)
X Mt(4) 1π■revisedXMffi(4)XMt(5)
XMZ (6) XMI (4) XMI (5) XM currency drunkenness + yz
(Protection-x Mz(3) x Mz(4) x Mz(5
)+Qx Ml(4) X Mz(5) X Mz(6
) X Ml(4) X Ml(5)+8XMt(3)
xi; TjTXMl (3) 10 VH revision × πH■x Ml (
3) X M (1 (3) c = VH revision x Mt (1)
x Mz (4) x Mi (5) 1πH correction X Mt (4
) X M*(5) X Mg(6) X M. (4)
XM. (5) X Ml(6)+V■■x Mz(
2) X Mz(3) X M! (4) 1πH revision XMt
(3)XM! (4) XM. (3) 10TX”; TT'i
x Xlr';”?TT X M t (3) X M
(3) Next, the operation of the binary data decoding circuit configured as described above will be explained with reference to FIGS.

A modulation clock CI. shown in FIG. 2(b) is connected to the clock terminal of the shift register 5. is given and its shift register 5
When the conversion code CI1 shown in FIG. 2(a) is applied from the input terminal l to the data input terminal of the shift register 5, the shift register 5 reads the conversion code C 1111i times for each modulation clock CL, and generates 5-bit data X. -x4 is input to the first programmable logic array 6. As a result, the programmable logic array 6 receives the input data x0~
3-bit data M is generated using the algorithm shown in Table 1 for X4. , M + , M z ゛. Converted data Mo, M+. Mt is latched by the latch circuit l3 by the 5-frequency divided clock SS, which is the subcode synchronization signal shown in FIG. The latch circuit 7 latches. Thereafter, in the same manner, the data latched by the latch circuit 13 is transmitted to the downstream latch circuits 8, 9, 10, 11 . 12 are latched sequentially. and latch circuit 13. 7. 8, 9,
10. 11. Each latch data M latched by 12
, (0), M! (0), M. (1), M2(1),
M + (2). M. (2), Me(3), M+
(3), Mz(3), Ml(4). Mz (4), M.
(5), M2 (5), M+ (6), and Mz (6) are manually input to the programmable logic array l5. The programmable logic array 15 converts the data into 3-bit data A, 8, and C using the algorithm shown in Table 2 above.

The algorithm of the programmable logic array 15 shown in Table 2 is as follows.

As mentioned above, the last two bits of the code to be decoded are ro
, oJ. Therefore, M. =x. The data portion of the latch circuit where +X,=0 is the last portion of the code to be decoded, and N can be determined from this.

In other words, the number of data on the latch circuit 12 side including the latch circuit is N. Then, these 5×N bits or N latch circuits 12. 11... When the decoding code is A=(1.0), the output A is "I".
When IT is set and B = (1.1), ゛l゛゜ is set at its output B, and when D = (0, O), its outputs A, B, and C all output 0. It is configured to do so. Therefore, the parallel input of the shift register (Z2.Z,)
= (1.0), (1,1), (0.1), (0.0)
correspond to decoding codes A, B, C, and D, respectively, and these correspond to 7, . ,Z. will be output in this order. That is, ZI
．． Z2 is loaded into the shift register I7 at the rising edge of the 5-minute m clock SS shown in FIG. 2(C) output by the 1/5 frequency divider l4, and is loaded into the shift register I7 as shown in FIG. 2(e) output by the 2 frequency divider 16. The divided-by-2 clock Oct. is applied to the shift register l7, the flip-flop circuit l is input in the order of Zz, Z,
8, and the flip-flop circuit 18 similarly divides the input data by two in that order and outputs it to the output terminal 4 every 1 DCL. As a result, the output terminal 4 has a second
The decoded data DDT shown in the figure (') is obtained.

As described above, the binary data decoding circuit of the present invention uses the programmable logic arrays 6 and 15 for decoding, so it can be easily integrated into an IC.

Note that the programmable logic array 6, I5 includes, for example, Texas Instruments product number +)AL.
16L8 can be used.

〔Effect of the invention〕

As detailed above, according to the present invention, there is no need to use a large number of ROMs in the circuit for reproducing and decoding data recorded at high recording density on recording media such as optical disks, disks, etc.
It can be configured using a small number of gate ICs. Therefore, the decoding circuit is easily configured, and since it does not use one river, the LS
This makes it possible to implement a large-capacity optical disk device and reduce its cost.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a binary data decoding circuit according to the present invention, FIG. 2 is a timing diagram of each part of the signal, and FIG. 5 is a block diagram of a conventional binary data decoding circuit, and FIG. 6 is a diagram of each part of the signal. This is a timing chart. 1.3...Input terminal 4...Output terminal 5...Shift register 6...Programmable logic array 7.8~l3・
...Lasochi circuit 14...1/5 frequency divider 15...Programmable logic array 16...η frequency divider 17
. . . Shift register 18 . . . Flip-flop circuit In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] (1) Separate the binary data string into variable-length data in units of 2 × N bits (an integer of 1≦N≦4), and make sure that each separated data has a number of insignificant bits between significant bits of 4 or more bits. A binary data decoding circuit that decodes a binary data string converted into a 5×N-bit code string includes means for separating the code string into 5-bit codes, and a means for separating the 5-bit code into 3 bits according to a predetermined algorithm.
The value of the number of conversions N is determined by means for uniquely converting into a bit code, means for sequentially delaying the converted 3-bit code by the period of the 5-bit code, and a specific 1-bit logic of the 3-bit code. and means for decoding the original binary data using the logic of the remaining 2-bit code in accordance with the conversion number N.