JPH0223458A - Access control system for address converting table - Google Patents

Abstract

PURPOSE:To share an address converting table by making inseparable a series of processings of reading, altering and writing for the address converting table, and prohibiting access by means of the other memory control unit during the said processings. CONSTITUTION:A lock instructing means 113 makes inseparable a series of the reading, altering and writing for an access converting table 21, and locking is instructed to a dynamic address converting mechanism 112 during the said processings. The dynamic address converting mechanism 112 combines the lock instruction from the lock instructing means 113 and the lock instruction by means of the other factors, lock-instructs a lock control mechanism 114, and the lock control mechanism 114 sends a lock signal by a lock signal line 40 according to the lock instructions, and access prohibition to a data bus 32 and a physical address bus 31 is notified. Thus, the other memory control unit 11 is prevented from reading the same address converting table 21 entry during a period from address converting table 21 entry reading to the writing by means of a single memory control unit 11.

Description

[Detailed Description of the Invention] [Summary] Regarding access control to an address translation table showing the correspondence between logical addresses and physical addresses in a data processing device, it is possible to share an address translation table among a plurality of central processing units. For the purpose of In a system that is shared by two systems, the memory management unit includes a translation index buffer consisting of a small capacity high-speed memory that performs address translation at high speed, and a translation index buffer that operates when a requested logical address is not in the translation index buffer. A dynamic address translation mechanism that performs registration, a lock instruction means that instructs to lock the common bus during a series of processes of reading, changing, and writing to the address translation table as inseparable processes, and locking the common bus according to the lock status. Equipped with a lock control mechanism that sends out a lock signal to notify access prohibition, the series of processes of reading, changing, and writing from one memory management unit to the 7-dress conversion table are treated as inseparable processes, and during this period, other memory management units are not allowed to access the table. Configure to prohibit access.

[Industrial application field]

The present invention relates to address translation in a data processing system using virtual memory, and more particularly to an access control method that allows multiple central processing units to share an address translation table.

[Conventional technology]

Many data processing devices that use virtual memory are equipped with a memory management unit to manage conversion between logical addresses and physical addresses. The memory management unit has
High-speed conversion buffer (usually,
TLB: TableLookaside Bu
Dynamic address translation mechanism (usually D : Dynami
c Address Translation).

As shown in Figure 4, when dynamically converting a logical address to a physical address, the memory management unit of a data processing device uses pages, which are the smallest unit of address change, to manage virtual memory. It must remember whether the page has been visited and whether the contents of the page have been modified. Hereinafter, the information indicating that the access has been made will be referred to as the R bit, and the information indicating that the access has been made will be referred to as the M bit.

The R bit is used to determine whether a page has been recently referenced when determining which page should be evicted to put a new page in the TLB, and the M bit is used to determine whether a page evicted from main memory needs to be written to secondary memory. use.

Large computers often have R bits and M bits attached to pages of physical memory, and management of R bits and M bits has been performed by dedicated hardware attached to the memory. In such a case, the problems described below can be easily solved by processing the dedicated hardware.

However, in a memory management unit related to a microprocessor, as shown in FIG. 5, it is common to store the R bit and M bit in an address translation table entry. In addition to the physical page number, R bit, and M bit, a table entry has a V bit indicating the validity of the entry and access protection information.
After once reading the address translation table entry containing the bit, if it is necessary to change the R bit or the M bit, writing to the address translation table entry is performed.

[Problem to be solved by the invention]

As shown in Figure 6, when multiple central processing units each having an address conversion unit as described above are connected and share an address conversion table, the M bit is guaranteed in the following operations. become unable.

■A certain address translation table entry (hereinafter referred to as AT
Suppose that both the R bit and the M bit of the data source (abbreviated as E) are “0”.

(2) The central processing unit 1 attempted to write data in the page specified by the ATE, so it read the ATE from the memory.

Value of ATH in memory: R=O, M=0 ■ The central processing unit 2 attempted to read data in a page defined by the same ATE, so it read the ATE from the memory.

Value of ATE in memory: R=O, M=0 ■ Since central processing unit 1 performs write access, R=l, M
= 1 and rewritten ATE.

Value of ATE in memory: R=1. M=1 ■Since the central processing unit 2 performs read access, R=1 was set (M is O as when read in ■), and ATE was rewritten.

Value of ATE in memory: R-1, M=0 At this point, central processing unit 1 enters the page defined by the ATE.
What I wrote is forgotten. If the M bit in the address translation table entry is O when it should be 1, changes in that page will not be reflected in secondary storage, and the page will be paged into physical page memory again. Sometimes it malfunctions.

Therefore, in the conventional method, there was a problem in that the address translation table could not be shared by a plurality of central processing units at the same time.

The problem to be solved by the present invention is to provide an address translation table access method that eliminates such conventional problems.

[Means to solve the problem]

FIG. 1 is a block diagram showing the principle of means for solving the above-mentioned problems.

In the figure, 1 is a central processing unit and 2 is a memory.

11 is a memory management unit that converts logical addresses into physical addresses during execution of instructions.

21 is an address conversion table, which stores physical addresses corresponding to logical addresses.

Reference numeral 111 denotes a translation lookaside buffer (TLB), which is a small-capacity high-speed memory that performs address translation at high speed.

A dynamic address translation mechanism 112 operates when the requested logical address is not in the translation lookup buffer 111 and replaces the contents of the TLB.

Reference numeral 113 denotes a lock instruction means, which treats a series of processes of reading, changing, and writing to the address conversion table 21 as inseparable processes, and instructs to lock the common bus during this process.

A lock control mechanism 114 sends out a lock signal to notify that access to the common bus is prohibited in response to a lock instruction.

A common bus 30 includes a physical address bus 31, a data bus 32, and a lock signal vA40 that notifies access to the physical address bus 31.

[For production]

The problem with the conventional method is that while an address translation table entry is read, modified, and written, another central processing unit reads the same entry.

Therefore, in the present invention, the operation of reading, modifying, and writing an address translation table entry (usually called read-modify-write) is an inseparable operation, and during this time, another central processing unit can read the entry. It was designed to prohibit doing so.

Therefore, the lock instruction means 113 performs a series of processes of reading, changing, and writing to the access translation table 21 (reading the content of an entry, changing the content, and writing it to the entry) as an inseparable process, and during this process, the dynamic address translation 112 to lock. The dynamic address conversion mechanism 112 indicates the lock↑ to the lock control mechanism 114 together with the lock instruction from the lock instruction means 113 and the lock instruction due to other factors, and the lock control mechanism 114 performs the lock in response to these lock instructions. Send a signal.

Address conversion table 21 by lock instruction means 113
When the central processing unit is operating independently, there is no need for a bus lock when issuing an atomic lock instruction for read, change, or write processing to a device (because the bus use by the device holding the bus lock will be delayed). It is also possible to make the lock indivisible only when information instructing the lock instructing means to make it indivisible is set by software.

This prevents other memory management units from reading the same ATE between ATE read and write by one memory management mechanism as described above.

〔Example〕

The present invention will be explained in more detail below with reference to embodiments shown in FIGS. 2 and 3.

FIG. 2 is a diagram showing the configuration of a lock instruction means and a lock control mechanism in an embodiment of the present invention.

In the figure, circuit elements 1131-1136 constitute lock instruction means, and circuit elements 1141-1149 constitute a lock control mechanism.

Inverters 1131 and 1132 constitute a switch, and inverters 1133 and 1134 constitute a launch. Inverter 1134, labeled R, provides weak feedback to inverter 1133, forming a latch but dominated by the input. One bit of the control data bus (a bit that instructs indivisibility of access to the address conversion table) is input to the inverter 1132, and an input instruction determined by a specific instruction or a specific operand is input to the inverter 1131, and the input instruction is " 1”, the switch is opened and the value of 1 bit (negative logic) of the control data bus is latched. This launch state is input to the AND circuit 1141 and also to the AND circuit 1135, and if there is an output instruction, the value is fed back to 1 bit of the control data bus via the driver 1136 and can be read. .

The processing device of this embodiment is equipped with an ink-locked instruction, for example, B S ET I (set a b
CS I (compare and
tore (interlocked) is an instruction that locks the bus, compares the destination operand and comparison operand, determines the result, and updates the contents.

The bus lock access signal on the lower side of FIG. 2 is a signal indicating that it is an operand access that locks these ink-locked instructions based on the result of instruction decoding. Address translation table access signals are directed from the dynamic address translation mechanism.

The address translation table access signal and the values of the latches (1133, 1134) are input to the AND circuit 1141, and when the value of the latch is "0" and the address translation table access signal is "1", the output becomes "L". .

The output of the AND circuit 1141 and the bus lock access signal are input to the NOR circuit 1142, and the output is "0" when the bus lock access is performed or when the address conversion table access is performed and the launch is latched at "O".
” becomes.

Inverters 1144 and 1145 constitute a switch, and A
The ND circuit 1146 and the inverter 1147 constitute a latch circuit, and the gate is opened by the bus cycle start signal, and the output value of the NOR circuit 1142 is "0°", and the A
When the output of the ND circuit 1143 is "O", it is latched and the output becomes 61", and the inverters 1148, 11
After 49, the *lock signal (* indicates reverse logic) becomes "1"
is latched and locked.

When the bus lock cycle end signal no longer needs to be locked, its output becomes “1” and the latch (
1146, 1147) are removed, the *lock signal becomes O'', and the lock is released.

As a result, when a lock is instructed by an input instruction, if there is an access conversion table access, the bus is locked for that bus cycle. In the case of an instruction with an ink clock, the bus is locked while the bus lock access signal is on.

FIG. 3 is a time chart showing the read/modify/write bus lock operation in this embodiment.

The topmost row shows the bus clock signal, the next row shows the address (A) signal, and the next row shows the read or write (
R/W). The part where nothing is done, ie, the read/modify/write modify part, is shown with address signal lines.

The next stage is the address strobe (AS>, which indicates that the address signal is valid when it is low), and the next stage is the data strobe (DS).
When this is on the lower side (low), the data in the next row (
D) is valid.

The next stage of SDC is synchronous data complete, which indicates that data has been loaded from the memory side onto the data bus when reading, and indicates that writing to memory has been completed when writing, ending the memory cycle. Indicates that it is okay to do so.

The bottom row shows a lock signal (LOG>), which indicates that when a read access is performed, it remains on (low side) until the end of the write.

〔Effect of the invention〕

As described above, according to the present invention, an access translation table including R bits/ ) and M bits can be shared by multiple central processing units, thereby facilitating the construction of a tightly coupled multiprocessor system. It has the effect of changing

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing the principle of the present invention, Fig. 2 is a diagram showing the configuration of a lock instruction and lock control circuit in an embodiment of the invention, and Fig. 3 shows the operation of an embodiment of the invention. Time chart, Figure 4 is a diagram showing a data processing device with a memory management unit, Figure 5 is a diagram showing an example of address translation table entries, and Figure 6 is an example where multiple central processing units share an address translation table. FIG. In the drawing, 1 is a central processing unit, 2 is a memory, 11 is a memory management unit, 21 is an address translation table, 111 is a translation lookaside buffer (TLB), 112 is a dynamic address translation mechanism, 113 is a lock instruction means, and 114 is a lock control mechanism,
1131-1134. 1144.1145.1147
~1149 is an inverter, 1135, 114L 1146 is an AND circuit, 1142
1136 indicates a NOR circuit, and 1136 indicates a driver. FIG. 2 is a diagram showing a data processing device having a memory management unit marked with "S" and "Z". FIG. 3 is a diagram showing an example of an address conversion table entry. FIG.

Claims (2)

[Claims] (1) Memory (2) that stores an address translation table (21) in which each entry has information indicating that there has been a reference to the memory area managed by the entry and that there has been a write.
In a system in which a plurality of central processing units (1), each having a memory management unit (11), share a conversion index, the memory management unit (11) includes a conversion index consisting of a small-capacity high-speed memory that performs address conversion at high speed. buffer (111) and the requested logical address is converted into a translation index buffer (111).
The dynamic address translation mechanism (112), which registers data in the translation index buffer (111), and the series of processes of reading, changing, and writing to the address translation table (21) are treated as inseparable processes, and the common bus is used during this time. A lock control mechanism (114) that sends out a lock signal to notify prohibition of access to the common bus in response to the lock instruction; Address conversion table access control characterized in that a series of processes of reading, changing, and writing to the address conversion table (21) are treated as inseparable processes, and access by other memory management units (11) is prohibited during this process. method. (2) It is configured to include indivisible instruction information that can be set by software in order to indivisibly perform a series of processes of reading, changing, and writing by the lock instruction means (113) and to enable an operation that instructs locking. The access control method for an address translation table according to claim 1.