JPH02234438A - Manufacture of thin-film transistor - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an 8111} transistor and a method for manufacturing the same. [Prior art and its problems] Conventionally, fill! }An inverted stagger type transistor shown in Figure 4 is known as a transistor. This type of thin film transistor is a field effect transistor and is configured as follows. That is, a gate electrode 2 is patterned on a glass substrate l, and a gate insulating film 3 is formed to cover this gate electrode 2.
On this gate insulating film 3, plasma C V D (Ch
t++sical VaporDeposition)
A semiconductor M4 made of a-Si (7 mol 77 silicon) is patterned to correspond to the gate electrode 2 by a method, and a source electrode 5 and a drain electrode 6 are formed to cover the edges of this semiconductor layer 4. A pattern is formed. In this case, the source electrode 5 and the drain electrode 6 are electrically connected to the semiconductor layer 4 by n'-a-Si layers 7, 7 at the edge of the semiconductor layer 4. Ql like this! }In a transistor, when a voltage is applied to the gate electrode 2, a current flows from the source electrode 5 to the drain electrode 6 through the semiconductor layer 4 in response, but since the semiconductor layer 4 is made of a-Si, the electric current The problem is that the mobility is small and the response speed is slow. On the other hand, planar thin film transistors that use polysilicon (polycrystalline silicon) for the semiconductor layer have also been developed to increase response speed. This kind of E! The J membrane transistor is constructed as shown in Figure 5. That is, a semiconductor layer 9 made of polysilicon is formed on a quartz substrate 8 by plasma CVD, and a pair of P-type or N-type inactive regions 1O and 1O doped with impurities are formed in this semiconductor layer 9. is formed. This semiconductor layer 9
The surface of the gate insulator I except for the inactive region 10.10
'll is formed. On this gate insulation Ilgll, a gate electrode l2 is patterned to correspond to the inactive regions 10, 10, and on both sides thereof, a source electrode l3 conductive to each inactive region 10 and IO, respectively.
and a drain electrode l4 are patterned. In such a thin transistor, the gate electrode l
When a voltage is applied to 2, the inactive region lO in the semiconductor layer 9
, 10, a current flows from the source electrode l3 to the drain electrode 14 in response, but since the semiconductor layer 9 is made of polysilicon, it is necessary to perform a hydrogenation treatment to reduce the defect density after generation. Moreover, in order to form the pair of inactive regions 10 and IO in the polysilicon semiconductor layer 9, a technique for doping impurities such as phosphorus ions and poron ions by ion implantation is required, which complicates the manufacturing process. There is a problem that. In addition, since polysilicon is produced using the plasma CVD method, the production temperature is 800 to 700.
As high as ℃. Therefore, it is difficult to form on a glass substrate or the like with a low melting point, and there is also the problem that an expensive quartz substrate 8 with a high melting point must be used. [Objective of the Invention 1 This invention was made in view of the above-mentioned circumstances, and its purpose is to improve the response speed, simplify the manufacturing process, and make it easy to manufacture. The purpose of the present invention is to provide a G-film transistor that can be used as a G-film transistor and a method for manufacturing the same. [Summary of the Invention] In the thin film transistor of the present invention, a gate electrode is patterned on a glass substrate, a gate insulating film made of silicon nitride is formed on the substrate to cover the gate electrode, and a gate insulating film made of silicon nitride is formed on the substrate to cover the gate electrode. A semiconductor layer made of polycrystalline silicon is formed to face the gate electrode, and source and drain electrodes are patterned on the semiconductor layer or the gate insulating film at locations facing the gate electrode. Further, in the method for manufacturing a thin film transistor or transistor according to the present invention, a gate electrode is patterned on a glass substrate, and then a gate insulating film made of silicon nitride is formed on the substrate to cover the gate electrode. A semiconductor layer made of polycrystalline silicon is formed on the gate insulating film, and source and drain electrodes are patterned on the semiconductor layer at locations facing the gate electrode, or source and drain electrodes are formed on the gate insulating film. An electrode is patterned at a location facing the gate electrode, and a semiconductor layer made of polycrystalline silicon is formed on the gate insulating film between the source and drain electrodes, covering at least the upper edges of the source and drain electrodes. It is a method. [First Embodiment J Hereinafter, with reference to FIGS. 1 and 2, the first embodiment of the present invention will be described.
An example will be explained. Figure 1 shows the configuration of an inverted staggered thin film transistor. 20 in the figure is a glass plate. This glass substrate 20
A gate electrode 2l is patterned on the upper surface.
The gate electrode 2l is made of a heat-resistant metal, for example, 40
Titanium (〒1) and chromium (
Cr) etc. Also, on the glass substrate 20 is a gate insulator 1? covering the gate electrode 21? u22 is formed. This gate insulating film 22 is silicon nitride (Si3N4
), and is formed into a film by plasma CVD method, with a film thickness of approximately 3000λ. This gate insulating film 2
A semiconductor layer 23 made of polysilicon is formed on top of the semiconductor layer 2 . This semiconductor layer 23 is formed in an ultra-vacuum state by low-temperature epitaxial evaporation (MBE) at about 400° C., and has a thickness of about 1000 to 3000λ.
On the upper surface of this semiconductor layer 23 is an n''-a-Si layer 24.2.
4 is patterned and this n''-a-Sr layer 24.2
4 have a source electrode 25 and a drain electrode 2, respectively.
6 is patterned. In this case, n'-a-S
The i-layers 24, 24 provide electrical conduction between the semiconductor layer 23, the source electrode 25, and the drain electrode 26, and are formed by plasma CVD. The source electrode 25 and the drain electrode 26 are made of metal having a low electrical resistance value, such as aluminum (AI), chromium (Cr), titanium (Ti), aluminum-titanium alloy (AI-Tr), or the like. Note that this source electrode 25, drain 1! The pole 26 and the semiconductor layer 23 are made of silicon nitride (Si38m) or silicon oxide (S
iO2)? It is covered and protected by an insulation film (not shown). Next, with reference to FIG. 2, the case of manufacturing an inverted stagger type thin film transistor as described above will be described. First, as shown in FIG. 2(A), the L of the glass substrate 20 is
A gate electrode 2l made of titanium (Ti), chromium (Cr), etc. that can withstand heat of about 400°C is patterned on the surface. That is, when forming the gate electrode 2l, a metal layer is first formed on the upper surface of the glass substrate 20 by vapor deposition or sputtering. A photoresist layer is then patterned on the surface of this metal layer by photolithography, and the metal layer is etched using this photoresist layer as a mask to remove unnecessary portions. As a result, a gate electrode 21 made of a metal layer is patterned on the upper surface of the glass substrate 20. In addition, gate ″: rL pole 2
After forming the photoresist layer, the photoresist layer is removed from its top surface. Next, as shown in FIG. 2(B), a gate insulating film 22 made of silicon nitride is formed on the glass substrate 20 by plasma CVD to cover the gate electrode 2l, and has a thickness of 300 mm.
Form around 0λ. In this plasma CvD method, monosilane (SiHa) is used as a reactive gas. Ammonia (NH3
), using a gas such as nitrogen (N2). Therefore, the generated gate insulation [22] contains hydrogen in silicon nitride. Then, as shown in FIG. 2(C), a semiconductor layer 23 made of polysilicon is deposited on the gate insulating film 22 by low-temperature epitaxial deposition (MBE) at 400°C or less.
), and is formed to a film thickness of approximately 1000 to 3000λ. When the semiconductor layer 23 is formed in this way, hydrogen contained in the silicon nitride of the gate insulating film 22 is diffused, so that the semiconductor layer 23 made of polysilicon is
is hydrogenated at the same time as it is produced. After this, as shown in Figure (D):jSz, the semiconductor layer 23
An n'-a-Si layer 24 is formed on the upper surface of the
is formed to a thickness of about 250 to 500λ, and this n'-a
- Form a metal layer 27 on the Si layer 24 by vapor deposition or sputtering. And this metal M27 and n”
- Unnecessary portions of the a-Si layer 24 are sequentially removed by photo-etching. As a result, n is formed on the upper surface of the semiconductor layer 23.
A source electrode 25 and a drain electrode 26 are patterned to face each other at a location corresponding to the gate electrode 2l via the -a-Si layers 24 and 24.Finally, if the photoresist layer is removed, the first The inverted staggered thin film transistor shown in the figure is obtained.The source electrode 25, the drain electrode 26, and the semiconductor layer 23 are
Silicon nitride (Si3Ns) or silicon oxide (
An insulating film (not shown) such as Si02) is formed for protection. Therefore, in such a thin film transistor, when a voltage is applied to the gate electrode 2l, the source electrode 25 is connected to the drain electrode 26 through the semiconductor layer 23 made of polysilicon.
A current flows and responds. In this case, since the semiconductor layer 23 is made of polysilicon, it has good electrical mobility and
Response speed can be increased. Furthermore, since the semiconductor layer 23 is formed by forming the gate insulating IFu21 made of silicon nitride and then generating polysilicon on the gate insulating W221, hydrogen contained in the silicon nitride is diffused during the formation. and hydrogenated. Therefore, it is not necessary to hydrogenate the semiconductor layer 23 in a separate process after the semiconductor layer 23 is formed, and the hydrogenation process can be performed at the same time as the semiconductor layer 23 is formed, and the defect density can be reduced by this hydrogenation process. Moreover, in such a thin film transistor, even if the semiconductor layer 23 is formed using polysilicon, there is no need to dope impurities into the semiconductor layer 9 unlike the conventional planar type, so the manufacturing process is simple and easy. It can be manufactured to In addition, since the semiconductor M23 is produced at a temperature below 400°C by a low-temperature epitaxial deposition method,
There is no need to use an expensive quartz substrate 8 or the like with a high melting point, and an inexpensive glass substrate 20 with a low melting point can be used.
[Second Embodiment 1 Next, a second embodiment of the present invention will be described with reference to FIG. In this case, the same parts as in the first embodiment described above are given the same reference numerals, and their explanations will be omitted. FIG. 3 shows an inverted coplanar thin film transistor, in which a gate electrode 2l is patterned on the upper surface of a glass substrate 20, as in the first embodiment, and a gate electrode 2l is formed on the upper surface of a glass substrate 20. Insulation 822 is formed. In this case, the gate electrode 2l is made of a metal having the same heat resistance as in the first embodiment, and the gate insulator 1122
- is made of silicon nitride (Si3N4), and plasma C
The film is formed using the VD method. On this gate insulator g22, a source electrode 25 and a drain electrode 26 are patterned to face each other at locations corresponding to the gate electrode 2l. On the opposing surfaces of each of the electrodes 25 and 26, an n.1a-Si layer 24 and 24 is formed over the upper portion thereof.
is patterned, and this "n""a2 Si layer 24
, 24 between the gate insulating film 22 between each electrode 25 and 26.
A semiconductor layer 23 made of polysilicon is formed thereon. This semiconductor layer 23 has a thickness of 400 nm as in the first embodiment.
The film is formed in an ultra-vacuum state using the low-temperature epitaxial deposition method at a temperature of about 1000 yen. Note that each electrode 25, 26 is made of the same metal as in the first embodiment, and each electrode 25, 26 and semiconductor layer 23 are also covered and protected with an insulating film (not shown) such as silicon nitride or silicon oxide. Ru. When manufacturing such an inverse coplanar thin film transistor, first, a gate electrode 2 is formed on a glass substrate 20, as in the first embodiment.
At the same time, a gate insulating film 22 made of silicon nitride is formed by plasma CVD to cover the gate electrode 2l. In this case, plasma CVD
The reaction gas used in the method is the same gas as monosilane, ammonia, nitrogen, etc. as in the first embodiment. Therefore, the generated gate insulating film 22 contains hydrogen in silicon nitride. Thereafter, a metal film is formed on the upper surface of the gate insulating film 22 by vapor deposition or sputtering, and unnecessary portions of this metal film are removed by photo-etching, thereby forming the gate insulating film 22. A source electrode 25 and a drain electrode 26 are patterned on L. Thereafter, an n-a-Si layer 24 is formed on the surfaces of the source electrode 25 and drain electrode 26 by plasma CVD, and this n-a-SiM
2 4 by removing unnecessary parts by photo-etching. n'-a-Si layers 24 and 2 are formed on the opposing surfaces of the source electrode 25 and the drain electrode 26 over their upper edges.
Form 4 into a pattern. Thereafter, a semiconductor film made of polysilicon is formed on each electrode 25, 26 and the gate insulation between them [22h] in an ultra-vacuum state by a low-temperature epitaxial single deposition method at 400° C. or less. During this film formation, hydrogen in the silicon nitride of the gate insulating film 22 diffuses and hydrogenates the semiconductor film. Then, by removing unnecessary portions of this semiconductor film by photo-etching, a semiconductor layer 23 made of polysilicon is patterned on the gate insulating film 22 between the source electrode 25 and the drain electrode 26. This semiconductor layer 23 corresponds to the gate electrode 21 and is connected to each electrode 25 via the n''-a-Si layers 24, 24.
, 26 are formed across the opposing parts. Therefore, even in such an inverse coplanar type t[} transistor, the gate insulating mass 22 made of silicon nitride is
Since the semiconductor layer 23 made of polysilicon is formed on top of the gate electrode 2l by a low-temperature epitaxial deposition method at 400° C. or lower in an ultra-vacuum state, the same effect as in the first embodiment can be obtained. be. In each of the above-described embodiments, the semiconductor layer 23 made of polysilicon was produced by a low-temperature epitaxial deposition method, but the semiconductor layer 23 is not limited to this, and may be produced by a plasma CVD method or the like. Furthermore, the gate insulating film 22 does not need to be a single layer of silicon nitride, and may have a two-layer structure in which an insulating layer such as Ta205 is laminated on a silicon nitride layer, or the order of the upper and lower layers may be changed. ．． [Advantageous Effects of the Invention 1] As described in detail above, according to the present invention, since the semiconductor layer is formed of polycrystalline silicon, the electrical mobility is fast and the response speed can be increased. In addition, since the semiconductor layer is formed on the gate insulating film made of silicon nitride, hydrogen in the silicon nitride diffuses during molding, which eliminates the need to hydrogenate the semiconductor layer in a post-process. This can be done simultaneously, thereby reducing the defect density in the semiconductor layer. Moreover, since this semiconductor layer does not need to be doped with impurities, the manufacturing process can be simplified and it can be manufactured easily. Furthermore, if the semiconductor layer is formed by low-temperature epitaxial deposition, there is no need to use an expensive quartz substrate with a high melting point, and an inexpensive glass substrate with a low melting point can be used. Each cross-sectional view showing the manufacturing process of the rfS of this invention, FIG.
Figure 4 is a cross-sectional view showing the configuration of an inverted coplanar thin film transistor in Example 2, Figure 4 is a cross-sectional view showing a 4I configuration of a conventional inverted staggered thin film transistor, and Figure 55 is a cross-sectional view showing the configuration of a conventional planar thin film transistor. This is a diagram.

Claims (3)

[Claims] (1) a glass substrate; a gate electrode patterned on the glass substrate; a gate insulating film made of silicon nitride formed on the glass substrate covering the gate electrode; a semiconductor layer made of polycrystalline silicon formed facing the gate electrode; and a semiconductor layer formed on the semiconductor layer or the gate insulating film and electrically connected to the semiconductor layer at a location facing the gate electrode. A thin film transistor comprising source and drain electrodes. (2) patterning a gate electrode on a glass substrate; forming a gate insulating film made of silicon nitride on the glass substrate to cover the gate electrode; and forming a gate insulating film made of polycrystalline silicon on the gate insulating film. A method for manufacturing a thin film transistor, comprising: forming a semiconductor layer on the semiconductor layer; patterning source and drain electrodes on the semiconductor layer at locations facing the gate electrode. (3) In claim 2, the step of patterning source and drain electrodes on the gate insulating film made of silicon nitride at locations facing the gate electrodes, and the gate insulating film between the source and drain electrodes. A method for manufacturing a thin film transistor, comprising: forming a semiconductor layer made of polycrystalline silicon over at least the upper edges of the source and drain electrodes.