JPH02232900A - Non-volatile semiconductor memory device - Google Patents

Abstract

PURPOSE:To prevent malfunction caused by the deviation of timing by making the starting timing of a bit line earlier than that of a word line at the time of data writing operation in the EEPROM of a NAND cell system. CONSTITUTION:A memory cell M and select gate FETs S1 and S2 are provided in a block, where an Si substrate is insulated and separated, and the control gate of each cell M constitutes each word line WL. Then, adjacent drain and source are shared and M1-M8 are serially connected. In such a way, the NAND cell is constituted and a cell array is connected to bit lines BL1-BL8. When data are erased, at first, an SD1 and made +20V, a control line SS1 is made 0, the BL1 is made 20V and the WL is wholly made 0. Then, the electron of the M1 is discharged and in the following processing, the data are wholly erased in the same way. When the data are written, the writing is started from the M which is distant from the bit line and the WL8 is made 18V. Then, the WL7 is made 0 and the WL1 is made 9V which is an intermediate voltage. After wards, the gate control line SD1 is made 12V, 0 or 9V is applied to the BL in correspondence to the data and the electron is injected. By applying the prescribed deviation to the timing of writing control, erroneous writing or errone ous erasing can be prevented and the reliability is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a nonvolatile semiconductor memory device using an electrically rewritable memory cell having a charge storage layer and a control gate.

(Prior art) In the field of EEPR゜OM? l! Memory cells having a MOSFET structure having a load storage layer and a control gate are widely known. The memory cell array of this EEFROM is constructed by arranging memory cells at each intersection of row lines and column lines that intersect with each other. In the actual pattern, the drains of the two memory cells are made common and the column lines are brought into contact with the drains, thereby minimizing the area occupied by the cells. However, even in this case, a contact portion with the column line is required for each common drain of two memory cells, and this contact portion occupies a large portion of the cell area.

Therefore, as a method that can further reduce the cell occupation area, a method has been proposed in which multiple memory cells are connected in series by sharing their source and drain diffusion layers to form a NAND cell (for example, Japanese Patent Application No. 62-23944 issue). NA
A drain at one end of the ND cell is connected to a bit line via a selection gate, and a control gate of each memory cell is connected to a word line. As a memory cell, FETMOS (Flo
at1ng Gate-Tunneling
In MOS), both data writing and erasing utilize the exchange of charges between the charge storage layer and the substrate.

NAND cell type E using this FETMOS
Specific data writing and erasing methods in EFROM include (a) II; Electron injection from the plate to the charge storage layer (hereinafter referred to as "ill") is used for data erasing, and electron injection from the charge storage layer to the substrate is used. There is a method in which electron emission (hereinafter simply referred to as electron emission) corresponds to data writing, and a method in which (
b) There is a method in which m-ion emission is used for data erasing, and electron injection is used for data writing. In the former method (a), a high potential is applied to all word lines, a low potential is applied to the bit lines, and electrons are injected into all memory cells constituting the NAND cell to perform collective erasing. The erased state is a state in which the threshold value of the memory cell moves in the positive direction due to electron injection. Data writing is performed by setting the word lines to a low potential in order from the one farthest from the bit line, setting the word lines on the bit line side to a high potential, and applying a high potential or an intermediate potential to the bit line depending on the data. Electrons are emitted accordingly. The threshold value of the memory cell moves in the negative direction due to electron emission. On the other hand, in the method (b), data is erased by applying a high potential to the bit line and applying a low potential to one selected word line to emit electrons from the bit line side. At this time, a high potential is applied to the word line located on the bit line side from the selected word line.

In this case, the data erase state is a state in which the threshold value of the memory cell has moved in the negative direction. For 0 data writing: - Apply a low potential to the selected word line, apply a high potential to word lines closer to the bit line, A high potential or an intermediate potential is applied to the bit line depending on the data. When a high potential is applied to the bit line, electrons are emitted from the memory cell, and writing is performed.

In these NAND cell type EEFROMs, conventionally proposed writing methods. In the erasure method, the data applied to the bit line and the word line rise simultaneously. However, the timing at which the voltage rises in each part depends on the capacity of the booster circuit and the resistance of the load. They vary depending on the capacitance, etc., and do not necessarily rise at the same time. If there is a difference in the timing of the potential rise of each part, problems such as erroneous writing and overerasing may occur. For example, consider a data write operation using the method (a) above. A high potential or an intermediate potential is applied to the bit line depending on the data, and electron emission does not occur when the bit line is at an intermediate potential.

At this time, unselected memory cells along the word line on the bit line side from the selected word line are in a half-selected state in electron injection mode with a high potential applied to their control gates. In this case, the timing at which the bit line becomes an intermediate potential is delayed, the word line (that is, the control gate) becomes a high potential, and when the bit line becomes a low potential state, a complete electron injection mode is established. Therefore, such an unselected memory cell is in an overerased state, and even if electrons are emitted during subsequent data writing, a desired threshold value cannot be obtained, which is unfavorable in terms of operating characteristics. Furthermore, in the method (b), if the rise of the bit line potential is delayed, erroneous writing occurs. That is, when writing data, the bit line is given an intermediate potential or a low potential depending on the data, the iQi potential is given to the selected word line, and electron injection occurs when the bit line is at a low potential. If there is a delay in applying an intermediate potential to the bit line to prevent this from occurring, the electron injection mode will be entered, resulting in :A writing.

The above-mentioned erroneous writing and over-erasing also occur when the timing of potential fall of the bit line is earlier than that of the word line.

(Problem to be solved by the invention) As described above, the E
In the EFROM, there is a problem in that during a data write operation, a timing shift causes erroneous writing or over-erasing, which reduces the reliability of the EEFROM.

An object of the present invention is to provide a highly reliable electrically rewritable nonvolatile semiconductor memory device that solves these problems.

[Structure of the Invention] (Means for Solving the Problems) The EEFROM of the present invention has a charge storage layer and a control gate stacked on a semiconductor substrate, and transfers charges between the charge storage layer and the substrate by a tunnel current. A plurality of memory cells that are used for electrical rewriting are connected in series to form a NAND cell and are arranged in a matrix.The drain at one end of each NAND cell is connected to a bit line, and the control gate of each memory cell is connected in series to form a NAND cell. It has a basic configuration connected to a word line.

In such an EEFROM, the present invention is characterized in that the bit line rise timing is earlier than that of the word line during data write operation.

(Function) According to the present invention, during a data write operation, over-erasing in a half-selected memory cell and erroneous writing in a selected memory cell due to a delay in rising of a bit line are prevented. There is a similar problem not only when starting up the bit line but also when turning it down, so in addition to advancing the timing of starting up the bit line,
It is more effective if the timing of the falling of the bit line is delayed.

(Example) Embodiments of the present invention will be described with reference to the drawings.

The following example shows a NA using n-channel FETMOS.
This is an ND cell type EEPROM.

FIG. 1 shows one NAN of a memory cell array of one embodiment.
Plan views showing the D cell part, FIGS. 2(a) and 2(b) are the A-
FIG. 3 is an equivalent circuit of the memory cell array.

First, focusing on one NAND cell, its configuration will be explained. In this embodiment, eight memory cells M1 to M are provided in a region defined by an element isolation insulating film 2 on a p-type silicon substrate 1.
g and two selection gate transistors S.g. , S3 are formed. Each memory cell has a floating gate 4 (4+ to 48) made of a first layer polycrystalline silicon film formed on a substrate 1 via a first gate insulating film 3 made of a thermal oxide film, and a second gate insulating film 4 (4+ to 48) made of a first layer polycrystalline silicon film is formed on a substrate 1. Control gates 6 (6. to 6l,) made of a second layer polycrystalline silicon film are formed through the film 5. The floating gate 4 of each memory cell is a charge storage layer. Control gate 6G of each memory cell. tsotLsot
It constitutes L'7-do mWL (WL1 to WL8).

Eight memory cells are connected in series so that the n+ type layer 9 serving as the source and drain of the memory cell is shared by adjacent cells. In this embodiment, selection gate transistors S. , Sl are connected to form one NAND cell. Selection gate transistor S+. Si gate electrode 49.69 and 4
,. , 61o are obtained by simultaneously patterning the first and second layer polycrystalline silicon films constituting the floating gate and control gate of the memory cell. Contact is made at predetermined intervals in the line direction. The whole is covered with CVD insulation [7], and Aj7 as a bit line BL contacts the n+ type layer which is the drain of the selection transistor S1 for the memory cell.
Wiring 8 is provided. This contact portion is doped with n-type impurities.

Coupling capacitance C between floating gate 4 and substrate 1 in each memory cell
I is set smaller than the coupling capacitance C2 between the floating gate 4 and the control gate 6. To explain the specific dimensions, both the floating gate 4 and the control gate 6 have a channel width of 1 μm, so the channel length of the memory cell is 1 μm, and the floating gate 4 has a field region as shown in FIG. 2(b). It extends 1 μm on both sides of the top.

The first gate insulating film 3 is a thermal oxide film of 110 people, and the second
The gate insulating film 5 is a 350-layer thermal oxide film.

Regarding the selection gate transistors Sr and Ss, the channel length of the transistor SI on the drain side, that is, on the bit line side is set longer than that of the transistor S on the source side. This is to prevent bunch-through of the transistor S1. A source diffusion layer to which a ground potential is applied is commonly formed in the word line direction.

The memory cell array in FIG.
It shows how 16 cells are connected to eight bit lines BL, -BL8. Each word nWL. -WL8,
The control line SD. of the selection gate St, S2 on the drain side. ，
SD2 is led out from the array region via a D-type n-channel selection MOS transistor controlled by the control signal PRO, and is connected to the control line S8 of the selection gates sJ and S4 on the source side.
1882 is directly derived.

The operation of the EEPROM configured in this way will be explained next. FIG. 4 shows memory cells M, -M. NAND consisting of
This is a basic timing diagram of data erasing and writing when focusing on a cell, and FIG. 5 shows the potential relationship of each part during data erasing, writing, and reading. Here, method (b) of the two methods described above is used, that is, electron emission is used in the data erase mode, and electron injection is used in the data write mode. First, data is erased from memory cells M1 to M8 in order from memory cell M.

Control line SD. Apply a positive high potential (-20 V) to
The control line SSL is set to a low potential (-0 V), the bit line is given a positive high potential (-20 V), all word lines are set to a low potential (-0 V), and the memory cell M emits electrons. let Next, the control line SD and the word line WL
A high potential is applied to +, causing the second memory cell M2 to emit electrons. Thereafter, the same operation is repeated to erase the entire area.

The erased state is a state in which the threshold value of the memory cell moves in the negative direction, and this is assumed to be, for example, "1°." Data is written in the memory cell in the order starting from the one farthest from the bit line. The word line on the source side is at a low potential (-0v), the word line on the bit line side is at an intermediate potential (-9V), and the control line SD of the selection gate on the drain side is connected to an intermediate potential (-18V). A potential (-12'l) is applied, and a low potential (Ov) or an intermediate potential (-9 V) is applied to the bit line BL depending on the data. When the bit line is at a low potential, electron injection occurs in the selected memory cell. "0" is written.

When the bit line is at an intermediate potential, the erased state "1" is maintained.

To read data, set one selected word line to a low potential (-0 V)
and unselected word lines are set to intermediate potential (-5 Vl,
This is done by applying a read voltage (-1 V) to the bit line and detecting whether the channel is on or off.

Regarding the above basic timing, the specific timing relationship during the data write operation is shown in FIG.

FIG. 6 shows word lines WL. In this case, one selected word line WL8, drain side selection gate 11
The timing of rising the bit line BL is advanced by a time tdl with respect to the timing of applying a predetermined potential to the underline SD and the unselected word line.

The timing of the fall of the bit line BL is delayed by a time td2. For example, both tdl and td2 are 0.5 mse.
It should be about c. The intermediate potential 9V applied to bit IIBL corresponds to data "1°" here, and is applied when the selected memory cell is in half-selected injection mode and '0' is not written, that is, when the erased state is maintained. but,
If the rise is delayed, the selected memory cell enters the electron injection mode and is erroneously written to "0". In this embodiment, such erroneous writing can be prevented by accelerating the rise of the bit line during this writing operation. The same meaning applies to delaying the fall of the bit line.

FIG. 7 is a specific example of data write timing in another embodiment. The basic operation follows the timing shown in FIG. 4 as in the previous embodiment. In the write operation in this case,
The rise timing of the bit line BL is advanced by the time tdl, which is the same as in FIG. The difference from the case in FIG. 6 is that, in applying a high potential to the selected word line WL, two steps are adopted: first, applying an intermediate potential to the other word lines, and then applying an intermediate potential, and then applying a high potential. That is what we are doing. In this way, a high potential of 18V can be boosted relatively easily. Regarding the timing of falling, first, the control line SD of the drain side selection gate falls, and then the time td
3, the control line S S r of the source side selection gate is once raised to 5V, the word line and the source side selection gate control line are brought down, and after a time td2 has passed, the bit line BL is brought down. The falling edge of this bit line is
Any time is fine as long as it is a certain amount of time after the SD has fallen. If the fall of the word line precedes the fall of the drain side select gate control line, the intermediate potential of the bit line becomes NAN.
If it is confined in the diffusion layer in the D cell, problems such as threshold fluctuation may occur afterwards. If the falling timing is set as above, the drain side selection gate is turned off, and the source side selection gate is turned on while the memory cell in the NAND cell is on, so unnecessary charges in the NAND cell can be swept away. I can put it out. This results in
A more reliable EEFROM can be obtained.

Next, the two posts mentioned above. An example in which another one of the erasing methods, method (a), is used will be described. The configuration of the memory cell array is the same as in the previous embodiment, so the explanation will be omitted. The basic timing of erasing and writing is
As shown in the figure. To erase data, apply a high potential (-20 V) to the control lines SD, SS, and all word lines,
The bit line is set to a low potential (-0 V). As a result, electron injection occurs in all memory cells, and the threshold voltage moves in the positive direction, resulting in an erased state. Data writing is performed in order of the distance from the bit line. That is, first, a high potential (-23 V) is applied to the control line SD and word lines WL, ~WL, and a low potential (-0 V) is applied to word II WL8.
and a high potential (-2
3 V) or an intermediate potential (-11.5 ■). At this time, in the memory cell Mk of the selected word line WL, electron emission occurs when the bit line BL is at a high potential, and the threshold value moves in the negative direction. Hereinafter, the word lines WL7, WL, .
...is lowered to a low potential and similarly emits electrons according to the data.

FIG. 9 shows more specific timing during the data write operation. Here, a case is shown in which word line WL is selected. Control line SD of the selection gate and unselected word lines WL, -WL. on the bit line side. ．． The bit line BL is raised prior to the time when a high potential is applied to the control line SD and the word line WL. -WL. The bit line BL is brought down with a delay from the falling of the bit line BL. This timing relationship is similar to the previous embodiment. If the rise of the bit line BL is delayed, the unselected word line W given a high potential
The memory cells L, ~WL, enter the erase mode, that is, the electron injection mode, resulting in an over-erased state. In this embodiment, since the data on the bit line is raised in advance, such over-erasing does not occur. The purpose of delaying the fall of the bit line is to similarly prevent over-erasing.

In this way, this embodiment also provides a highly reliable EEPR.
OM can be obtained.

In the embodiment shown in FIG. 9, as explained in the embodiment shown in FIG. It is effective to perform a controlled discharge operation.

〔Effect of the invention〕

As described above, according to the present invention, by giving a predetermined shift in timing during data write operation, erroneous writing and over erasing are prevented and reliability is improved.
A cellular EEFROM can be obtained.

[Brief explanation of the drawing]

FIG. 1 shows one NA of an EEPROM according to an embodiment of the present invention.
Plan views showing the ND cell, Figures 2 (a) and (b) are its A-
3 is an equivalent circuit diagram showing the memory cell array, FIG. 4 is a basic timing diagram for explaining its operation, FIG. 5 is a diagram showing the potential relationship of each part, 6 is a diagram showing specific timing during a write operation, FIG. 7 is a diagram showing specific timing during a write operation in another embodiment, and FIG. 8 is a diagram showing specific timing during a write operation in another embodiment with a different write method. 9 is a diagram showing the specific timing during the write operation. M1 to M8...memory cell, WL. to WL8...word line, BL...bit line, s,, S2...Selection gate, SD+, SS+...Selection gate control line, 1...
・P-type silicon substrate, 2... Element isolation insulating film, 3...
- First gate insulating film, 4... floating gate, 5... second gate insulating film, 6... control gate. (a) Applicant's agent Patent attorney Takehiko Suzue (b) Figure 2 [Mr. Ura] [} Figure 1 Figure [Shikyo 17] Figure 6

Claims (5)

[Claims] (1) A charge storage layer and a control gate are stacked on a semiconductor substrate, and a plurality of rewritable memory cells that perform data rewriting by transfer of charge between the charge storage layer and the substrate are connected in series to form a NAND cell. In a nonvolatile semiconductor memory device, the memory cell is arranged in a matrix, the drain at one end of each NAND cell is connected to a bit line, and the control gate of each memory cell is connected to a word line. A positive high potential is applied to the word line, a positive intermediate potential is applied to unselected word lines, and an intermediate or low potential is applied depending on the data to the bit line to accumulate charge from the substrate in the selected memory cell. 1. A nonvolatile semiconductor memory device having a data write operation of injecting electrons into a layer, and characterized in that during data writing, the timing of bit line rising is earlier than that of word line rising. (2) A charge storage layer and a control gate are stacked on a semiconductor substrate, and a plurality of rewritable memory cells that rewrite data by transferring and receiving charge between the charge storage layer and the substrate are connected in series to form a NAND cell. The NAND cells are arranged in a matrix, and the drain at one end of each NAND cell is connected to a bit line through a first selection gate, and the source at the other end is connected to a ground line through a second selection gate. In a nonvolatile semiconductor memory device in which the control gate of each memory cell is connected to a word line, a positive high voltage is applied to the word line selected in the NAND cell selected by the first and second selection gates. Applying a potential, giving a positive intermediate potential to unselected word lines and giving an intermediate potential or a low potential depending on the data to bit lines, injecting electrons from the substrate into the charge storage layer in the selected memory cell. 1. A non-volatile semiconductor memory device having a data write operation, characterized in that the bit line rising timing is earlier than the rising timing of a control line of a selection gate and a word line during data writing. (3) The nonvolatile semiconductor memory device according to claim 1, wherein the bit line falling timing is set later than the word line falling timing. (4) The non-volatile semiconductor memory device according to claim 2, wherein the bit line falling timing is set later than that of the control line of the selection gate and the word line falling. (5) A charge storage layer and a control gate are stacked on a semiconductor substrate, and a plurality of rewritable memory cells that perform data rewriting by transfer of charge between the charge storage layer and the substrate are connected in series to form a NAND cell. A selected word in a nonvolatile semiconductor memory device configured such that the NAND cell is arranged in a matrix, the drain at one end of each NAND cell is connected to a bit line, and the control gate of each memory cell is connected to a word line. A low potential is applied to the line, a positive high potential is applied to unselected word lines on the bit line side, and a high potential, intermediate potential, or low potential is applied to the bit line depending on the data, and the selected memory cell is It has a data write operation that releases electrons from the charge storage layer to the substrate, and when writing data,
A nonvolatile semiconductor memory device characterized in that the bit line startup timing is earlier than the word line startup timing.