JPH02232575A - Test circuit - Google Patents

Abstract

PURPOSE:To enable the implementing of a speed test by a short and simple input signal pattern by building up an exclusive circuit with first and second transfer gates TG having first and second clocks as gate inputs respectively and a delay circuit. CONSTITUTION:A clock pulse is inputted previously into a logic IC to be measured and an input signal pattern is inputted at a text input terminal 1. Outputs of a delay circuit 3, a second TG 4, a coincidence detection circuit 5 and a test output terminal 6 vary depending on when a signal propagates through the circuit 3 from a rising of a first clock to a falling of a second clock and when it fails to do. The former case corresponds to possibility of letting the signal propagate through a critical pass and the latter to impossibility thereof. Therefore, a speed testing is accomplished simply by repeating a test to observe an output of the terminal 6 with the inputting of the input signal pattern into the terminal 1 varying a clock pulse frequency. This can save labor and time required for the generation of the input signal pattern and enables the cutting of time for the test itself.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a test circuit for logic integrated circuits, and in particular to a test circuit used for a maximum operable clock pulse frequency test (hereinafter referred to as speed test) of a logic integrated circuit using a synchronous control method. Regarding circuits. [Prior Art] In a logic integrated circuit using a synchronous control method, each part of the circuit operates in synchronization with clock pulses that are generated at regular intervals. Therefore, the first clock to which the first clock is input is
The output signal of the gate is transmitted through the gates in the next stage and beyond,
The second clock must be input to the second gate before it becomes active. If there is sufficient time between when the first clock becomes active and when the second clock becomes active, that is, when the clock pulse frequency is low, the signal propagates from the first gate to the second gate. Either there is sufficient time for the above operation to occur, or the above operation becomes impossible if the clock pulse frequency increases. The upper limit of the frequency at which the above operation is possible is called the maximum operable pulse frequency, and the purpose of the speed test is to investigate this. By the way, in the speed test, even if you do not confirm that the above operation is performed in the section of the gate to which all clocks are input, the output of the first gate in the above section is transmitted to the next stage and the second stage. Investigate the section that takes the longest time to enter the gate (hereinafter referred to as the critical path),
If it is confirmed that the above operation is performed in that section, it can be expected that the above operation is performed in all sections, so it is only necessary to investigate the critical bus.

In conventional logic integrated circuits, speed tests are performed on the actual critical bus that exists within the integrated circuit. In other words, if a clock pulse is applied to an external terminal of a logic integrated circuit, the logic integrated circuit determines whether or not the output of the first gate in the actual critical bus has propagated to the second gate before the second clock becomes active. A speed test was performed by inputting a signal pattern devised so that it could be judged from the output of the external terminal to the external terminal, observing the output of the external terminal, and comparing the output with the expected output value. [Problems to be Solved by the Invention] In the conventional logic integrated circuit described above, creating an input signal pattern for a speed test requires a lot of manpower and time, and the input signal pattern for a speed test is long. The speed test itself also has the disadvantage of requiring a lot of time.

[Means to solve the problem]

The test circuit of the present invention includes a test input terminal that is an external terminal of a logic integrated circuit, a first transfer gate whose gate input is a first clock that inputs a signal from the test input terminal, and a second transfer gate. a delay circuit that receives the output as an input; a second transfer gate that receives the output of the delay circuit as an input and receives a second clock as a gate input;
It has a coincidence detection circuit which inputs the signal from the test input terminal and the output of the second transfer gate, and a test output terminal which is an external terminal of the logic integrated circuit and which outputs the output of the coincidence detection circuit.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a circuit diagram of an embodiment of the present invention. A test input terminal 1 is provided as an external terminal of a logic integrated circuit, and a first transfer gate 2 receives a first clock φ1 as a gate input. A signal is input from test input terminal 1 to . The delay circuit 3, which receives the output of the first transfer gate 2, is constructed of the same circuit as the actual critical bus in the logic integrated circuit, and the circuit is controlled so that the signal can propagate through the critical bus. There is. In this embodiment, the logic at the input and output of the delay circuit 3 does not change, and both are positive logic. The output of the delay circuit 3 is connected to a second transfer gate 4 whose gate input is the second clock φ2.
is input into . The output of the second transfer gate 4 is input to the coincidence detection circuit 5. The other input of the match detection circuit 5 is directly input from the test input terminal 1. The output of the coincidence detection circuit 5 is applied to the outside of the logic integrated circuit by a test output terminal 6 which is an external terminal of the logic integrated circuit. Here, the above test circuit is provided exclusively as a test circuit. FIG. 3 is a timing chart when the circuit of this embodiment is operated, and the numbers on the left side of the chart correspond to the numbers in FIG. 1. For example, the timing chart in FIG. This represents the output of Figure 2. A speed test using this example will be described. A clock pulse is input to the logic integrated circuit to be measured. Then, the input signal button shown in FIG. 3 is input to the test input terminal 1.

Then, the signal level of each part of the test circuit is
It changes as shown in Figures 2-6.

Here, there are two ways in which the outputs of the delay circuit 3, second transfer gate 4, coincidence detection circuit 5, and test output terminal 6 change.
b4. Indicated by bs. In the case of as+at+a in Figure 3,
This is a case where the signal can propagate through the delay circuit 3 from the rising edge of the first clock to the falling edge of the second clock. Figure 3 1) The case of $+b4+b5 is a case where propagation was not possible. The delay circuit 3 has the same circuit configuration as the actual critical bus in the logic integrated circuit, and in other words, the same signal propagation delay time can be expected for the same circuit on the same chip due to the nature of the integrated circuit. In the former case, the signal can propagate on the critical bus from the rising edge of the first clock to the falling edge of the second clock.
The latter corresponds to not being able to propagate. To determine which of the two cases is the case, observe the test output terminal 6 and refer to Figure 3 al.
It can be determined that the former case is true if l is changed, and the latter case is true if the change shown in Figure 3b is made. Therefore, a speed test can be performed by inputting the input signal button shown in FIG. 3 to the test input terminal 1 and repeating the test of observing the output of the test output terminal 6 while changing the clock pulse frequency.

FIG. 2 is a circuit diagram of a second embodiment of the invention.

This is almost the same as the first embodiment, but the difference is that the output of the second transfer gate 4 is input to AND together with φ2, the output is input to the RS flip-flop 7, and the RS
The other input of the flip-flop 7 receives the input from the test input terminal 1 and the first clock φ1.
The output of ND is input to h, and the output 8 of RS flip-flop 7 is input to coincidence detection circuit 5. Fourth
The figure is a timing chart of the circuit of this embodiment, and the view of the figure is the same as that of the first embodiment.

Next, a speed test using this embodiment will be explained. Input a clock pulse to the logic integrated circuit to be measured. Then, the same input signal as in the first embodiment is applied to the test input terminal 1.

Then, the signal level of each part of the test circuit is as shown in Fig. 4 2~
It changes like 6, 8. Here, a delay circuit 3, a second transfer gate 4, a coincidence detection circuit 5, a test output terminal 6
, there are two ways of changing the output of the RS flip-flop 7, aH+ aH+ aH+ in FIG.
Shown as ax and bzs+ b24* bz5tbat. Fig. 4 8 2*r & ,4r a 2Sna
In the case of t&, the signal can be propagated through the delay circuit 3 from the rising edge of the first clock to the rising edge of the second clock. Fig. 4 bx3e t) 21+ bzs+ bag
In this case, propagation was not possible. Since the delay circuit 3 has the same meaning as in the first embodiment with respect to the actual critical bus in the logic integrated circuit, the former of the above two cases is delayed from the rising edge of the first clock to the rising edge of the second clock. Since the signal can be propagated through the critical bus,
The latter corresponds to not being able to do it. As to which of the two cases it is, it can be determined that the change in azs in FIG. 4 is the former case, and the change in bts in FIG. 4 is the latter case, as in the first embodiment. Therefore, test input terminal 1
A speed test can be performed by inputting the input signal pattern shown in FIG. 1 and repeating the test while changing the test clock pulse frequency to observe the output of the test output terminal 6. In this embodiment, the period is from the rising edge of the first clock to the falling edge of the second clock in the first embodiment, but by adding the RS flip flop to the test circuit, the second
This has the advantage of being able to test signal propagation up to the rising edge of the clock. [Effects of the Invention] As explained above, the present invention can perform a speed test using a very short and simple input signal button by adding a dedicated test circuit, and as a result, the time spent on creating the input signal button can be reduced. This has the effect of reducing manpower and time, as well as reducing the time required for the speed test itself.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of the first embodiment of the present invention, FIG. 2 is a circuit diagram of a second embodiment of the present invention, and FIGS. 3 and 4 are the circuits of FIGS. 1 and 2, respectively. This is a timing diagram. DESCRIPTION OF SYMBOLS 1... Test input terminal, 2... First transfer gate, 3... Delay circuit, 4...
... Second transfer gate, 5 ... Coincidence detection circuit, 6 ... Test output terminal, 7 ...
...RS flip-flop, 8...RS flip-flop output. Agent Patent Attorney Shinkazu Uchihara φl γ! Kayi γ2 Zukan

Claims (1)

[Claims] The output of the first transfer gate having the first clock as the gate input is input to the circuit under test, the output of the circuit under test is input to the second transfer gate having the second clock as the gate input, and A test circuit for a logic integrated circuit, comprising a coincidence detection circuit whose inputs are an input to a first transfer gate and an output from the second transfer gate.