JPH02228746A - Error detecting circuit - Google Patents

Abstract

PURPOSE:To hold correct select information to discriminate erroneous input data by writing select information of data in a word of a storage means corresponding to this data and holding this select information in accordance with the error detection result of data. CONSTITUTION:In a storage circuit 12, selected data is written in the word indicated by a write address f inputted through a signal line 206, and select information d of input data indicated through a signal line 204 is written in the same word. At the time of read, a storage circuit 13 sends select information i of the word, which is indicated by a read address g inputted through a signal line 207 correspondingly to the storage circuit 12, to a select information indication flip flop PI 16 through a signal line 21, and this information i is held in the PI 16. Thus, correct select information is held at the time of detecting error of read data, and erroneous input data is discriminated.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to an error detection circuit, and more particularly, to an error detection circuit for a memory circuit that inputs data selected from a plurality of input data and is composed of a plurality of words. It is related to.

[Conventional technology]

A conventional error detection circuit is shown in FIG. In this circuit,
Input data selected by the selection circuit 1 from the input data on the signal lines 101 to 103 is set in the register 2 via the signal line 104. Then, a flip-flop (E I F,
Error Indication Flip Flo
p) The output signal of 4 is input to the OR circuit 5 via the signal lines 107 and 108, and the logical sum is calculated. The signal output from this OR circuit 5 via the signal line 109 causes
A flip-flop (PI) receives selection information on the signal line 105.

Path Indicator) 6 is retained. This makes it possible to identify which input data is incorrect if a data error is detected.

[Problem to be solved by the invention]

However, when the above-mentioned conventional technology is applied to a storage circuit composed of at least a plurality of words such as a register file, writing and reading addressing are performed independently, so that the selection information at the time of writing is transferred to the PI6.
Even if an error is actually detected in the read data, the selection information corresponding to the read data is not retained and it is not possible to identify which input data is incorrect. was there.

[Means to solve the problem]

In order to eliminate such drawbacks, the present invention provides an error detection circuit that detects errors in a target memory circuit, including a selection means for selecting one data from a plurality of input data, and a selection means corresponding to the target memory circuit. a storage means for holding selection information indicating which input data has been selected by the target storage circuit; an error detection means for detecting an error in the read data when reading the data from the target storage circuit; and a detection result of the error detection means. and a second flip-flop that receives the output of the storage means read out corresponding to the target storage circuit, and reads the contents of the second flip-flop according to the output of the first flip-flop. It was designed to be retained.

[Effect]

In the error detection circuit according to the present invention, it is possible to identify which input data is erroneous even if the timing at which data is written and the timing at which errors in that data are detected are far apart.

〔Example〕

FIG. 1 is a system diagram showing one embodiment of an error detection circuit according to the present invention. In FIG. 1, 11 is a selection circuit, 12
1 is a target memory circuit, 13 is a memory circuit as a memory means, 1
4 is an error detection circuit (PC), 15 is an input data error display flip-flop (EIF) that holds the data error detection result, and 16 is a selection information display flip-flop (PI) that receives selection information from the storage means 13. It is.

The selection circuit 11 selects data a, b, and c input via signal lines 201, 202, and 203 according to a signal d on a signal line 204, and sends the selected signal e to a storage circuit via a signal line 205. Send to 2.

The memory circuit 2 is a memory circuit composed of a plurality of words, and writes the input data e sent from the selection circuit 11 via the signal vA205 to the word indicated by the write address f input via the signal line 206. , data h held in the word indicated by the read address g input via the signal line 207 is sent to the PCl4 via the signal line 208.

The memory circuit 13 is a memory circuit that stores selection information of input data corresponding to the memory circuit 12, and writes the selection information d on the signal line 204 to the word indicated by the write address f.
Selection information li held in the word indicated by read address g
is sent to the PI 16 via the signal line 211. The selection information held in the word indicated by the read address g is written as selection information d from the signal line 204 when the data corresponding to the read address is written.

PCl4 is an error detection circuit that detects errors in data written in the memory circuit 2. It receives data h from the memory circuit 2 via the signal line 208, detects errors, and sends the result j via the signal line 209. Send to EIF15.

EIF15 is an error display flip-flop that lights up when a data error is detected in PCl4. It receives the error detection result via signal line 209, and when it lights up, it sends signal k to hold PI16 via signal line 210. and send it.

PI16 is a selection information display flip-flop that receives selection information Ht of human data sent from the storage circuit 13 via the signal line 211 in correspondence with EIF15;
When lit, the signal k is maintained by the signal k sent out via line 210.

Next, the operation of this embodiment will be explained. First, the operation when writing data will be explained. Input data a, b
, c are inputted through signal lines 201, 202 and 203, respectively, and the selection circuit 1 is selected according to the selection information d on the signal line 204.
1 is selected. The selected data is sent to the storage circuit 12 via the signal line 205. The memory circuit 12 writes the selected data into the word indicated by the write address f input via the signal line 206. At the same time, the memory circuit 13 writes the input data selection information d indicated via the signal vA204 into the word indicated by the write address f input via the signal line 206 corresponding to the memory circuit 12. That is, selection information for selecting the data is stored in the same word as the data.

Next, the operation at the time of reading will be explained. Memory circuit 12
sends the word data 11 indicated by the read address g input via the signal line 207 to the PCl4 via the signal line 208. At the same time, the memory circuit 13 sends word selection information i indicated by the read address g manually entered via the signal line 207 to the PI 16 via the signal line 211 corresponding to the memory circuit 12 . Memory circuit 12
Error detection is performed on the data sent from PCl4. If a data error is detected in PCl4,
The signal j on the signal line 209 becomes "1", and the EIF 15 holds "1". As a result, the signal k on the signal line 210 becomes "1''', and pH6 holds the selection information i sent from the storage circuit 13 via the signal line 211.

In this way, when an error occurs in the output data of the storage circuit 12, the manual selection information is always set in the PI 16, so that when an error is actually detected in the read data, the correct selection information is held. This makes it possible to identify which input data is incorrect.

〔Effect of the invention〕

As explained above, the present invention is capable of converting a plurality of input data into one
When selecting one piece of data and writing that data to a target storage circuit composed of multiple words, the selection information for that data is written in the same word of the storage means corresponding to the data, and the data error detection result is By retaining the selection information, it is possible to retain the correct selection information when an error is detected in the read 2 data, so even if the timing at which the data is written and the timing at which the error in that data is detected are different, This has the effect of being able to identify which input data is incorrect.

[Brief explanation of the drawing]

FIG. 1 is a system diagram showing an embodiment of an error detection circuit according to the present invention, and FIG. 2 is a system diagram showing a conventional error detection circuit. 11... Selection circuit, 12.13... Memory circuit, 14
...Error detection circuit, 15...Error display flip-flop, 16...Selection information display flip-flop,
201-211...Signal lines. Figure 1

Claims (1)

[Claims] In an error detection circuit that detects an error in a target storage circuit, selection means selects one data from a plurality of input data, and a selection indicating which input data is selected by the selection means corresponding to the target storage circuit. a storage means for holding information; an error detection means for detecting an error in the read data when reading data from the target storage circuit; and a first flip-flop for holding the detection result of the error detection means; a second flip-flop that receives the output of the storage means read out corresponding to the target storage circuit, and holds the contents of the second flip-flop according to the output of the first flip-flop. error detection circuit.