JPH02226985A - Vector coding and decoding device - Google Patents

Abstract

PURPOSE:To improve the compression efficiency by providing a vector deciding means deciding the identity of vectors included in split blocks and deciding plural vectors being objects of coding so as to apply hierarchical coding to moving vectors by the incorporation of blocks. CONSTITUTION:The code of inter-segment moving vector MV5 is made up of an identification bit and a code bit obtained through regarding the vector as an unequal length code when vectors in macro blocks Bi, j are all identical. When vectors in the blocks Bi, j are not equal, only identification bit is significant and the block bi, j is divided into 8X4 vector macro blocks Bi, j (k/2)(k/1, 2)2. With respect to each code bit to Bi, j (k/2), the identification bit is assigned similarly and the remaining code bits are assigned to the Bi, j (k/2) vectors. The processing above is repeated to apply coding of a block of 8X8 vector.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to vector encoding and decoding, and in particular to motion encoding and decoding in interframe encoding used in compression and expansion of digital moving images. The present invention relates to a vector encoding/decoding device suitable for motion vectors used for compensation.

[Prior Art 1] Motion compensated interframe predictive coding is a method for highly efficient coding of digital video images. In this method, in units of pixels or blocks composed of multiple pixels,
The motion of the image between frames, that is, the motion vector is detected.

Then, using this motion vector, a new image is synthesized from the pixels of the decoded image one frame before, and the difference between the current frame and the synthesized image and the motion vector are encoded.

Further, in the decoding operation, the encoded difference and motion vector are decoded, and the current frame is decoded using the decoded image of the previous I norm.

By the way, the above-mentioned encoding and decoding of motion vectors has conventionally been performed by unequal-length encoding and decoding of the difference vector with respect to the motion vector, or by unequal-length encoding and decoding of the difference vector with respect to a specified vector. It was.

For example, Japanese Patent Application Laid-Open No. 57-199379 discloses a vector encoding device that gives short codes to small vectors and long codes to large vectors.

[Problems to be Solved by the Invention] However, when assigning codes to differential vectors, it is difficult to assign at least a 1-bit code to each vector, especially when fixed motion vectors form a group, such as in the background. A shortcoming occurs during which the compression efficiency cannot be improved.

Furthermore, the encoding of vectors obtained by a plurality of means cannot be realized simply by encoding the difference.

Furthermore, since the method is used differentially in the horizontal or vertical direction, there is also the disadvantage that the influence of error propagation on the transmission path is large.

The present invention has been made in view of the above two points, and its purpose is to improve the compression efficiency of encoding.

Another object is to perform well the encoding and decoding of vectors obtained by multiple means.

Yet another objective is to reduce the degree of error propagation in the transmission path.

[Means for Solving the Problems 1] One of the main aspects of the present invention is that in a vector encoding device that encodes a plurality of vectors with unequal length, a block that divides a plurality of vectors into a predetermined number of blocks is provided. a dividing means, a vector determining means for determining the identity of vectors included in one divided block, and when it is determined that all the vectors are the same, a code representing that fact and a code representing the vector; If it is determined that they are not the same, a code indicating this is assigned and a division command is issued to the block division means, and when the division by the block division means is completed, a code is assigned to each different vector in the final block. The present invention is characterized by comprising an encoding means for allocating the information.

[Operation] According to the present invention, it is determined whether a plurality of vectors to be encoded are the same. As a result, when it is determined that they are the same, that fact and the vector are encoded.

If it is determined that they are not the same, that fact is encoded and the plurality of vectors are divided into appropriate blocks.

Then, the above-described operation is performed for each block, and when it is determined that the vectors are not the same, the blocks are divided again.

When these operations are repeated to reach the final block, encoding is performed for each vector within that block.

[Example] Two examples of the present invention will be described below with reference to the accompanying drawings.

Coding Method> In this embodiment, as shown in FIG. 2, coding is performed for each coding segment SG in units of five frames. Intra-frame encoding is performed on the first and second leading frames S of this encoded segment SG, and inter-frame encoding with motion compensation 71 is performed on the remaining four frames.

In this case, an inter-segment motion vector MV5 between the first frame SH in the encoded segment SG and the first frame SH of the next encoded segment SG is determined. When motion compensation is performed, a motion vector adaptively selected from the motion vectors estimated from the interframe motion vector -Vi (i=0 to 3) and the intersegment motion vector MV5 is used.

<Configuration of Embodiment> FIG. 1 shows a block configuration of such an embodiment. In the figure, frame memories 12 to 22 are connected to the output side of the selector 10 to which the digitized signal is input.
The input terminals of are connected to each other. The output sides of these 71 norm memories 12 to 22 are all connected to the input side of the selector 24.

Next, the output side of the selector 24 is connected to an inter-segment motion vector detection circuit 26 . Interframe motion vector detection circuit 2
8. Motion compensation circuit 30. They are each connected to the input side of the intraframe encoding circuit 32. The output side of the inter-segment motion vector detection circuit 26 is connected to the input sides of the inter-segment motion vector encoding circuit 34 and the motion vector selection circuit 36, respectively, and the inter-frame motion vector detection circuit 2
The output side of 8 is also connected to the input side of the motion vector detection circuit 36.

Next, one output side of the motion vector selection circuit 36 is connected to the input side of the motion vector encoding circuit 38, and the other output side is connected to the input side of the motion compensation circuit 30. Further, one output side of the intraframe encoding circuit 32 described above is connected to the input side of the intraframe decoding circuit 40, and the output side of the intraframe decoding circuit 40 is connected to the input side of the motion compensation circuit 30. It is connected to the.

The output side of this motion compensation circuit 30 is connected to a differential encoding circuit 42.
This differential encoding circuit 42 is connected to the input side of
The output sides of are each connected on the one hand to the input side of an interframe decoding circuit 44. The output side of this interframe decoding circuit 44 is connected to the input side of the motion compensation circuit 30.

Further, an inter-segment motion vector encoding circuit 34, a motion vector encoding circuit 38. Differential encoding circuit 42. Each output side of the intraframe encoding circuit 32 is connected to a buffer 4.
6 input terminals, respectively.

<Operation of the Embodiment> Next, we will explain the general operation of the embodiment configured as described above.
are selected by the selector 10 from the frame memories 12 to 22.
are supplied and stored in order.

Next, the selector 24 reads out the first frame SH of the encoded segment SG and the first frame SH of the next encoded segment SG from the frame memories 12 to 22, and inputs them to the inter-segment motion vector detection circuit 26. Here, the inter-segment motion vector MVS is detected and further encoded by the inter-segment motion vector encoding circuit 34.

On the other hand, the first frame SH is processed by the intraframe encoding circuit 32
Based on this, the intra-frame decoding circuit 40 decodes the encoded image. This decoded image is output to the motion compensation circuit 30 because it is used for motion compensated interframe coding for the next frame. The resulting difference after motion compensation is encoded by the differential encoding circuit 42.

Furthermore, the second and subsequent frames of the encoded segment SG are sequentially read out from the frame memories 14 to 22 by the selector 24 and input to the interframe motion vector detection circuit 28. Then, using the decoded image of the previous frame, the interframe motion vector −vl
Detection is performed. The detected inter-frame motion vector MVi is input to the motion vector selection circuit 36 together with the inter-segment motion vector MV5, where the motion vector MV is adaptively selected.

The selected motion vector MV is input to the motion vector encoding circuit 38, where it is encoded. The interframe decoding circuit 44 performs interframe decoding using the output of the motion vector encoding circuit 38 and the output of the differential encoding circuit 42, and the decoded image is input to the motion compensation circuit 30.

Further, a motion vector MV is also input to the motion compensation circuit 30, and motion compensation is performed using this motion vector paste and the decoded image of the previous frame.

Next, an inter-segment motion vector encoding circuit 34, a motion vector encoding circuit 38. Differential encoding circuit 42. Each output code of the intraframe encoding circuit 32 is input to a buffer 46 and stored therein. After speed adjustment is performed here, each code is output to a transmission path (not shown).

Encoding of inter-segment motion vector> Next, the encoding of the inter-segment motion vector -v5 by the encoding circuit 34 will be explained with reference to FIGS. 3 to 7. As shown in FIG. 3, the inter-segment motion vector MV5 determined in 1 is divided into macroblocks Bi, j each having an 8×8 vector as a unit.

First, the codes of the inter-segment motion vector pasting 5 are as shown in FIG. 5 fAl. In other words, if all the vectors in macroblocks Bi, j are the same, the code is composed of a 1-bit leading identification bit indicating this, and a code bit obtained from the vector as an unequal length code. be done.

Next, if the vectors in the macroblock Bi,j are not all the same, fA+ in FIG. 5 is only the identification bit,
The macroblock Bi, j is an 8×4 vector macroblock Bi, ]k/2) (k=1.2) divided into two (FIG. 4 IA) iB) 1 town, and each divided macroblock The identification bits 1 to 1 and the code bits generated every BL, j (k/2) are as shown in Fig. 5 f8).
Each 0-divided macroblock Bi,j (k/21
Similarly, one identification bit is provided for each code bit for the macroblock Bijfk/21, and the remaining code bits are assigned for coding to the vector of each macroblock Bijfk/21.

The above processing is repeated, and the macroblock Bi,
j ik/2) is the macroblock Bi, j, k(β/2) 1I2 as shown in Fig. 4 fG+, (Dl)
=1.2+, Bi, j, k.

β(m/2) fmlll, 21, and on the other hand, the identification bit and code bit generated for each divided macroblock are as shown in Fig. 5 fc1.103, respectively.
The same diagram that was generated earlier! B+ and (h) are each additionally connected to the rear of the code of C1. By such divisional encoding of the macroblock, encoding of an 8×8 vector block is performed.

In addition, the division of the macroblock Bij is stopped at a specified size, and the vector difference is calculated according to the direction shown in FIG.
It is also possible to perform unequal length encoding of the difference vector. In this case, among the macroblocks generated by dividing the macroblock 61.1 in FIG. The vector on the left of l block is used as the initial value for other macroblocks.

Next, an example of macroblock division coding shown in FIGS. 3 to 5 will be described with reference to FIGS. 6 and 7. FIG. 6A shows a case where all vectors in a block of 8x8 vectors are VO. Let rOJ be the identification bit when all vectors in a block are the same, and let C be the unequal length code of vector Vi.
Assuming Vi, the entire code of the inter-segment motion vector MV5 is as shown in fB) in the same figure.

Next, the sign of the inter-segment motion vector MV5 when the vectors in the 8×8 macroblock have a distribution as shown in TAI in FIG. 7 is as shown in FIG. 7(B). Further, the binary structure of the identification bits generated by repeating the division of the macroblock is as shown in FIG.

Motion Vector Encoding> Next, the operation of the motion vector encoding circuit 38 will be described. When the motion vector selection circuit 36 selects an estimated vector based on the inter-segment motion vector 1JV5, one code is assigned in the motion vector encoding circuit 38. Then, the above-mentioned inter-segment motion vector MV5 is encoded (see FIGS. 3 to 7).
Similarly, blocks are hierarchically combined into macroblocks, and the motion vector -■ is encoded.

However, in the case where the division of the macroblock is stopped at blocks of a specified size and the estimated vector is included in the macroblock, the processing is as shown below. First, as shown in FIG. 10(A), the sign of the estimated vector -VB is assigned to the difference vector -■ΔAB between the vector 5a (including the estimated vector MVAf) and the current estimated vector -VB.

Also, as shown in fB) in the same figure, the difference vector between the previous vector and the current vector (excluding the estimated vector) is encoded as follows. First, the previous vector of vector bO is the estimated vector. If the vector bl
The difference vector between the vector and the previous vector is encoded. If vector 5 and bl are both estimated vectors, vector b2 is encoded. Vector bO9b1. If both b2 are estimated vectors, the difference from the zero vector is encoded.

<Specific Example of Code System> Next, with reference to FIG. 11, a specific example of a code system that performs the hierarchical integration of the above-mentioned vectors into macroblocks will be described.

In the figure, the output side of the vector memory 50 is on the one hand a vector register VRata=5.4.3°2
．． 1.01 is connected to the input side of the address generation circuit 52, and the other output side is connected to the comparator circuit CP5.
is connected to the input end of the

The output side of the comparison circuit CPbfb=5.4.3.2.1.01 is a vector register VRa and a flag register F.
Rc (c=5°4.3.2.1.Ol), and the output sides of the flag register FRc are both connected to the input end of the address generation circuit 52. Vector register VRaia=5.4,3,2
, 1) is connected to the comparator circuit CPb (b=4.3
．． 2.1.01 is connected to the input side.

One output side of the flag determination circuit 54 is connected to the other input side of the address generation circuit 52, and the output side of the address generation circuit 52 is connected to the comparison circuit CPb (b-5, 4, 3).
, 2, 1, 0), are connected to the input terminals of the flag determination circuit 54 and the unequal length encoding circuit 56, respectively. and,
flag? ! +1 constant circuit 54. The output sides of the unequal length encoding circuit 56 are both connected to the input side of a buffer 58.

Next, the operation of the code system as described above will be explained using the case shown in FIG. 7 fA) as an example. First, the comparator circuit CP5 reads an 8.times.8 block vector (see +A+ in FIG. 13) from the vector memory 50 using the address inputted from the address generation circuit 52. Then, it is determined whether the vectors are the same for each of the 32 macroblocks shown in FIG. 12 fA).

As a result of the determination, if they are the same, the logical value is "0", and if they are not the same, the logical value is "rl", which is set in the flag register FR5 as shown in FIG. 13(B). Further, if it is determined that they are the same, the solids 1 to 1 are input to the corresponding position of the vector register VR5,
If it is determined that they are not the same, vector register VR5
The address of that vector is entered manually at the corresponding position.

For example, "P6" in the figure corresponds to this.

Next, the comparator circuit CP4 similarly uses the address inputted from the address generation circuit 52 to generate the data as shown in FIG.
Two vectors corresponding to the macroblocks shown in are read out and compared. The comparison result is similarly set in the flag register FR4, and the vector or address is input into the vector register VR4 (first
Figure 3 fG1 M).

When the above operations are repeated, vector register VRa
, the contents of flag register FRc are as shown in FIG. Then, in this state, that is, a state in which all registers are set, the encoding shown in FIG. 7(B) is performed by performing a search in the reverse direction as shown by the arrow in FIG. That is, the flag register FRifiJ,1
．． The flag set to 2.3.41 is read by the address generation circuit 52 and determined by the flag determination circuit 54.

As a result, if the logical value is "0", it is determined that the buffer 58
is output to. Also, the corresponding vector register VRi
The vectors are read out, subjected to unequal length encoding by the unequal length encoding circuit 56, and output to the buffer 58.

On the other hand, if the logical value is rl4, it is output to the buffer 58. Further, the corresponding address is read from the vector register VRi, and the address generation circuit 52
is used as the read address of flag register FRi+1, and the vector is read out. Note that the flag register FR5 is used as a read address of the vector memory 50.

Specifically, referring to the example shown in FIG. 7 (fAl, FB), the logical value of the flag register FRO is "1".
Therefore, the logical value r14 is sent from the flag determination circuit 54 to the buffer 58, and the registers VR
Address PO in O is stored in address generation circuit 52.

Next, the flags indicated by the address PO (see arrows YA and YB in FIG. 13) are sequentially read out in the two-flag register FRI. The first flag (arrow FA) has a logical value of "0", so it is sent to the buffer 58 and the vector V
D is read out and encoded by the unequal length encoding circuit 56. The encoded vector vO is sent to buffer 58. The next flag (arrow FII) is “l”, so “0” is sent to the buffer 58, and address P1 is read from the vector register VRO and stored in the address generation circuit 52. .

Similarly, the flags indicated by the five addresses PL (see arrows yc and yo in the figure) are sequentially read out from the flag register FR2. Then, the above-mentioned processing 7 y 58 i: Irl, 0, CVI J is input.

Furthermore, by processing the flag register FR3, “0
, CV2.1" is input.

Next, in flag register FR4, both flags are r
14, "l, l" is input to the buffer 58, and the address generation circuit 52 receives the address P4. P5 are respectively stored.

Next, in flag register FR5, the vector corresponding to address P4 of address generation circuit 52 is processed in the same manner, and then the vector corresponding to address P5 is processed continuously. As a result, the buffer 58 contains Ir01CV3.0, CV4.0, CV5. IJ
is done manually.

Finally, the vector corresponding to address P6 in vector register VR5 is read out from vector memory 50 and processed in the same manner. As a result, Buff 758
, rO1CV6.0, CV7, and ll are input. Note that vector V6. Since V7 is also the terminal,
"01 can be omitted.

Through the above processing, the code shown in FIG. 7 (FB) is output from the buffer 58.

(Specific example of Mq system) Next, a specific example of a decoding system corresponding to one or more code systems will be explained with reference to FIG. 14. In the figure, the output side of the buffer 60 is It is connected to the input side of the unequal length decoding circuit 62, and the other side is connected to the input end of the flag determination circuit 64. One output side of this flag determination circuit 64 is connected to the input side of the buffer 60. The other output side is an unequal length decoding circuit 62.
It is connected to the input side of the address generation circuit 66 as well as the output side of the address generation circuit 66 .

Next, the first output side of the address generation circuit 66 is pect,
It, Lz register VRd (d=0.1.2.3.4.5
) are connected to the input side of the memory 68.

The second output is flag register FRe (e=o, l
, 2.3.4゜5) are connected to the input terminals of
The third output side is a control circuit CTLf (f・0.1, 2.
The output sides of the vector register VRd and the flag register FRe are respectively connected to the input sides of the control circuit CTLf, and the output side of the control circuit CTL5 is connected to the input side of the control circuit CTLf. It is connected to the input side of vector memory 68.

Next, the operation of the decoding system configured as above will be explained. If the code stored in the buffer 60 is a flag, it is output to the flag determination circuit 64, and if the flag is "0", it is output to the flag determination circuit 64 (the code is output to the unequal length decoding circuit 64).
2 is output. The flag is determined by a flag determination circuit 64.

As a result, flag register FRi (i=1.2.3,4
．． When the 51 flag is "0", it is set in the corresponding flag register FRi. Next, buffer 60
The code output from ! is decoded by the unequal length 1 circuit 62, and ! ! The encoded vector is stored in vector register V
Ri(iJ, 2, 3, 4.51] corresponds to 67)'L/S.

Further, if the flag is r14, it is set in the corresponding flag register FRi. Subsequently, the corresponding address of flag register FRi+1 is flag register FR.
It is set to the corresponding address of j. Next, the flag in flag register FRL-1 is read out, and if it is a logical value of "0", "0" is set to the two corresponding addresses of flag register FRi through control circuit CTLi, and vector register VRi A vector corresponding to -1 is set to two corresponding addresses of vector register VRi.

The above processing is repeated, and the decoded vector is stored in the vector memory 68 and output.

Specifically, referring to the example of FIG. 7 FA,l,(B), the first code is a logical value "1". Therefore, "1" is set in the flag 1 register FRO, and the address indicated by the arrow in FIG.
is set to

The next code is a logical "0". Therefore, the logic value "0" is set in the at1nos corresponding to PO of the flag register FRI. Then, the next code CvO is decoded by the unequal length decoding circuit 62, and the V port is set to the corresponding address of the vector register VRI.

Next, the code following the code CvO is a flag, which is “
Therefore, like flag register FRO, flag register FRI is set to "1", address PL is set to address generation circuit 66, and flag register FRO is checked. Since this is "1",
The processing in flag register FRI ends.

Next, flag register FR2 is processed. The first sign of R is the logical value rlJ. Therefore, the address pt set in the address generation circuit 66 is used, and rlJ is set in the corresponding flag register FRI. Further, the next code is "0" and the next code is rcVIJ.

Therefore, similar to the processing in the old flag register F,
Flag register F[t2. A code corresponding to a predetermined address of vector register VR2 is set.

Furthermore, the flag of the flag register FRI is checked. Since the logical value is "0", the vector VO of the vector register VRI corresponding to the address of this "0" corresponds to the address of the flag register FRI. is set in two address registers of flag register FR2.

The above process is repeated, and 6
Four vectors are input and output.

<Effects of Example> As described above, according to this example, the following effects are achieved.

(1) In the conventional method, codes are assigned to difference vectors, so at least one bit of code is required for each vector. For this reason, there are disadvantages such as inability to improve compression efficiency.

In contrast, in this embodiment, motion vectors are hierarchically encoded by block integration.

For this reason, it is necessary to significantly compress areas where conventional methods cannot achieve compression efficiency, especially in cases where there is a constant motion vector in an image such as the background, or in cases where an object moves with little change in shape. Efficiency can be improved, and vectors obtained by multiple means can be encoded.

(2) Furthermore, since the code of the motion vector is determined in units of macroblocks, the propagation of errors in the transmission path is
It is possible to keep it within a macroblock.

<Other Embodiments> Note that the present invention is not limited to the above embodiments, and the code system shown in FIG. 11 may be configured as shown in FIG. 15. A good example of this configuration is vector register 70. The flag registers 72 are all constructed from one memory, and the comparison circuit 74 is also constructed in common.

Further, the decoding system shown in FIG. 14 may be configured as shown in FIG. 16. This configuration example also has solid registers 1 to 80. The flag registers 82 are all constructed from one memory, and the control circuit 84 is also constructed in common.

In either case, the operation is as described above, but the circuit configuration is greatly simplified.

Furthermore, although the above embodiments are directed to motion vectors used in the digitization of television signals,
Other vector quantities may be used as targets.

[Effects of the Invention] As explained above, according to the present invention, it is possible to improve the compression efficiency of encoding, and it is also possible to efficiently encode and decode vectors obtained by a plurality of means. Furthermore, there is an effect that the degree of error propagation in the transmission path can be reduced.

[Brief explanation of the drawing]

FIG. 1 is an overall configuration diagram of a code system showing an embodiment of the present invention.
FIGS. 2 to 8 are explanatory diagrams showing the encoding method in the above embodiment, FIGS. 9 and 10 are explanatory diagrams showing other encoding methods, and FIG. 11 is an explanatory diagram showing an example of the configuration of the coding system. 121J and 13 are explanatory diagrams showing the operation of the code system shown in FIG. 11, and FIG. 14 is a block diagram showing a decoding system corresponding to the code system shown in FIG. 11, and FIGS. The figure is a block diagram showing another embodiment. 10.24... Selector, 12-22... Frame memory, 26... Inter-segment motion vector detection circuit, 28... Inter-frame motion vector detection circuit, 30.
...Motion compensation circuit, 32...Intraframe encoding circuit,
34... Inter-segment motion vector encoding circuit, 36
. . . motion vector selection circuit, 38 . . . motion vector encoding circuit, 40 . . . intraframe decoding circuit, 42.
. . . Differential encoding circuit, 44 . . . Intraframe decoding circuit, 46 . . . Buffer. Patent applicant: Japan Victor Co., Ltd. Representative: Kunio Kakiki Figure 75, Daλ Figure

Claims (6)

[Claims] (1) In a vector encoding device that encodes a plurality of vectors with unequal length, a block division means divides the plurality of vectors into a predetermined number of blocks, and a block division means that divides the plurality of vectors into a predetermined number of blocks, and a block division means that determines the identity of vectors included in the divided blocks. A vector determining means for determining, and when all the vectors are determined to be the same, a code representing that fact and a code representing the vector are assigned, and when it is determined that all the vectors are not the same, a code representing that fact is assigned. and a coding means for assigning a code to each different vector in the final block, and issuing a division command to the block division means, and assigning a code to each different vector in the final block when division by the block division means is completed. Device. (2) An inter-frame motion vector (MV_i) estimated from the motion vector (MV_M) between M frames and a motion vector (MV) adaptively selected from this inter-frame motion vector (MV_i), and a motion compensated predictive code When encoding a motion vector (MV) when performing a Motion vector (MV_i)
is used, its interframe motion vector (MV
A vector encoding device characterized by encoding _i). (3) The vector encoding device according to claim 2, further comprising block dividing means for dividing the motion vector (MV) into a predetermined number of blocks; A vector determining means for determining identity, and when it is determined that all vectors are the same, a code representing that fact and a symbol representing the vector are assigned, and when it is determined that they are not the same, a symbol representing that vector is assigned. a vector that is characterized by comprising: encoding means that assigns a code representing the vector, issues a division command to the block division means, and assigns a code to each vector in the final block when division by the block division means is completed; Encoding device. (4) In the vector encoding device according to claim 3, when different vectors exist within a block, in encoding the inter-frame motion vector (MV_i), among the neighboring vectors, a neighboring vector at a certain position and If the vector is a motion vector (MV_M) between M frames, among the neighboring vectors,
A vector code characterized in that a difference vector between a neighboring vector at a next fixed position is encoded, and a code is assigned to the information when encoding a motion vector estimated from a motion vector (MV_M) between M frames. conversion device. (5) In the vector encoding device according to claim 3, when different vectors exist within a block, in encoding the inter-frame motion vector (MV_i), a difference vector with a constant vector is encoded, and M frames are encoded. In encoding a motion vector estimated from a motion vector (MV_M) between, a vector encoding device assigns a code to the information. (6) A vector decoding device that decodes a code encoded by the vector encoding device according to any one of claims 1 to 5.