JPH02226829A - Duplex communication system - Google Patents

Abstract

PURPOSE:To make a duplex communication efficiently in real time hy monitoring the signal state on a monitor line and judging whether or not transmission is possible, performing the transmission only when possible, and putting the system back into a reception wait state when not. CONSTITUTION:A 1st equipment 1A and a 2nd equipment 1B which are expected to make a duplex communication are connected by a clock line 3, a data line 5, a period line 7, and a DCL line 9 constituting the monitor line. Then the signal state on the monitor line is monitored to perform the transmission only when it is judged that the transmission is possible, but the system is put back into the reception wait state. Consequently, the duplex communication is made efficiently in real time.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention relates to a two-way communication system that performs two-way communication between a plurality of devices.

(Prior Art) In the conventional bidirectional communication system, as shown in FIG. 7, when bidirectional communication is performed between the first device 51 and the second device 53, the first 1 acts as a master, the second device 53 acts as a slave, and the first 8
Data is transmitted by polling from 1151. More specifically, as shown in FIG.
A clock line 55 for transmitting a master clock is connected between the device 51 and the second device 53.
A data line 57, a latch line 58, which transmits data in synchronization with the clock of 5, and a control line 59, which is a transmission permission line that transmits a transmission permission signal from the 1N51 mask of I'11 to the slave of the second device 53.
connected with. Then, from the mask of the first device 51, the second device il! To send data to the slave of the I53, the polling method is used as described above, but when transmitting data from the slave of the second device 53 to the mask of the first device 51, the first This is done by the device 51 setting the transmission permission line 59 to a low level.

In this case, the first device 51 sets the control line 59 to a low level, and upon receiving one packet from the second device 53, sets the control line 59 to a high level, repeating this operation at regular intervals. .

(Problems to be Solved by the Invention) In the conventional two-way communication method described above, even if a communication factor occurs, the slave device cannot transmit it to the mask in real time, and the mask uses polling to detect when there is no data. There is also an overhead due to so-called polling, which requires communication with the slave at regular intervals, which is inefficient, and there is also a problem that there is a load on the slave side due to the communication clock supplied from the mask side.

The present invention has been made in view of the above, and its purpose is to provide a two-way communication system that satisfies real-time requirements and efficiently performs two-way communication.

[Structure of the Invention] (Means for Solving the Problems) In order to achieve the above object, the bidirectional communication system of the present invention has the following features:
It is a two-way communication method that performs two-way communication between multiple devices, and it uses a data line that connects each device to transmit data bidirectionally between each device, and the status of the other device to which data is transmitted. A monitoring line connecting each device to be monitored; and a standby state provided in each device to supply a first signal level on the monitoring line to indicate the state when each device is in a reception standby state. a display means, a transmission state display means provided in each device and which supplies a second signal level to the monitoring line to display the transmission state when each +A device attempts to transmit; and the transmission state display means a line state monitoring means for monitoring the signal state on the monitoring line; and when the signal state on the monitoring line monitored by the line state monitoring means is at a first signal level, transmitting via the line state monitoring means; Judging that it is possible, send it with μ, and send the second
and a transmission control means which returns to a reception standby state as being unable to transmit when the signal level is at .

<Function> In the two-way communication system of the present invention, each device is connected by a monitoring line, and when each device is in a reception standby state, a first signal level is supplied on the monitoring line, and each device I transmits. providing a second signal level on the monitoring line and monitoring the signal state on the monitoring line;
When the signal state is at the first signal level, it is determined that transmission is possible and transmission is performed, and when the signal state is at the second signal level, it is determined that transmission is impossible and returns to the reception standby state.

(Example) Hereinafter, the present invention will be explained in detail using the drawings.

FIG. 1 is a diagram showing the overall configuration of a bidirectional communication system according to an embodiment of the present invention. As shown in the figure, a clock is transmitted between the first device 1Δ and the second device 1B that are attempting to perform bidirectional communication. A clock line 3 for transmitting data, a data line 5 for transmitting data, a period line 7 for transmitting latch pulses for latching data, and indicating the status and communication direction of each device so that the status of each device can be monitored and determined. They are connected by a DCL line 9 that constitutes a monitoring line. Figure 2 (a), (b).

(C) shows the timing of the clock, data, and period signals when transmitting 1 byte, which are output to the clock line 3, data line 5, and period line 7, respectively.

FIG. 3 shows each unit 111A, 1 of the clock line 3, data line 5, period line 7 and DCL line 9.
FIG. 2 is a circuit diagram of a bus interface in B. FIG. As shown in the figure, each line is pulled up by a resistor and transmitted and received via an oven collector. Note that FIGS. 1 to 3 show the case of serial communication.

In the configuration as described above, each 1111i supplies a signal indicating its own state, that is, whether it is in a reception standby state or a transmission state, on the DCL line 9, and also sends a signal to the DCL line 9. In doing so, the signal status on the DCL line 9 is monitored, and based on this, it is determined whether transmission is possible or not, and the signal is transmitted only when it is possible to transmit.
If transmission is not possible, the device returns to a reception standby state.

The following table is a signal level table showing the state on the CL line 9 and the state of each device.

(Hereinafter, blank space) As shown in this table, when each device is in the reception standby state, each device outputs a low level signal on the DCL line 9, and each *i, i and D CI- All signal levels on line 9 are in a low state.

Next, when the first device 1△ transmits in such a state, it outputs a high level (H) signal onto the DCL line 9, checks the signal level on the DCL line 9, and transmits the corresponding signal. If the signal level is low, the second 11119
1B is also at a low level, and transmission from the first device 1A to the second device 1B is possible.

Furthermore, when the first device 1△ attempts to transmit and outputs a high level signal to the DCL line 9F, as a result of ixing the signal level on the DCL line 9, if the signal level is high, the The second device 1B is at a high level, that is, all the devices are at a high level and cannot transmit. Therefore, the first device 1A that attempted to transmit is the DCL
The output on line 9 is returned to low level to return to the reception standby state. In this case, there are two cases: the other party's second m unit 1B has already entered the transmission sequence;
This is a case where the first device 1A and the second device 1B attempt to transmit simultaneously and output high level signals onto the DCL line 9. In such a case, the output signal on the DCL line 9 will be returned to a low level, and the transmission will be retransmitted after waiting a certain period of time.

Also, at the bottom of the table is a case where device 1B of EI2 tries to transmit, but this is the case where device 1A of the second first device in the table
This is the same behavior as when trying to send a message.

FIG. 4 shows detailed circuits of the main parts of each device shown in FIG. 1. In the figure, the circuit of the first device 1A is shown in detail, and only the output buffer 11 of the second device 1B connected to the first device 1A via the DCL line 9 is shown. , the circuit of the second device 1B is also the same as that of the first device 1.
It is the same as the circuit of a1A.

In the circuit of the first device 1A shown in the figure, D CL
A full-up resistor 13 is connected to one end of the line 9, and the output of the output buffer 715 and the input buffer 17
is connected to the input of the first TA device 1A via the output buffer 15 to output a high 1 novel signal or a low level signal onto the DCL line 9, and also,
Via an input buffer 17 it is possible to receive the signal level on the DCl- line 9.

In addition, the input of the output buffer 15 has a timing I#1.
It is connected to the transmission request line b of the m circuit 19. The timing υIWI11 circuit 19 1 is OR circuit 2
1 to the transmission request line a of the transmission module 23. The transmitting module 23 has the aforementioned clock line 3, data line 5 and period line 7, and is connected to the second m-unit 1B via these lines.

In addition to being connected to the input of the output buffer 15, the transmission request line b of the timing control circuit 19 is also connected to the data input of the first latch circuit 25.
Timing l11111 circuit 1 as clock input of 5
The transmission request signal from the timing control circuit 19 is latched by the first latch circuit 25 by the determination result latch pulse supplied from the timing control circuit 19 through its output line C, and the output of the first latch circuit 25 is ready for transmission. , is supplied to one input of an AND circuit 29.31 that determines whether or not the output is acceptable.

Further, the signal level on the DCL line 9 received by the input buffer 17 is supplied to the receiving module 41, and is also supplied to the data input of the second latch circuit 27, so that the DC
The signal state on the L line 9 is changed to the second latch circuit 27 by the determination result latch pulse from the timing control circuit 19.
The output of the second latch circuit 27 is supplied to the other input of the AND circuit 29 via the inverter 39, and also directly to the other input of the AND circuit 31, whereby the output of the AND circuit 29 and 31, respectively, to output a transmittable or transmittable signal. A transmittable signal outputted from the AND circuit 29 is supplied to the transmitting module 23 and the receiving module 41, thereby starting a transmitting operation.

The transmission disable signal outputted from the AND circuit 31 is passed through the delay circuit 33 and the NAND circuit 35. 1JI
Clear terminal CLR of I11 circuit 19 and latch circuit 2
5.27, and clears them, and after a predetermined time delay via the delay circuit 37, is further supplied to the input i of the timing control circuit 19 as a retransmission signal via the OR circuit 21. It has become. Further, the transmission completion signal @g from the transmission module 23 is configured to clear the timing control circuit 19 and the latches 25 and 27 via the NAND circuit 35.

Next, the operation of the circuit shown in FIG. 4 will be explained with reference to the timing diagram shown in FIG.

FIG. 5(a) shows the signal level on the DCL line 9, and FIG. 5(n) shows the signal level of the other device, that is, the second device 1B.
The signal level that is being output on DCL line 9 is shown. First, as shown in the first half of FIG. , as shown in FIG. 5(b), when a transmission request signal is output to the transmission request line a of the transmission module 23, this signal drives the timing control circuit 19 via the OR circuit 21, and the timing control circuit 19 Figure 5 (C)
A transmission request signal is output to transmission request line b as shown in FIG. This transmission request signal is sent to the DC via the output buffer 715.
It is output on the L line 9 as well as in FIG. 5(d).
The determination result latch pulse from the timing control circuit 19 shown in FIG.

Further, the signal level on the DCL line 9 when the first device 1A attempts to transmit is transmitted to the second device via the input buffer 717.
is supplied to the data input of the latch circuit 27, is latched by the judgment result latch pulse from the 1JIE circuit 19 at timing f, and is supplied to the AND circuit 2 via the inverter 39.
9 and directly to the other input of the AND circuit 31. In addition, in the first half of Figure 5, D
Since the signal level on the CL line 9 is low, the second latch circuit 27 latches this low level and outputs it, so the AND circuit 29 generates the transmittable signal e as shown in FIG. 5(f). Output. This transmittable signal e is supplied to the transmitting module 23, and from the transmitting module 23 as shown in FIG.
As shown in h), c+), and (j), clock, data, and period signals are outputted via a clock line 3, a data line 5, and a period line 7, respectively. When the data transmission is completed, a transmission end signal is outputted from the transmission module 23 as shown in FIG. 5 (k'), and this is sent to the timing υ control circuit as a clear signal shown in FIG. 19, the signal is supplied to the latch circuits 25 and 27, and each part is cleared.

Next, as shown in the second half of FIG. 5, a case where the second device 1B is transmitting and the signal level on the DCL line 9 is high level will be described.

As shown in the latter half of FIG. 5(a) to (C), the transmission module 23 outputs a transmission request signal @a, and in response, the timing control circuit 19 outputs a transmission request signal @a, and furthermore, the timing control circuit 19 outputs a transmission request signal @a. When the control circuit 19 outputs the judgment result latch pulse C, the input buffer 717
In response to the high level signal on the CL line 9, as shown in FIG.
A high level signal is supplied to the second wrap circuit 27 as shown in FIG.

As a result, the second latch circuit 27 outputs a high level signal, this high level signal is supplied to the AND circuit 31, and the AND circuit 31 outputs a transmission disable signal f as shown in FIG. 5(0). Ru.

When the AND circuit 31 outputs the transmission impossible signal, this signal passes through the delay circuit 33 and the NAND circuit 35 to clear each part as a clear signal shown in FIG. After being delayed, it is supplied to the timing control circuit 19 via the OR circuit 21 as a retransmission signal shown in FIG. 5 (layer).In this case, the second device 1B has already finished transmission, D.C.L.
When the signal level on line 9 is low, the transmission operation is performed in the same manner as in the first half of FIG.

FIG. 6 is a circuit diagram when a plurality of data lines 5 between the two devices are connected in parallel so that parallel communication can be performed between the first device 1A and the second device 1B.

[Effects of the Invention] As explained above, according to the present invention, each g! The weapons are connected by a monitoring line, and when each device is in a reception standby state, a first signal level of 1 level is supplied on the monitoring line, and when each device is about to transmit, a second signal level is supplied on the monitoring line. At the same time, the signal status on the monitoring line is monitored, and when the signal status is at the first signal level, it is determined that transmission is possible and transmission is performed, and when the signal status is at the second signal level, it is determined that transmission is not possible. Since the reception timing is fixed, it is possible to communicate efficiently and in real time without the need for polling as in conventional methods.In addition, the clock can be selected on the transmitting side and is independent from the mask clock. can be operated.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the overall structure of a two-way communication system according to an embodiment of the present invention, and FIG. 2 is a waveform diagram of clock, data, and period signals used in the two-way communication system of FIG. Figure 3 is a circuit diagram of the bus interface in the two-way communication system shown in Figure 1, Figure 4 is a detailed circuit diagram of the two-way communication system shown in Figure 1, and Figure 5 shows the operating waveforms of the circuit in Figure 4. 6 is a circuit diagram of a bus interface in the case of parallel communication, and FIG. 7 is a configuration diagram of a conventional bidirectional communication system. 1A...First device, 1B...Second device, 3...Clock line, 5...Data line, 7...Period line, 9...DCL line, 15... Output buffer? , 17... Input buffer 7. 19...One circuit at timing 1I111, 23...
Transmission module, 29.31...AND circuit.

Claims (1)

[Claims] It is a two-way communication method that performs two-way communication between multiple devices, and it uses a data line that connects each device to transmit data bidirectionally between each device, and the status of the other device to which data is transmitted. a monitoring line connecting each device to be monitored; and a standby state provided in each device to supply a first signal level on the monitoring line to indicate the state when each device is in a reception standby state. a display means, a transmission state display means provided in each device and supplying a second signal level to the monitoring line to display the transmission state when each device attempts to transmit; line state monitoring means for monitoring the signal state on the monitoring line, and when the signal state on the monitoring line monitored by the line state monitoring means is at a first signal level, transmission is possible. 1. A two-way communication system, comprising: a transmission control means that performs transmission by determining that the signal is at a second signal level, and returns to a reception standby state as being unable to transmit when the signal is at a second signal level.