JPH02226726A - Manufacture of mos type semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To manufacture high and low concentration regions simultaneously by one time ion-implantation by a method wherein a gate in inverse T type sectional shape as well as in dimension smaller than the opening in a mask film by the film thickness of a gate material on one side, accordingly, two times smaller than the gate material is manufactured. CONSTITUTION:An opening 16 made in a mask film 14 is filled with a gate material 20 so as to form a gate material layer 20; further a coated film 22 in a pattern dimension smaller by the film thickness of the gate material 20 on one side only; and then the gate material 20 is etched away to form a gate 24 in inverse T type sectional shape using the gate material as a mask. Accordingly, a MOS transistor in LDD structure having a gate 24 smaller than the size of the opening 16 by the film thickness of the gate material 20 in one side can be manufactured. Furthermore, a high concentration region 34 and a low concentration region 32 can be formed simultaneously by one time ion- implantation using the stepped part of the gate 24 in inverse type sectional shape.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a method for manufacturing a MOS transistor (MOS) transistor, which has a so-called LDD structure (Lightly Doped [)rai] having a high concentration region and a low concentration region at the drain.
The present invention relates to a method of manufacturing a MOS transistor having the following characteristics.

[Conventional technology]

In order to improve the degree of integration of semiconductor integrated circuit devices, MOS
) When a transistor is made to have a short channel, the hot electron injection phenomenon becomes noticeable, causing a fluctuation in the threshold voltage. Therefore, as a way to suppress the generation of hot electrons by relaxing the electric field near the drain, an LDD structure is used in which the junction depth near the gate is shallow (and the impurity concentration is lower than that of the drain).
The DD structure weakens the electric field near the drain by making the drain a double structure with low impurity concentration and high impurity concentration, and expanding the drain depletion layer not only into the channel region but also into the low impurity concentration region. be.

A method for manufacturing a MOS transistor having the LDD411 structure is proposed in, for example, Japanese Patent Laid-Open No. 51-68776.

The manufacturing method described in this publication involves forming a gate, forming a low concentration region in a region aligned with the gate, forming a silicon oxide film as an insulating film over the entire surface, and then performing anisotropic ion etching to form the gate. A MOS with an LDD structure is created by forming a sidewall film made of a silicon oxide film on the side surface and then forming a high concentration region using this sidewall film.
It forms a transistor.

However, in the manufacturing method described in the above publication, a sidewall film made of an insulating film is formed on the side surface of the gate, and a low concentration region is formed directly under this sidewall film. Therefore, there is a problem that no gate voltage is applied to the low concentration region, and this low concentration region becomes a resistance, resulting in a small drain current (MOS) and a deterioration of the transistor characteristics.

Therefore, in order to solve this problem, for example, the International Electron Device Meeting 19
An inverted T-shaped gate in which a part of the gate extends over a low concentration region via a gate insulating film was proposed, as described in 1986, p. 742-745. The method for manufacturing the inverted T-shaped gate described in this document will be explained with reference to FIG.

FIGS. 5(a) to 5(d) are cross-sectional views showing, in order of steps, a method of manufacturing a conventional LDD structure MOS transistor having an inverted T-shaped gate.

First, as shown in FIG. 5(a), a gate material 20 and a silicon oxide film 50 are sequentially formed on a semiconductor substrate 12, and the silicon oxide film 50 is etched by photoetching. Further, the gate material 20 outside the gate formation region is etched so that a film thickness of 5 Q nm to 1100 nm remains, thereby forming a stepped portion 26 in the gate material 20. Thereafter, an impurity of a conductivity type opposite to that of the semiconductor substrate 12 is introduced into the semiconductor substrate 12 to form a low concentration region 62.

Next, as shown in FIG. 5(b), a silicon oxide film 50 is formed on the entire surface, and this silicon oxide film 50 is etched by anisotropic ion etching to form a gate material 200.
A sidewall film 44 made of a silicon oxide film 50 is formed on the stepped portion 26 .

Next, as shown in FIG. 5C, the gate material 20 is etched using the silicon oxide film 50 on the gate material 20 as an etching mask to form a gate 24 having an inverted T-shaped cross section.

Next, as shown in FIG. 5 (d3), the gate 24 and the sidewall film 4 are
A high concentration region 62 is formed in the semiconductor substrate 12 in a region aligned with 4.
A MOS transistor having a low concentration region 32 and a high concentration region 64 in the source 28 and drain 30 is obtained.

[Problem to be solved by the invention]

In conventional gates, a photosensitive resin is formed on a gate material, exposed to light by an exposure device using a photomask, and then developed to pattern the photosensitive resin into a gate shape. Thereafter, using this patterned photosensitive resin as an etching mask, the gate material is etched by dry or wet etching to form a gate having a predetermined shape.

For this reason, a gate having a size exceeding the resolution limit of the photosensitive resin cannot be formed. For example, in patterning photosensitive resin using ultraviolet rays as the light source of an exposure device, 0.8μ
A photosensitive resin with a size of about m to 1.0 μm or less cannot be stably formed, and therefore a gate with a size smaller than this cannot be formed.

L D-D structure MO equipped with an inverted T-shaped gate of a size that solves the above problems and exceeds the resolution limit of photosensitive resin.
S) It is an object of the present invention to provide a method for forming a transistor.

[Means to solve the problem]

In order to achieve the above object, an LDD structure MOS transistor with an inverted T-shaped gate in the present invention is formed by the method described below.

(a) A step of forming a mask film over the entire surface of a semiconductor substrate having a first conductivity type and forming an opening in this mask film by photoetching, and forming a gate insulating film on the semiconductor substrate within this opening. A process of forming a gate material and a coating film with a substantially flat surface on the entire surface, a process of etching the coating film until the gate material is exposed, and a process of etching the gate material using the coating film as an etching mask to form a gate inside the opening. A low concentration is achieved by embedding the material and forming a gate with an inverted T-shaped cross section with a step on the side surface, removing the mask film, and introducing impurities of the second conductivity type into the semiconductor substrate using ion implantation. The method includes a step of forming a region and a high concentration region, and a step of forming an intermediate insulating film, forming a connection hole in the intermediate insulating film, and further forming a wiring.

(b) forming a mask film over the entire surface of the semiconductor substrate having the first conductivity type and forming an opening in the mask film by photo-etching; forming a gate insulating film on the semiconductor substrate 1 within the opening; A process of forming a gate material and a coating film with a substantially flat surface on the entire surface, a process of etching the coating film until the gate material is exposed, and a process of etching the gate material using the coating film as an etching mask to form a gate inside the opening.・A low concentration region is formed by embedding the material and forming a gate with an inverted T-shaped cross section with a step on the side surface, and by introducing impurities of the second conductivity type into the semiconductor substrate using ion implantation. step, removing the mask film, forming an insulating film over the entire surface, and anisotropic ion etching of this insulating film to form a sidewall film made of an insulating film on the side surface of the gate; and a second step using ion implantation. The method includes a step of introducing an impurity having a conductivity type into a semiconductor substrate to form a higher concentration region than K, and a step of forming an intermediate insulating film, forming a connection hole in the intermediate insulating film, and further forming wiring.

(c) forming a mask film over the entire surface of the semiconductor substrate having the first conductivity type and forming an opening in the mask film by photoetching; forming a gate insulating film on the semiconductor substrate within the opening; A process of forming a gate material and a coating film with a substantially flat surface on the entire surface, a process of etching the coating film until the gate material is exposed, and a process of etching the gate material using the coating film as an etching mask to form the inside of the opening. A low concentration region is formed by embedding gate material into the semiconductor substrate and forming a gate with an inverted T-shaped cross section with a step on the side surface, and by introducing impurities having a second conductivity type into the semiconductor substrate by ion implantation. a step of forming a planarizing film with a substantially flat surface over the entire surface; a step of embedding the planarizing film into the stepped portion of the gate by etching the planarizing film until the mask film is exposed; A step of forming a high concentration region by removing the film and introducing an impurity having a second conductivity type into the semiconductor substrate, forming an intermediate insulating film, forming connection holes in this intermediate insulating film, and further forming wiring. It has a process.

2) The mask film in (a), (b), or (c) is formed by forming a polycrystalline silicon film over the entire surface of the semiconductor substrate, forming an opening in this polycrystalline silicon film by photoetching, and then performing oxidation treatment. It is formed by converting a polycrystalline silicon film into a silicon oxide film.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings. N
An example of manufacturing a channel MOS transistor will be described below.

FIGS. 1(a) to 1(f) are cross-sectional views showing a method of manufacturing a MOS transistor having an LDD structure in the order of steps according to a first embodiment of the present invention.

First, as shown in Figure 1(a), the impurity concentration is 2
Silicon dioxide with a thickness of 400 nm is deposited on the entire surface of a P-type semiconductor substrate 12 having a low impurity concentration of about 10 atoms/61 d by chemical vapor deposition (hereinafter referred to as CVD method) using monosilane and oxygen as reaction gases. A mask film 14 made of a film is formed.

Thereafter, a photosensitive resin is applied to the entire surface of the mask film 14, exposed using a photomask, and developed (5) to form a patterned photosensitive resin (not shown). Thereafter, the mask film 14 is etched using the patterned photosensitive resin as an etching mask, and the openings 16 are etched.
form. Thereafter, the photosensitive resin used as an etching mask is removed in a mixed solution of sulfuric acid and hydrogen peroxide.

Next, as shown in FIG. 1(b), an oxidation treatment is performed to form a gate insulating film 18 made of a silicon dioxide film and having a thickness of 20 nm on the surface of the semiconductor substrate 12 within the opening 16. After that, a film with a thickness of 4
A gate material 20 made of a 00 nm polycrystalline silicon film is formed. Thereafter, polymethyl methacrylate is applied onto this gate material 20 to form a coating film 22 made of polymethyl methacrylate and having a substantially flat surface.

Next, as shown in FIG. 1C, the coating film 22 is etched by anisotropic ion etching using oxygen as a reactive gas until a portion of the gate material 20 is exposed. By this etching, a coating film 22 having a pattern size smaller than the pattern size of the opening 16 is formed so as to be embedded in the recessed portion of the gate material 20 on one side by the film thickness of the gate material 20.

Next, as shown in FIG. 1(d), the gate material 20 is etched by anisotropic ion etching using sulfur hexafluoride as a reactive gas, using the coating film 22 formed in the recessed portion of the gate material 2o as an etching mask. do. By this etching, the gate material 20 is embedded in the opening 16, and a gate 24 having an inverted T-shaped cross section and having a stepped portion 26 on the side surface is formed.
form.

Of the gates 24 embedded in the opening 16 at this time,
The area not covered with the coating film 22 has a film thickness of approximately 1100 nm.
Etching is controlled so that it remains.

Next, as shown in FIG. 1(e), the coating film 22 and mask film 14 are removed. Thereafter, phosphorus having a conductivity type opposite to that of the semiconductor substrate 12 is heated at an acceleration energy of 100 k, for example.
ev, ion implantation amount: 4×10”1 ons/(I) The ions are introduced into the semiconductor substrate 12 by the ion implantation method under the conditions of i.

As a result of this ion implantation, in the region not covered by the gate 24, a high concentration region 64 with a deep junction depth (and high impurity concentration) is formed by phosphorus ions. Immediately below the step portion 26 which is thin (and has a low junction depth), when phosphorus ions penetrate the gate 24 and the gate insulating film 18, part of its energy is not lost, and the junction depth is shallower (and has a lower impurity concentration) than the high concentration region 64. low concentration region 62 where
is formed. Note that the channel region directly under the thick region of the gate 24 is blocked from penetrating phosphorus ions.
No phosphorus ions are introduced. By this one-time ion implantation, a low concentration region 62 and a high concentration region 64 are simultaneously formed in the source 28 and the drain 60.

Next, as shown in FIG. 1(f), an intermediate insulating film 36 made of a silicon dioxide film doped with phosphorus is formed by the CVD method. After that, in a nitrogen atmosphere at a temperature of 950 degrees Celsius for 3 hours.
Heat treatment is performed for 0 minutes. Thereafter, a connection hole 38 is formed in the intermediate insulating film 36 by photoetching. Thereafter, a wiring material made of an aluminum silicon alloy is formed by sputtering, and a wiring 40 is formed by photoetching.
A MOS) transistor with a D structure is obtained.

In the first embodiment of the present invention described with reference to FIG. A coating film 22 having a pattern size reduced on one side by the film thickness is formed, and the gate material 20 is etched using this coating film 22 as an etching mask to form a gate 24 having an inverted T-shaped cross section. . Therefore, a MOS transistor is obtained which has a gate 24 that is smaller on one side by the thickness of the gate material 20 than the size of the opening 160 of the mask film 14 and has an LDD structure.

Further, by using the stepped portion 26 of the gate 240 having an inverted T-shaped cross section, it is possible to simultaneously form the high concentration region 64 and the low concentration region 32 by one ion implantation.

Next, the second embodiment of the present invention is shown in FIGS. 2(a) and (
This will be explained using bl.

Similar to the method explained using FIGS. 1(a) to (d),
An inverted T with a stepped portion 26 inside the opening 16 of the mask film 14
A letter-shaped gate 24 is formed so as to be embedded therein.

Thereafter, as shown in FIG. 2(a), the coating film 22 on the gate 24 is removed, and phosphorus having a conductivity type opposite to that of the semiconductor substrate 12 is implanted, for example, at an acceleration energy of 110 keys and an ion implantation amount of 2×10 tons/ The ions are introduced into the semiconductor substrate 12 by ion implantation under the conditions d. By this ion implantation, a low concentration region 32 is formed in the semiconductor substrate 12 directly under the step portion 26 where the gate 24 has a thin film thickness.

Next, as shown in FIG. 2(b), the mask film 14 is removed and a silicon dioxide film with a thickness of 4QQnm is formed as an insulating film 42 by the CVD method. After that, the insulating film 42 is etched by anisotropic ion etching using the reaction residue of trifluoromethane and hexafluoroethylene, and the gate 2 is etched.
A sidewall film 44 made of an insulating film 42 is formed on the 40-step portion 26 . The region at the end of the gate 24 has a small difference in level from the semiconductor substrate 12. Therefore, the area at the end of this gate 24 is
Most of the insulating film 42 is removed by anisotropic ion etching. Thereafter, arsenic having a conductivity type opposite to that of the semiconductor substrate 12 is heated at an acceleration energy of 50 keV, for example.
, ions are introduced into the semiconductor substrate 12 by an ion implantation method under conditions of an ion implantation amount of 4×10 xons/d to form a high concentration region 64.

Thereafter, a method similar to that described using FIG. 1 (0) is performed to obtain a MOS transistor having a gate having an inverted T-shaped cross section and an LDD structure.

Next, the third embodiment of the present invention is shown in FIGS. 3(a) and (
This will be explained using b).

Similar to the method explained using FIGS. 1(a) to (d),
An inverted T with a stepped portion 26 inside the opening 16 of the mask film 14
A letter-shaped gate 24 is formed so as to be buried therein.

Thereafter, as shown in FIG. 3(a), the coating film 22 on the gate 24 is removed, and phosphorus having a conductivity type opposite to that of the semiconductor substrate 12 is implanted, for example, at an acceleration energy of 110 keys and an ion implantation amount of 2Xl. The ions are introduced into the semiconductor substrate 12 by ion implantation under the conditions of (l tons/(yl). By this ion implantation, a low concentration region 62 is formed in the semiconductor substrate 12 directly under the step portion 26 where the film thickness of the gate 24 is thin. Thereafter, polymethyl methacrylate is applied to the entire surface to form a flattening film 46 made of polymethyl methacrylate and having a substantially flat surface.

Next, as shown in FIG. 3(b), the planarizing film 46 is etched by anisotropic ion etching using oxygen as a reaction gas until the mask film 14 is exposed.

By this anisotropic ion etching, in the groove formed by the mask film 14 and the step portion 26 of the gate 240,
A flattening film 46 is formed. After that, the mask film 14 is removed, and arsenic having a conductivity type opposite to that of the semiconductor substrate 12 is removed.
For example, acceleration energy 50 keV ion implantation amount 4XI
A high concentration region 64 is formed by introducing into the semiconductor substrate 12 by ion implantation under the condition of O''1 ons/cyt.

Thereafter, a method similar to that described using FIG. 1(f) is performed to obtain a MOS transistor having a gate having an inverted T-shaped cross section and an LDD structure.

In the second and third embodiments of the present invention described using FIGS. 2 and 3, similarly to the first embodiment, the gate material 20 is removed on one side due to the size of the opening 160 of the mask film 14. A gate 24 is obtained which is reduced by the film thickness. Furthermore, in the second and third embodiments, the high concentration region 64 and the low concentration region 62 are formed under different ion implantation conditions. Therefore, it becomes possible to form the high concentration region 64 and the low concentration region 32 under optimal conditions. Therefore, a ``highly doped region 64'' and a ``lowly doped region 62'' having a shallow junction depth are obtained, and a short channel MOS
) It is also fully compatible with transistors.

The fourth embodiment of the present invention is shown in FIGS. 4(a) and 4(b).
Explain using.

First, as shown in FIG. 4(a), a polycrystalline silicon film 48 with a thickness of 200 nm is formed over the entire surface of the semiconductor substrate 12. Thereafter, this polycrystalline silicon film 48 is etched by photoetching to form an opening 16.

Thereafter, as shown in FIG. 4(b), the polycrystalline silicon film 48 is subjected to oxidation treatment, for example, in a steam oxidation atmosphere at a temperature of 700 degrees Celsius for 1 hour and 120 minutes, and a mask film made of a silicon oxide film 50 is formed. Form 14. This oxidation treatment increases the volume of polycrystalline silicon@48, and the film thickness increases by 4.
A silicon oxide film 50 with a thickness of 0.00 nm is obtained. At the same time in the thickness direction, the side surface of the opening in the polycrystalline silicon film 48 is also oxidized.
A mask film 14 having openings reduced by 400 nm in increments of 0 nm is obtained. By this oxidation treatment, the surface of the semiconductor substrate 12 within the opening 16 of the mask film 14 is also oxidized, and the film thickness is 2. A silicon dioxide film of Q n m is formed. This silicon dioxide film can also be used as a gate insulating film.

From this point on, by performing the same steps as those described using FIGS. 1, 2, and 3, the LDD 11i with a gate having an inverted T-shaped cross section is created! A manufactured MOS transistor is obtained.

The mask film 1 according to the fourth embodiment explained using FIG.
4, the size of the gate 24 is 1.2.3.
A gate 24 having a size reduced by the thickness of the gate material 20 in the embodiment described above plus the volume increase when converting the polycrystalline silicon film 48 into the silicon oxide film 50 is obtained. Therefore, it is still possible to form a gate 24 having a very small dimension.

In the first to third embodiments described above, a silicon dioxide film is used as the mask film 14. However, if a material different from the gate material 20 is used, it can be used as the mask film 14. Furthermore, the coating film 22 and the flattening film 4
In addition to polymethyl methacrylate, other materials such as organic polymers, photosensitive resins, coated glass films, etc. that can be formed into a substantially flat surface can be used as the coated film 2.
2 and a flattening film 46.

〔Effect of the invention〕

As is clear from the above explanation, claims (11, (2),
(3) By performing the manufacturing method described above, a cross-sectional shape having a dimension reduced by the thickness of the gate material on one side from the opening of the mask film, that is, the gate has a dimension reduced by twice the thickness of the gate material. An inverted T-shaped gate is obtained. Therefore, a method for forming an LDD structure MOS transistor having a gate having a size exceeding the resolution limit of photosensitive resin can be obtained.

Furthermore, by carrying out the manufacturing method according to claim (4), each side is made to have a length equal to the thickness of the gate material plus the increase in volume when converting the polycrystalline silicon film into a silicon oxide film. , an inverted T-shaped gate is obtained with dimensions reduced from the opening of the mask film.

Further, by carrying out the manufacturing method according to claim (1), a high concentration region and a low concentration region can be simultaneously formed by one ion implantation.

Furthermore, in the manufacturing method described in claims (2) and (3), the high concentration region and the low concentration region are formed in separate steps. Therefore, the low concentration region and the high concentration region can be formed under optimal conditions, and the low concentration region and the high concentration region having shallow junctions can be obtained. Therefore, it is possible to obtain an LDD structure MOS transistor having an inverted T-shaped gate, which still has high performance characteristics.

[Brief explanation of the drawing]

FIGS. 1(a) to (f) are cross-sectional views showing the manufacturing method of a MOS type semiconductor integrated circuit device according to the first embodiment of the present invention in order of steps, and FIGS. 2(a) and (b) are 3(a) and 3(b) are cross-sectional views showing the manufacturing method of a MOS type semiconductor integrated circuit device in the order of steps in the second embodiment.
FIGS. 4(a) and 4(b) are cross-sectional views showing the method for manufacturing a MOS type semiconductor integrated circuit device in the fourth embodiment of the present invention in order of steps. Cross-sectional views shown in the order of steps, FIGS. 5(a) to 5(d)
) are cross-sectional views showing a conventional method of manufacturing an MQS type semiconductor integrated circuit device in order of steps. 14...Mask film, 16...Opening, 20...Gate material, 22...Coating film, 24...Gate, 62 ...Low concentration region, 64 ...High concentration region, 46 ... Flattening film, 48 ... Polycrystalline silicon film, 50 ...・Silicon oxide film. Figure 4

Claims (4)

[Claims] (1) A step of forming a mask film over the entire surface of a semiconductor substrate having a first conductivity type and forming an opening in the mask film by photoetching, and forming a gate insulating film on the semiconductor substrate within the opening. a step of forming a gate material and a coating film with a substantially flat surface on the entire surface; a step of etching the coating film until the gate material is exposed; and etching the gate material using the coating film as an etching mask. and burying the gate material in the opening to form a gate having an inverted T-shaped cross section with a stepped portion on the side surface, and removing the mask film and implanting an impurity having a second conductivity type into the opening by ion implantation. It is characterized by comprising a step of forming a low concentration region and a high concentration region by introducing it into a semiconductor substrate, and a step of forming an intermediate insulating film, forming connection holes in the intermediate insulating film, and further forming wiring. A method for manufacturing a MOS type semiconductor integrated circuit device. (2) Forming a mask film over the entire surface of a semiconductor substrate having a first conductivity type, forming an opening in the mask film by photoetching, and forming a gate insulating film on the semiconductor substrate within the opening. and further steps of forming a gate material and a coating film with a substantially flat surface on the entire surface, etching the coating film until the gate material is exposed, and etching the gate material using the coating film as an etching mask. burying the gate material in the opening to form a gate having an inverted T-shaped cross section with a stepped portion on the side surface; and introducing an impurity having a second conductivity type into the semiconductor substrate by ion implantation. a step of forming a low concentration region, removing the mask film, further forming an insulating film on the entire surface, and anisotropic ion etching of the insulating film to form a sidewall film made of the insulating film on the side surface of the gate. a step of forming a high concentration region by introducing an impurity having a second conductivity type into the semiconductor substrate by ion implantation, forming an intermediate insulating film and forming a connection hole in the intermediate insulating film; 1. A method for manufacturing a MOS semiconductor integrated circuit device, comprising the step of forming wiring. (3) Forming a mask film over the entire surface of a semiconductor substrate having a first conductivity type, forming an opening in the mask film by photoetching, and forming a gate insulating film on the semiconductor substrate within the opening. and further steps of forming a gate material and a coating film with a substantially flat surface on the entire surface, etching the coating film until the gate material is exposed, and etching the gate material using the coating film as an etching mask. burying the gate material in the opening to form a gate having an inverted T-shaped cross section with a stepped portion on the side surface; and introducing an impurity having a second conductivity type into the semiconductor substrate by ion implantation. A step of forming a low concentration region, a step of forming a planarization film having a substantially flat surface over the entire surface, and a step of etching the planarization film until the mask film is exposed, thereby applying the planarization to the stepped portion of the gate. a step of embedding a film, a step of removing the mask film and introducing an impurity having a second conductivity type into the semiconductor substrate to form a high concentration region, and forming an intermediate insulating film to the intermediate insulating film. 1. A method of manufacturing a MOS type semiconductor integrated circuit device, comprising the steps of forming a connection hole and further forming a wiring. (4) The mask film according to claim (1), (2), or (3) is obtained by forming a polycrystalline silicon film on the entire surface of a semiconductor substrate and forming an opening in the polycrystalline silicon film by photoetching. , and then converting the polycrystalline silicon film into a silicon oxide film by oxidation treatment.