JPH02226449A - Cache memory control system - Google Patents

Abstract

PURPOSE:To prevent that a write action into a main storage and the tag check of the other processor from unnecessarily being generated by switching a cache memory control from that of a write through system to that of a write back system when a write access request destination from a processor is not the shared area of the main storage. CONSTITUTION:An area which requires the coincidence of data between the cache memories 18-0 and 18-1 of respective processors 12-0 and 12-1 in a multi- processor system is not the whole area of the main storage 11 but only the shared area which is actually used in respective processors 12-0 and 12-1. When a discrimination means has discriminated that the write access request destination from the processors 12-0 and 12-1 is not the shared area of the main storage 11, a system is switched to the cache memory control by the write back system. Thus, the unnecessary write action into the main storage 11 and the tag check of the other processor can be prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention relates to a cache memory control method in a multiprocessor system.

(Prior Art) In a multiprocessor system using a cache memory control method in which a plurality of processors share a main memory, a write-through method is generally applied as cache memory control at the time of memory write. The reason why the write-through method is applied in a multiprocessor system is that it is easy to match data between the cache memory prepared for each processor and the main memory, as described below. That is, in the write-through method in a multiprocessor system, when there is a memory write request from a processor, data is written not only to the cache memory of this processor but also to the main memory. At the same time, each cache tag memory (for managing each cache memory) of other processors is checked, and if the contents of the same address (same block address) are stored in the cache memory of another processor, An operation is performed to invalidate the tag in the corresponding cache tag memory. As a result, it becomes possible to match data between the cache memory and main memory of each processor.

Now, in addition to the write-through method described above, a write-back method is known as a cache memory control method during memory write. This write-back method normally only writes to the cache memory of the processor that requested the memory write, so the processing is simpler and faster, but the data between the cache memory and main memory is There is no consensus. Therefore, it has not been adopted in multiprocessor systems in which the main memory is shared by a plurality of processors.

(Problems to be Solved by the Invention) As described above, in the conventional cache memory control method in a multiprocessor system, a write-through method is used to ensure data consistency between the cache memory and main memory of each processor. was applied. However, in the write-through method, when a memory write request is issued from a processor, a write operation to the main memory and a tag check for the cache tag memory of other processors are always required, which reduces system performance. There was the problem of inviting

Therefore, an object of the present invention is to improve system performance while ensuring data consistency between the cache memory and main memory of each processor in a multiprocessor system.

[Structure of the Invention] (Means for Solving the Problems) This invention provides a multiprocessor system using a cache memory control method in which a plurality of processors share a main memory, when a main memory access request is issued from the processor. A determination means is provided for determining whether the main memory area of the request destination is a shared area shared with other processors, and if the main memory access request is a write access request, the Doi tll The present invention is characterized in that the cache memory is controlled by a write-through method or a write-back method depending on the determination result of the separate means.

(Operation) In a multiprocessor system, the area in which it is necessary to match data between the cache memory of the valley processor and the main memory is not the entire area of the main memory, but is actually shared by each processor. If the determination means determines that the write access request from the processor is not the shared area of the main memory, the write-back cache is By switching to memory control,
It is now possible to prevent unnecessary write operations to the main memory and tag checks of other processors, which were unavoidable in the past. Note that if the destination of a write access request from a processor is a shared area of main memory, it is necessary to perform write-through cache memory control to ensure data consistency between each processor's cache memory and main memory. There is.

(Embodiment) FIG. 1 shows a block diagram of an embodiment of a multiprocessor system to which the present invention is applied. In the figure, 11 is a main memory, and +2-0.12-1 is a processor that shares the main memory I+. In this example 1
．． Processor +2-0.12-1 accesses main memory 11 using logical addresses. The area of the main memory 11 is mainly a program area, a processor 1
It is divided into a local data area specific to 2-0.12-1, and a shared area used by processors 12-0.12-1 for mutual data exchange, etc., and each area is divided into a page unit. managed. 13 is a memory bus for the main memory ti. This memory bus 13 is used for transferring address, data, read/write signals, etc., as well as a shared area access signal indicating whether or not a shared area of the main memory 11 is to be accessed. Note that it is also possible to use a system bus instead of the memory bus 13.

14-0.14-1 is a memory management unit for managing access to the main memory 11 of the processor 12-0.12-1. Memory management unit 14-0. 1
4-1 is a processor +2-0. Among the logical addresses output from 12-1, the address (logical address information) excluding the lower bits indicating the intra-page offset (displacement) is converted into physical address information (upper physical address excluding the intra-page offset) PA. It has a useless address translation table 15-0.15-1. The address conversion table 15-0.15-1 has entries in the number of stages that can be specified by the logical address information, and each entry is allocated a logical page area specified by the corresponding logical address information. Well-known information such as physical address information PA indicating the physical page area of No. 11 and main memory protection information P, and a shared flag SF (SF-1) indicating whether the physical page area belongs to a shared area or not.
(indicating a shared area) is registered.

Note that the description of the main memory protection information P will be omitted since it is not directly related to this invention.

1B-0 and 16-1 are cache blocks. Kya/Sh”: f o Tsuk16-0. 16-1ha,
The above tall (7) cache data memory in which a copy of a part is placed in blocks of a predetermined size, the address tag indicating the address area corresponding to each of the above blocks placed in this cache data memory, and the same tag are valid. a cache tag memory in which tag information including a valid bit indicating whether the
-0.12-1 A hit detector (none of which is shown) for detecting whether or not the data in the area of the main memory 11 that the 1-1 attempts to access exists in the cache data memory (i.e., hit/miss). have 17-0.17-
1 is a hit detection signal indicating a hit/miss from the cache block 18-0.degree. 18-1 (the hit detector therein). If! -0,fli-■ is a cache tag memory provided separately from the cache tag memory in the cache block +6-0.18-1, +9-0.1
9-1 indicates that when a write is performed (by write-through) to the above [11] at the time of a main memory access request from another processor, the data in that area is transferred to the cache block I.
Whether G-0, ie- exists in the cache data memory in the cache tag memory 17-0.17 specified by the predetermined field of the memory address (write address) on the memory bus 13 and the same address. The comparator that checks by comparing the address tag of the entry in -1, 20-0.20, is a match detection signal that indicates the comparison result of comparator +9-0.19-1.

21-0. 21-1 is a memory management unit 14-0.
Either the memory address (main memory address) output from 14-1 or the memory address (write address) on the memory bus 13 is stored in the cache block 16.
-0. A selector for selectively outputting to 16-1, 22-0.
22-1 is a memory management unit 14-0. Memory address output from 14-1 (main memory address) or memory address on memory bus 13 (write address)
cache tag memory ts-o, t
This is a selector that selectively outputs to st. 23-0.23
-1 is a cache control unit that controls cache memory control. This cache control unit 23-0.23-1 includes a memory bus 13, a memory management unit 14-0.14-1,
It is connected to the cache blocks te-o, te-t and the comparator 19-0.19-1, etc., and the control unit 2
3-0.23-1 includes a memory management unit 14-0.
Shared flag SF in the entry of address translation table 15-0.15-1 that is referenced during address translation in 14-1, hit detection signal from cache block 16-0.18-1 (hit detector within) 17-0. 17
-L and a coincidence detection signal 20-0.20-1 from a comparator 19-0.19-1, etc. are supplied.

Next, the operation of the configuration shown in FIG. 1 will be explained.

First, it is assumed that a main memory access request is generated in processor 12-0, and that processor 12-0 outputs a logical address indicating an access destination. This logical address is provided to memory management unit 14-0.

The memory management unit 14-0 receives the upper logical address (logical address information) from the processor 12-0.
Refers to the entry in the address translation table 15-0 specified by , and finds the physical address corresponding to the logical address based on the physical address information FA in the entry and the in-page offset of the logical address. That is, the memory management unit 14-0 converts the logical address from the processor 12-0 into a physical address. This physical address is supplied to one input of the selectors 21-0 and 22-0. The other inputs of the selectors 21-0 and 22-0 are supplied with addresses on (the address bus of) the memory bus 13.

In the normal state, the selector 21-0.22-0 selects the address output from the memory management unit 14-0. The address selected by the selector 21-0 is supplied to the cache block 16-0, and the address selected by the selector 22-0 is supplied to the cache block 16-0.
The address selected by 0 is provided to cache tag memory 18-O. In the cache block 16-0, the main memory 11 to which the address from the memory management unit 14-0 selected and output by the selector 21-0 belongs
Whether or not the data of the block exists in the cache data memory in the cache block 16-0 is checked using a well-known method, and a hit detection signal 17 indicating the result is detected.
-0 is supplied from (the hit detection circuit of) cache block 1G-0 to cache control unit 23-0. This cache control unit 23-0 has an address translation table 15-0 that is referenced when converting to the above-mentioned physical address.
The shared flag SF of the entry in 0 is memory management unit 1
Supplied from 4-0. Also, the cache control unit 23-0
The access type indicating whether the main memory access request from the processor 12-0 is a read access request or a write access request is also notified. The cache control unit 23-0 performs cache memory control according to the shared flag SF, access type, and the like. This cache memory control will be explained in detail below.

In the multiprocessor system of FIG. 1, the above tati
As described above, this area is mainly allocated to the program area, local data area, and shared area. Among these three types of areas, the program area and the local data area do not necessarily have to match the cache data memory of other processors. Such a case is called case a. On the other hand, the shared area is shared by each processor and used for data exchange, etc.
It is necessary to match data between the cache memories of each processor. Such a case is called case b. The cache memory control in this embodiment is based on the combination of the above cases (a/b) and the type of main memory access request from the processor (write access/read access). (called cache memory control) ■Case b
Case B and cache memory control during read access (referred to as type 2 cache memory control); Case b and cache memory control during write access (referred to as type 3 cache memory control) .

Therefore, the cache memory control of (1) to (4) will be explained in order.

■Type 1 cache memory control The cache control unit 23-0 controls the memory management unit 14-0 when a main memory access request is made from the processor 12-0.
When the shared H flag SF supplied from the shared H8fj area is "0", that is, when the main memory access request destination is not the shared H8fj area, write-back type cache memory control is applied.

First, if the hit detection signal 17-0 from the cache block 1G-0 (the hit detector therein) is "O", that is, the requested data in the tall is stored in the cache data memory of the cache block 1G-0. In the case of a non-existing cache miss (miss), the cache control unit 23-0 reads the data of the corresponding block from the main memory 11 via the memory bus 13, regardless of the access type, and caches the read block. block 1
A block read (copy) operation is performed to write to the cache data memory in 6-0. After this, cache control unit 2
3-0 transfers the data corresponding to the request destination from the read block written to the cache data memory in the cache block 16-0 from the processor 12-0 only when the main memory access request is a write access request. Rewrite to write data. At the time of the above block read, if the block of the cache data memory to which the read is to be read is white and has already been rewritten, the cache control unit 23-
0 writes the contents of the block to the original area of the main memory 11 (writes back). In addition, the cache control unit 23-
0 registers valid tag information in each corresponding entry of the cache tag memory 18-row and the cache tag memory in the cache block 16-0 when the above block read is performed.

Note that tag information registration in the cache tag memory 18-0 is unnecessary when the main memory access request destination is not a coexistence area as in this example, but here, the tag information registration in the cache tag memory 18-0 is unnecessary.
In order to simplify the control of the cache tag memory 18-0, the cache tag memory 18-0 is configured to perform the same processing as the cache tag memory in the cache block 16-0.

Next, when the hit detection signal l7-0 from the cache block 16-O is "1", that is, when the requested data in the main memory 11 is a cache hit existing in the cache data memory of the cache block 16-0, If the main memory access request is a write access request, the cache control unit 23-0 transfers the data corresponding to the request destination from the corresponding data block of the cache data memory in the cache block 16-0 from the processor 12-0. Rewrite to the write data. Note that if the main memory access request is a read access request, data corresponding to the request destination out of the relevant data block in the cache data memory is transferred to the processor 12-0, regardless of hits/misses.

■Type 2 cache memory control The cache control unit 23-0 controls the memory management unit 14-0 when a main memory access request is received from the processor 12-0.
If the shared flag SF supplied from the cache block 16- is "1", that is, the main memory access request destination is a shared area, and the request is a read access request, the cache block 16-
A block read operation is performed in response to the hit detection signal 17-0 from 〇. That is, if the hit detection signal 17-0 indicates a cache miss, the cache control unit 23-O reads the data of the corresponding block from the main memory 11 and stores the read block in the cache block 16-0.
Write to cache data memory in 0. The cache control unit 23-0 then controls the cache tag memory 18-0.
Then, valid tag information is registered in each corresponding entry of the cache tag memory in the cache block 16-0. It goes without saying that the data corresponding to the request destination among the corresponding data blocks in the cache data memory is transferred to the processor 120.

■Type 3 cache memory control The cache control unit 23-0 controls the memory management unit 14-0 at the time of a main memory access request from the processor 12-O.
If the shared flag SF supplied from the main memory access point is "1", that is, the main memory access target is a shared area and the request is a write access request, write-through type catch-memory control is applied.

However, the control at this time is divided into the following two types depending on the state of the hit detection signal 17-0 from the cache block 16-0, that is, whether it is a cache miss or a hit.

First, in the case of a cache miss, the cache control unit 23-0
reads the data of the Tomoe block from the main memory 11,
A block read operation is performed to write the read block to the cache data memory in cache block 16-0. Thereafter, the cache control unit 23-0 transfers the data corresponding to the request destination from among the read blocks written to the cache data memory in cache block 1 to 0 to the processor! Along with rewriting the write data from 2-0,
This write data is written to the area of the main memory 11 specified by the address from the memory management unit 14-0. This writing to the main memory 11 involves writing the address, write data, read/write signal indicating write access, etc. from the memory management unit 14-0 to the cache control unit 23-0.
This is done by outputting it onto the memory bus 13.

At this time, the cache control unit 23-0 also outputs a shared area access signal on the memory bus 13 indicating that the write destination is a shared area.

The shared area access signal sent onto the memory bus 13 from the cache control unit 23-0 provided corresponding to the processor 12-0 is transmitted to the cache control unit 23-0 provided corresponding to the other processor 12-1. I am guided by 1. This cache control unit 23-1 includes a cache control unit 23-1.
A read/write signal indicating a write access sent to the memory bus 13 from -0 is also led.

In this case, the cache control unit 23-1 determines that write-through cache memory control is being performed by another cache control unit 23-0, and selects the selector 23-1.
2-1 to the memory bus 13 side. Further, the cache control unit 23-1 switches the selector 21-1 to the memory bus 13 side immediately if the cache block 16-1 is not in operation, or waits for the end of the operation if it is in operation. As a result, the above +f is sent from the cache control unit 23-0.
The address sent onto the memory bus 13 for writing to 5.11 is selectively output to the cache block IG-1 by the selector 21-1, and to the cache tag memory 18-1 by the selector 22-1. .

Cache tag memory 18-1 is accessed with a predetermined field of the address from memory bus 13, thereby reading the address tag and valid bit in the corresponding entry in cache tag memory 18-1 to comparator 19-1. Comparison S 19-1 compares the address tag read from the cache tag memory 18-1 and the memory bus 1.
Compare the address from 3 with a predetermined field other than the above, and if both are equal and the valid bit is on (true)
Only in this case, that is, only if the data of the block to which the area of the main memory 11 written by the cache control unit 23-0 belongs exists in the cache data memory in the cache block 1G-1, a logical "1" match occurs. A detection signal 20-1 is output. Cache control unit 23-1
In response to the coincidence detection signal 20-1 of logic "1" indicating a hit, the cache tag memory 18-1 and the cache block te- are invalidated by turning off the valid bits of the relevant entry in the cache tag memory 18-1 and the cache block te-. Perform conversion processing. On the other hand, if the coincidence detection signal 20 is logic "0" indicating a miss, the operation of the cache control unit 23-1 ends at that point.

Next, in response to a write access request to the shared area from the processor 12-0, a hit detection signal 17-0 of logic "1" indicating a cache hit is output from the cache block 1B-0 (hit detector). I will explain about it. In this case, unlike in the case of a cache miss, the cache control unit 23-0 does not perform a block read operation, but immediately reads the data corresponding to is rewritten to the write data from the processor 12-0. The operation after this rewriting is the same as in the case of a cache miss described above.

In addition, in the above embodiment, a case was explained in which the implementation was performed on a multiprocessor system with two processors.
The present invention is equally applicable to multiprocessor systems having three or more processors.

[Effects of the Invention] As detailed above, according to the present invention, it is realized that data matching between cache data memories of each processor is not necessarily required in areas other than the shared area of the main memory in a multiprocessor system. Focusing on this, we determined whether the write access request destination from the processor was a shared area of the main memory or not, and if it was not a coexisting area, we switched from the write-through method to the write-back method of cache memory control. It is possible to prevent unnecessary write operations to the main memory and tag checks of other processors, which were unavoidable in the past, and improve system performance.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a multiprocessor system to which the present invention is applied. 11... Main memory, 12-0.12-1... Processor, 13... Memory bus, 14-0. 14-1...
-Memory management unit, 15-0.15-1...Address translation table, 1B-0, 16=1...Cache block, 19-0.19-1...Comparator, 21-
0.21-1.22-0. 22-1...Selector,
23-0. 23-1...Cache control unit, SF/
...Shared flag. Applicant's agent Patent attorney Takehiko Suzue

Claims (1)

[Claims] In a multiprocessor system in which a plurality of processors share a main memory and apply a cache memory control method, when a main memory access request is issued from the processor, the request destination main memory A determination means is provided for determining whether or not the area is a shared area shared with other processors, and when the main memory access request is a write access request, the determination means determines whether the request destination is the shared area. If it is determined that the request destination is not the shared area, the cache memory control is performed using a write-back method. Cache memory control method.