JPH02224276A - Non-defectiveness of improved gate silicon dioxide and method of realizing it - Google Patents

Abstract

PURPOSE: To avoid short-circuiting of a polysilicon and a singlecrystalline semiconductor material by a method wherein a fault-free sidewall layer covering a gate oxide and overlapping with an undercut region formed between a singlecrystalline semiconductor material and an insulator layer close to the gate oxide is provided. CONSTITUTION: An improved fault-free gate oxide structure 40 formed on a semiconductor substrate 32 having a singlecrystalline semiconductor material 36 overlapped with an insulator 34. Next, an undercut region 38 is formed between the singlecrystalline semiconductor material 36 and the insulator layer 34 close to the gate oxide 40. Next, a sidewall layer 44 is formed on the gate oxide 40 to be overlapped with the undercut region 38 so as to protect the singlecrystalline semiconductor material 36 from a polysilicon gate 48 to be provided layer. Through these procedures, the single crystalline semiconductor material 36 can be protected from the polysilicon gate 48 to be provided later not to be short-circuited with the polysilicon gate 48.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to semiconductor processes, and more particularly to improved silicon dioxide gate integrity.
) and its method.

Prior Art and Problems In the process of semiconductor devices on insulating (80T) substrates, a layer of silicon dioxide <5in2) is removed from the device mesa (single crystal silicon material) before forming the gate oxide and polysilicon gate. Removal is often necessary.

One typical method for removing silicon dioxide is hydrofluoric acid wet etching. Because the insulating layer of silicon dioxide separates the substrate from the single crystal silicon material, wet etching tends to also etch the insulating layer, undercutting the single crystal silicon and forming an undercut region. When gate oxide is formed by oxidizing the surface and sidewalls of single crystal silicon mesas in a high temperature oxidizing atmosphere, not enough silicon dioxide is formed in the lower corners of the mesas in the undercut regions. wax (
due to directionally dependent oxidation rates and/or stress effects).

If there is not enough silicon dioxide in the corners of the lower mesa, the single crystal silicon islands will not be well protected from subsequent polysilicon games.

When the polysilicon gate and single crystal silicon contact, under normal circuit operating conditions, an undesirable short circuit will result.

It is known that adding a very thick layer of sidewall oxide forms a very thick barrier so that the corners of the mesa are not removed or exposed by etching and prevents unwanted shorting. However, if it is desired to use a device thus formed in an environment such as sanitary, this method is unacceptable due to the increased sensitivity to ionizing radiation. Outside the atmosphere, radiation is more abundant than within Earth's atmosphere, and thicker sidewall oxides tend to absorb more radiation, which will damage the circuitry that is to be protected. Thus, improved integrity gate oxides are needed to prevent shorting between polysilicon and single crystal silicon in semiconductor devices.

SUMMARY OF THE INVENTION The present invention includes an improved integral sidewall oxide and a method that eliminates or significantly reduces the problems associated with conventional sidewall oxides. The present invention forms a nitride barrier and
Provides better protection from shorting between the polysilicon gate and the single crystal silicon device.

According to one aspect of the invention, l! An improved integral gate oxide structure is formed on a semiconductor substrate having a crystalline semiconductor material. An undercut region is intentionally formed between the single crystal semiconductor material and the insulating layer near the gate oxide. A nitride layer is formed over the gate oxide and overlies the undercut region to protect the single crystal semiconductor material from the subsequently provided polysilicon gate.

The monocrystalline silicon device is later applied to the polysilicon
It is a technical advantage of the present invention that the gate is protected from shorting.

For a better understanding of the invention and its advantages, reference should be made to the following detailed description in conjunction with the drawings.

Embodiment FIG. 1 shows a conventional semiconductor device, designated by reference number M 10. In FIG. Device 10 includes a semiconductor substrate 12, such as silicon. Silicon oxide or silicon dioxide (S t 02
) covers the substrate 72. Patterned circuit device mesa 1 that may include single crystal silicon
6 is on the insulating layer 14. Mesa 16 is surrounded by: an oxide layer 18 formed over mesa 16 and oxide sidewalls 20 formed around mesa 16 . Patterned over the R layer 14, oxide sidewalls 20, and oxide layer 18 is a polysilicon gate 22.

At the stage of the process in which device 10 is formed, mesa 16 is undercut by a hydrofluoric acid wet etch to form undercut region 24. Side M1 oxide 20 fills the perimeter of mesa 16 and part of the undercut @M24, but at the corners 26 of mesa 16 the oxide coverage is very thin. Tests have shown that convex surfaces grow less oxide due to stress. Therefore, there is not as much B (oxide) 1 between the polysilicon gate 22 and the mesa 16 as desired. If the oxide breaks down around corner 26 and undercut region 24, gate 22 will short circuit within mesa 16.

In FIG. 2, a cross-sectional view of a device formed in accordance with a preferred embodiment of the invention is shown at 30. A substrate 32, such as silicon, is covered with an insulating layer 34 comprising silicon dioxide. A mesa 36 containing single crystal silicon and appropriate active devices is patterned over the insulating layer 34. An undercut region 38 is formed in the process of apparatus 30. Bud oxide 40 and sidewall oxide 42 surround mesa 36.

An important feature of the present invention is the addition of an integral layer of nitride, such as silicon nitride (Si3N4), to sidewall oxide 42 to partially fill around and within undercut region 38. be. The solid layer forms nitride filaments 44 and provides further insulation to the thin oxide immediately adjacent corners 46 of mesa 36, thus preventing conventional oxide breakdown and polysilicon gate 48. prevent short circuit.

Figures 3a-3f illustrate the major steps necessary to form a preferred embodiment of the invention. In FIG. 3a, the substrate 32
An insulating layer 34 is formed thereon.

Insulating layer 34 is typically silicon oxide or silicon dioxide (Si
02), and the substrate 32 typically includes silicon.

Single crystal silicon 150 completely covers underlying insulating layer 34. A mask, indicated by reference numeral 52, is then provided to cover the desired active device areas to be formed in layer 50. The mask 52 includes, for example, an oxide layer 54, a silicon nitride (Si a N4) w156, a second oxide layer 58,
and patterned photoresist 60.

Plasma etching is used to etch the oxide/nitride/llide deposits 54, 56, 58 following the pattern of photoresist 60 to form the structure shown in FIG. 3a.

A silicon etch that is selective to silicon dioxide, such as a plasma etch using chlorine chemistry, is performed on the silicon layer 5 which is not covered by a mask 52.
All 0 parts are removed.

In FIG. 3b, silicon layer 50 is etched away leaving under mask 52 to form mesa 36. In FIG. Next 7
The otoresist 60 is removed to form the structure shown in Figure 3b. Polymer removal may be performed to remove any remaining polymer n1 products of the silicon etch.

In FIG. 3C, important steps of the invention are illustrated. Unlike the prior art, the present invention uses undercut removal to intentionally undercut mesa 36. Mesa 36 is undercut to form undercut region 38 using a dilute hydrofluoric acid wet etch for about two minutes.

As a result of undercut removal, oxide layer 58 is also removed, forming a structure as shown in Figure 3C. Sidewall oxide 42 is thermally grown on the sidewalls of mesa 36;
Mesa 36 is protected from subsequent hot phosphoric acid to remove pad nitride 56. The structure of FIG. 3d thus includes a substrate 32, an insulator 34, and a mesa 36 surrounded by pad oxide 54 and sidewall oxide 42.

A nitride layer 62 is then provided over the entire structure. For example, to ensure that nitride layer 62 also fills undercut region 38, nitride may be applied by chemical vapor deposition. An anisotropic plasma nitride etch is used to remove nitride 162 from side Illide 42 and except within undercut region 38 to form an integral layer or nitride filament 44. If pad oxide 54
If it is necessary to remove the pad oxide and implant ions to adjust the threshold voltage, it may be necessary to regrow another pad oxide in place of pad oxide 54.

Figure 3f is the final step in forming the device 30 shown. Pad oxide 54 (or replacement pad oxide)
is removed by wet etching and the gate oxide is grown. If desired, pad oxide 5
4 or replacement pad oxide can be used as the gate oxide.

A polysilicon gate 48 is deposited over the device, which may then be suitably doped, patterned, and etched. It is now possible to begin forming complete semiconductor circuit devices using any method.

A semiconductor device with an improved integrated gate oxide is thus formed. The possibility of a short between polysilicon gate 48 and single crystal silicon 50 of mesa 36 is
It was greatly reduced due to the addition of nitride filament 44. Nitride filament 44 fills around sidewall oxide 42 and undercut region 38 to provide greater protection between the single crystal silicon of mesa 36 and the polysilicon of gate 48 .

Although the invention has been described with respect to particular preferred embodiments thereof, it is intended that various changes and modifications may be made and included within the scope of the appended claims.

Building on the above description, the following items are further disclosed.

(1) In an improved integral gate oxide structure on a semiconductor substrate with a single crystal semiconductor material overlying an insulating layer, the improvement is: between the single crystal semiconductor material and the insulating layer immediately adjacent to the gate oxide. and includes an undercut region formed in the undercut to cover the gate oxide and to protect the single crystal semiconductor material from the subsequently applied polysilicon gate and to improve the integrity of the gate oxide. Improved integrated gate oxide structure including integral sidewall layers overlapping regions.

(2) In the improved structure described in paragraph (1), the integral layer comprises silicon nitride.

(3) The improved semiconductor device includes: a substrate having on its surface a layer of a single crystal semiconductor material that is used as a layer of an insulator, a mesa formed from the single crystal semiconductor material, and a layer between the mesa and the insulator layer. The undercut area formed between and the side surrounding the mesa! ! an oxide and also an integral layer formed around the sidewalls and in the undercut region to insulate the single crystal material and also form an improved semiconductor device. Semiconductor equipment.

(4) In the improved structure described in item (3), the integrated layer includes silicon nitride.

(5) A method for improving the integrity of a gate oxide, comprising: undercutting a single crystal semiconductor material to form an undercut region between the material and an insulator layer; and growing a side 1uWI oxide on the material. , and also forming an integrity layer overlying the sidewall oxide and overlying the undercut region to improve the integrity of the gate oxide.

(6) (In the improved structure described in paragraph 53, the undercutting step includes wet etching.

(7) In the improved structure described in paragraph (6), the wet etching step includes wet etching with hydrofluoric acid.

(8) (In the improved structure described in paragraph 53, the growth step includes thermal oxidation.

(9) In the improved structure described in paragraph (5), the step of forming an integrated layer comprises chemical vapor deposition of silicon nitride on the single crystal semiconductor material and the oxide; The method includes etching the nitride to form nitride filaments.

(10) In the improved structure described in paragraph (9), the etching step includes anisotropic plasma etching.

(11) An improved method in semiconductor processing includes providing a substrate having a layer of single crystal semiconductor material on its surface overlying a layer of insulator, masking said material, and separating the masked portions and the unmasked portions. etching the unmasked portions down to the insulator layer, forming an undercut region, removing the mask, growing a sidewall oxide around the material, and etching the unmasked portions down to the insulator layer;
forming an integral layer around M and in the undercut region, and forming a polysilicon gate over the integral layer and the single crystal material to form an improved semiconductor device. How to include.

(12) In the method described in (11), the masking step includes forming a first oxide layer on the material, forming a nitride layer on the second oxide, and forming a nitride layer on the material. A method comprising: forming a second oxide layer over the nitride layer; and patterning a photoresist over the second oxide layer.

(13) In the method described in (11), the etching step is a plasma etching process that utilizes the chemical properties of chlorine.
Including etching.

(14) In the method described in paragraph (11), forming the undercut region includes hydrofluoric acid wet etching.

(15) In the method described in item (11), the growth step includes thermal oxidation.

(16) In the method described in paragraph (11), the step of forming an intact layer comprises chemical vapor deposition of silicon nitride and anisotropic plasma etching of the nitride to form the sidewall. removing the nitride layer except around and within the undercut area.

(17) Semiconductor device 1 (30) with improved and intact gate oxide is formed. Silicon nitride (Si3N4
) A filament (44) is formed between the gate oxide (42) and the polysilicon gate (48). Prior to depositing the nitride layer (62), an undercut area (38) is formed.
), undercut removal is performed. An anisotropic plasma etch is then performed □ to remove all the nitride layers (62) except for the nitride filaments (44).
is removed. After appropriate device implantation, a polysilicon gate (48) is deposited to complete the formation of device (30).

[Brief explanation of the drawing]

FIG. 1 is a drawing showing a cross-sectional view of a semiconductor device according to a conventional technique. FIG. 2 is a drawing showing a cross-sectional view of a semiconductor device formed according to a preferred embodiment of the present invention. Figures 3a-3f are cross-sectional views illustrating step-by-step the formation of a semiconductor device in accordance with a preferred embodiment of the present invention. Explanation of main symbols 32: Semiconductor substrate 34: Absolute Rm 36: Mesa 48: Polysilicon gate 38 Two undercut regions 46: Corner: Sidewall oxide: Nitride filament: Mask: Photoresist 12° 14° 16° 22゜24゜26゜FIG, 3a

Claims (2)

[Claims] (1) In an improved integral gate oxide structure on a semiconductor substrate with a single crystal semiconductor material overlying an insulating layer, the improvement is: between the single crystal semiconductor material and the insulating layer immediately adjacent to the gate oxide. and includes an undercut region formed in the undercut to cover the gate oxide and to protect the single crystal semiconductor material from the subsequently applied polysilicon gate and to improve the integrity of the gate oxide. Improved integrated gate oxide structure including integral sidewall layers overlapping regions. (2) a method of improving gate oxide integrity, comprising: undercutting a single crystal semiconductor material to form an undercut region between the material and an insulating layer; and growing a sidewall oxide on the material; . A method comprising forming an integrity layer overlying the sidewall oxide and overlying the undercut region to improve gate oxide integrity.