JPH02222578A - Manufacture of mos field-effect transistor - Google Patents

Abstract

PURPOSE:To facilitate the manufacture of a MOSFET possessed of a gate very small in length by a method wherein a gate electrode and a gate insulating film are formed on an insulating film or the like, a side wall is provided, then a semiconductor film is formed on the upside, and then a source and a drain electrodes are formed on the sides of the side wall respectively thicker than the semiconductor film formed on the gate electrode. CONSTITUTION:A gate electrodes 3 and a gate insulating film are formed on an insulating substrate or a substrate 1 on which an insulating film has been formed, a side wall 7 is provided to both the ends of the gate electrode respectively, and a semiconductor film 8 is formed on the upside of the gate electrode 3. Then, a source electrode and a drain electrode 9 are formed on both the ends of the side wall 7 respectively thicker than the semiconductor film 8 formed on the gate electrode 3. For instance, the amorphous silicon 8 is made to adhere, arsenic is ion-implanted into the silicon 8, and then the amorphous silicon 8 is thermally treated to be monocrystallized. Then, the silicon 8 is flattened through a polishing method, a single crystal silicon 9 is formed on a region which is to serve as a source and a drain, an element isolating region 10 is formed, and an amorphous silicon 11 is made to adhere as thick as 50nm, which is thermally treated to be monocrystallized to form a channel region.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a MOS field effect transistor, particularly a method for manufacturing a 5OI (Silicon On Inductor).
) This relates to a method of manufacturing a MOS field effect transistor formed on a substrate.

[Conventional technology]

In recent VLSH, the gate length is 0.8. MOS type field effect transistors are used.

It is thought that further miniaturization will occur in the future, and it is necessary to establish a manufacturing technology for MOζ transistors having a channel length of O,t, or less. However, with miniaturization due to higher integration, the characteristics of MOS field effect transistors deteriorate due to two-dimensional effects such as bunch-through and short channel effects. On the other hand, in a MOS field effect transistor formed on an SOI substrate, a single crystal semiconductor thin film with an SOI film thickness of about 0.5 μm, which is easy to grow, has conventionally been used. However, for example, if the device size is 0. I.J.
When forming a MOS transistor of less than m, 0.5μ
When a thick SOX film is used, the characteristics of a MOS field effect transistor are degraded due to two-dimensional effects such as punch-through and short channel effects, just as when a bulk silicon substrate is used. However, in order to reduce such two-dimensional effects and substrate floating effects.

It has recently been reported that it is sufficient to make the 5OIWI thickness less than or equal to the maximum depletion layer thickness. For this reason, a method of forming a thin SOX film is to form a thick SOX film of about -0.5 degrees and then thin the film using various etching methods.

[Problem to be solved by the invention]

In a MOS field effect transistor with a fine gate length, the two-dimensional effect cannot be sufficiently suppressed unless the SOI film thickness in the gate region is less than the depletion layer width. The thickness of the SOI film must be approximately 50 nm or less, but it is not only difficult to form such a thin SOI film over a wide area using conventional beam annealing methods or solid phase growth methods. Thick SO currently being carried out
Even in methods of thinning the I film using various etching methods, it is extremely difficult in terms of uniformity and controllability. Also.

Since the film thickness of the source/drain regions is also extremely thin, it is expected that the source/drain resistance will increase. Furthermore, as processing becomes finer, it is necessary to improve the condition of the underlying material, such as its flatness. Furthermore, in order to take measures against hot electrons, it is sufficient to make the change in the electric field near the source/drain gentle, and for this purpose it is also necessary to create a concentration gradient in this region.

The purpose of the present invention is to solve the problems of the prior art.
An object of the present invention is to provide a method for manufacturing an OS type field effect transistor.

[Means to solve the problem]

In order to achieve the above object, 1. a method for manufacturing a MOS field effect transistor according to the present invention includes forming a gate electrode and a gate insulating film on an insulating substrate or a substrate on which an insulating film is formed; The method includes a step of providing a sidewall, a step of forming a semiconductor film on the upper surface of the gate electrode, and a step of forming source and drain electrodes on both ends of the sidewall to be thicker than the semiconductor film formed on the gate electrode. It is something that

[Effect]

In the present invention, in order to form an SOI device with a fine gate, the thickness of the SOI film must be 50 nm or less. If such a thin film is formed using conventional methods, the distance that a single crystal will grow will be several -
Therefore, it is difficult to monocrystallize the entire device formation region. Furthermore, as the gate length becomes shorter, it is not easy to process the gate, and the flatness of the underlying layer becomes particularly important. moreover.

At the same time as forming the thin SOI film, the gate must be formed using self-line. Therefore, first, the gate electrode and gate insulating film are formed on the insulating film, and after forming the sidewalls, silicon is deposited, and the source/drain regions are formed. Once formed, it automatically becomes a self-line structure. At this time, silicon is deposited thickly on the gate electrode, so ions are implanted into the source and drain at this point, and then planarization is performed to make it the same height as the upper end of the gate electrode. In this way, a concentration gradient can be automatically formed in the vicinity of the source/drain region. In this case, the source/drain region is made into a single crystal, and the region that becomes the channel is formed.
Next, a thin silicon film is deposited and made into a single crystal. At this time, the crystallization distance may be short because the length corresponds to the channel length, and even a thin SOI film can be grown sufficiently.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1(a) is a schematic sectional view showing an embodiment of the present invention.

In FIG. 1(a), after 1p of oxide film 2 is formed on a silicon substrate 1, a seed is provided on a part of the oxide film 2, 500 nm of polysilicon is deposited on the entire surface, and an oxide film of 0.4 μm is further deposited on the entire surface. Then, the polysilicon is melted using an electron beam based on the seed to form a single crystal.

3 is single crystal silicon. At this time, the conditions for electron beam annealing are an acceleration voltage of 15 kV and a beam current of 30 mA.
, scanning speed 120cs+/sea, substrate temperature 1000℃
Next, after removing the oxide film and nitride film, the oxide film 4 was thermally oxidized to a thickness of 7 nm on the single crystallized silicon 3 film, and a nitride film 5 was further deposited. These films were patterned to form the structure shown in FIG. 1(a). At this time, the seed is embedded with single crystal silicon 6 and an oxide film 7 is formed on the side surface of the single crystal silicon 3 using an etch-back method as shown in FIG. 1(b).
A side wall was installed. After placing the sample in an MBE apparatus, surface treatment was performed, and amorphous silicon 8 was deposited to form the structure shown in FIG. 1(c). At this time, after heat treatment was performed at 450° C. for 20 minutes in the same vacuum, arsenic ions were implanted.

Next, this sample was heat-treated at 600° C. for 10 hours in a nitrogen atmosphere to form amorphous silicon 8 into a single crystal. At this time, arsenic enters a certain depth from the surface by ion implantation, but it is hardly diffused by the first heat treatment, so the arsenic concentration is reduced by planarization using a polishing method. It gradually decreases towards As a result, a structure as shown in FIG. 1(d) was formed, and single-crystal silicon 9 was formed in regions to become sources and drains.

Next, oxidation is performed except for the source and drain regions.

An element isolation region 10 was formed. Thereafter, the nitride film 5 is removed, and the amorphous silicon 11 is deposited on the MB as shown in FIG. 1(e).
The film was deposited to a thickness of 50 nm using an E equipment, and heat treated at 600°C to form a single crystal, forming a channel region.
Next, an oxide film 12 was deposited to serve as a protective film.

In the above embodiments, the in-phase growth method was used as a method for forming the single crystal films of the source/drain and channel regions, but a beam annealing method or the like may also be used.

〔Effect of the invention〕

As explained above, according to the present invention, unlike the conventional manufacturing method of MO3 type field effect transistors, the thin SOI film in the channel region is formed using these regions as seeds after forming thick source and drain regions. Therefore, there is no need for the high-precision etching method or direct formation of a thin SOI film over a large area, which was necessary for conventional thin SOI film formation, and the growth distance of the thin SOI film is short, only a few microns. Tesumu,
Furthermore, as shown in the above embodiment, even when an I'lO5 type field effect transistor is formed in a thin SOI film in the channel region, the source and drain regions can be formed in a thick silicon film, so the resistance of the source and drain regions is Transistors can be manufactured without increasing the cost. Also.

The gate can also be formed using self-line, and the source and
The impurity concentration gradient near the drain region is also created at the same time as the ion implantation into the source and drain.

Further, it can be controlled by the thickness of the deposited silicon film and the energy and dose of ion implantation.

[Brief explanation of the drawing]

FIG. 1 (ω~(d) is a schematic cross-sectional view showing one embodiment of the present invention.

Claims (1)

[Claims] (1) Forming a gate electrode and a gate insulating film on an insulating substrate or a substrate on which an insulating film is formed, providing sidewalls at both ends of the gate electrode, and forming a semiconductor film on the upper surface of the gate electrode. and forming source and drain electrodes at both ends of the sidewalls to be thicker than a semiconductor film formed on the gate electrode.