JPH02218974A - Logic circuit of scan test system - Google Patents

Abstract

PURPOSE:To obtain a logic circuit which can be shifted by one scan line, by a construction wherein scan FFs of positive and negative edge operations are provided on the same scan line and first and second scannable shift registers constructed thereof are brought into cascade connection. CONSTITUTION:After a shift register is constructed of all scan FFs (SFF4 and SFF5) of negative edge operation, another shift register is constructed of all scan FFs (SFF1, SFF2 and SFF3) of positive operation and connected to the aforesaid register to form a circuit. As for the internal state of each scan FF, an operation of shifting one data by one basic clock input is maintained and no error occurs, although a shift of data quickens by half a period of a clock between the scan FFs 15 and 11. Therefore, set data of the scan FFs after input of five basic clocks are set as L, L, H, H and H in the sequence from the scan FF 11 to 15 in accordance with an input waveform respectively. According to this constitution, a logic circuit can be realized by the same scan line without any need to alter a package, or the like.

Description

Detailed Description of the Invention (Field of Industrial Application) The present invention provides two types of flip-flops on one scan line: a scan flip-flop that operates on the positive edge of a basic clock, and a scan flip-flop that operates on the negative edge of the basic clock. Concerning a scan test method that uses multiple types simultaneously.

(Prior Art) In recent years, as LSIs have become larger in scale, the number of man-hours required for development has become more and more substantial. In particular, as the proportion of testing man-hours has increased, logic circuit design using a scan test method has come to be performed as a means of reducing testing man-hours.

FIG. 3 shows a logic circuit using the conventional scan test method. In FIG. 3, 31 (SFF1),
32 (S F F2), 33 (S F F, ) are scan flip-flops with positive edge operation of the basic clock, 34 (S F F4), 35 (S F F
S) is a basic clock negative edge operation scan flip-flop, 36 is a combinational circuit, and NT is a switching signal input terminal.
1 to 35 (S F F1 to S F F,) are switching signal input terminals when used as a shift register and when used as a normal flip-flop, and when signal H is input, the shift register operates. , when a signal is input, normal flip-flop operation is performed. SET is the set signal input terminal, CL
K is a clock signal input terminal, 5CN1. ．． 5cNr, is the data input terminal of the scannable shift register, 5CN
O8, 5CNO, is the data output terminal of the scannable shift register, IDT engineering or IDTfi is the input signal terminal, ODT□ or ODT is the output signal terminal, ■ and ■
is a scan line.

FIG. 4 shows the positive edge operation scan flip-flops 31 to 33 (SFF, to SFF3) of FIG.
) shows the internal circuit. In Fig. 4, 41 is a selector, and when signal H is input from the control signal terminal (S L), data from data input terminal A is input, and when signal R is input, data from data input terminal B is input. Data is selected. 42 is a positive edge operation flip-flop with a SET signal terminal. DT is a data input terminal during shift register operation, D is a data input terminal during normal operation, and Q is a data output terminal. N.T., C.L.K.
, SET are the same as the corresponding symbols in FIG. In addition.

Negative edge operation scan flip-flop (S
F F4. The internal circuit of SFF, ) is such that the D-type flip-flop 42 in FIG. 4 is replaced with a flip-flop with a SET signal terminal that operates at the negative edge of a clock signal.

FIG. 5(A) is a schematic diagram of a shift register in which scan flip-flops of positive edge operation and scan flip-flops of negative edge operation are mixed on one scan line, and FIG. The waveforms of each part of A) are shown.

Figure 5 Nioite, 51 (S F F, ), 52 (S
FF,), 53 (S F F,) are scan flip-flops with positive edge operation;
F4) and 55 (SFF,) are negative edge operation scan flip-flops.

Next, the operation of the above conventional example will be explained. In FIG. 3, first, signal H is input from the SET terminal. As a result, scan flip-flops 31 (S F Fl) to 3
All 5 (S F F,) flip-flops are set to state H. Furthermore, a signal H is input from the switching signal input terminal NT, and each scan flip-flop 31 (S F
F□) ~35 (S F FM) is changed to shift register operation. The 0th order set signal input terminal SET is fixed at the signal level. In this state, the data input terminal 5CNI of the scannable shift register.

A signal for setting the scan flip-flop 33 (S F Fa) is input to the data input terminals 5CN1. of the scannable shift register. A signal X (indeterminate) is input to the input terminal, and one basic tarok is input from the clock terminal CLK.

As a result, the scan flip prop 31 (S F F
, ) has a scan flip-flop 33 (SFF,
) is set to the data input terminal 5CNI of the primary scannable shift register, and the signal X is set to the scan flip-flop 34 (SFF, ).
Input the signal to be set to the scan flip-flop 32 (SFF2) of □, and input the signal to be set to the scan flip-flop 35 (SFF,) to the data input terminal SCN2 of the scannable shift register. , one basic clock is input from the clock terminal CLK. As a result, the scan flip-flop 31 (S F Fl
) signal is sent to the scan flip-flop 32 (SFF
,) d, 34 (SFF4) signal is 35 (S F F,)
, and a new scan flip prop 31 (S
FF, ) 2 is set to 32 (SFF, ) 2, and 34 (S FF, ) 2 is set to 35 (S FF5). Then, again, the data input terminal 5CNI□ of the scannable shift register,
5CNI2, scan flip-flop 31 (S F
By inputting the signal to be set to the signal 34 (SFF4) to be set to the scan flip-flop 31 (SFF4) and inputting one basic clock from the clock terminal CLK,
Signals are set to all of F Fl) to 35 (S F Fs). In this state, a signal is input from the switching signal input terminal NT to each scan flip 70 knob 31 (
SFF Fl) ~35 (SFF,) is changed from shift register to normal operation.

Furthermore, input signal terminals IDT U or I of the combinational circuit
Set the input signal to DT, and input one tarok from the clock terminal CLK. This causes the circuit to work,
The operation result is scan flip-flop 31 (SFF
, ) to 35 (S F F, ) and are output to the output signal terminals ○DAT and 0DAT.

Here, the signal H is input again from the switching signal input terminal NT to return each scan flip-flop to the shift register operation, and furthermore, the data input terminals 5CNI, 5CN1 . Therefore, by sequentially inputting new data to be set to each scan flip-flop as described above, and inputting the basic clock from the clock terminal CLK, the new data is input to the flip-flop 31 (S
FF,) to 35 (SFF,). Along with this data setting, scan flip-flops 33 (S F F,), 32 (S F F, ),
The data after the circuit operation of 31 (SFF□) is the data output terminal 5CNO.

From, scan flip prop 35 (SFF,
).

The data after the circuit operation of 34 (SFF,) is output together with the data shift.

By being able to set and retrieve data from flip-flops in one circuit using scan lines in this way, it becomes possible to treat synchronous sequential circuits as combinational circuits, and combinations are also effective in combinational circuits. By combining automatic generation of fault test patterns using this method, it is possible to reduce the number of man-hours required for fault testing of logic circuits.

As mentioned above, for a logic circuit in which there is a scan flip-flop with positive edge operation and a scan flip-flop with negative edge operation of the basic clock,
When applying the scan test method, it was necessary to configure the circuit with two scan paths. If the above two types of scan flip-flops are mixed in one scan line and the scan shift register configuration shown in FIG.
Therefore, the input setting data of each flip-flop is not sent in a correct shift operation, and as a result, the intended data is not set in each flip-flop, making it impossible to perform a correct scan test. In other words, Fig. 5 (B
), the scan flip-flop 51 (S
F F engineering), 54 (SFF4), 52 (S F F,
) and 55 (S F F,) by one tarok input, 51 (S F F,) - 54 (S F F,), 5
2 (S F F2) - 55 (S F F,), and the scan flip-flop 51 (
The data sent to the scan flip-flop 54 (S F F4) is set to the scan flip-flop 54 (S F F4), and the data sent to the scan flip-flop 52 (S F F, ,)
As a result, in FIG. 5(B), the flip-flop 51 (S F F, ) ~
Although H, L, H, H, L signals should be set in 55 (S F F,), H, H,
The L, H, and H signals are set, and the correct shift operation is not performed.

(Problems to be Solved by the Invention) In the conventional scan test method logic circuit described above, when applying the scan test method to a circuit in which flip-flops with positive edge operation and negative edge operation flip-flops of the basic clock are mixed, Two scan lines were required, and it was also necessary to provide an input terminal to each scan line and an output terminal from the scan line. Since the number of terminals for testing must be increased in this way, there are problems such as an increase in cost due to an increase in chip size and an inability to mount the device in the originally planned package due to the increase in the number of pins.

The present invention solves the above conventional problems, and aims to provide a scan test logic circuit in which the number of test terminals can be minimized and data shift operations can be performed correctly in one scan line. It is something.

(Means for Solving the Problems) In order to achieve the above object, the present invention has a positive edge operation scan flip-flop and a negative edge operation scan flip-flop operating on the same basic clock on the same scan line. , the scannable shift register constituting the scan line includes a first scannable shift register composed only of scan flip-flops of all first edge operations included on the scan line; The second scan pull shift register is constructed by cascading second scan pull shift registers, each of which is composed of only second edge operation scan flip-flops.

(Function) Therefore, according to the present invention, the number of test terminals in a circuit can be kept to a minimum, and a scan flip-flop with a positive edge operation and a scan flip-flop with a negative edge operation of the basic clock can be connected on one scan line. Even when scan flip-flops are mixed, the data shift operation is performed correctly, and the intended scan test can be performed correctly.

(Embodiment) FIG. 1 shows a scan test type logic circuit according to an embodiment of the present invention. In Figure 1, 1 (S F F
, ), 2(S F F,), 3(S F F,
), 4 (SFF, ), 5 (SFFs) are scan flip-flops, 6 is a combinational circuit, NT is a switching signal input terminal, SET is a set signal input terminal, CLK is a clock signal input terminal, IDT, or IDT, is an input The signal terminals 0DT1 to ODT are output signal terminals, and the above are the same as in the conventional example. 5CNI is a data input terminal when the flip-flop performs a shift register operation, and 5CNO is a data output terminal of the shift register.

FIG. 2(A) schematically shows the shift register section of FIG. 1 according to the embodiment of the present invention, and FIG. 2(B) shows the input waveform and internal state waveform of FIG. 2(A). This is what is shown. In Figure 2, 11 (S F F).

12 (S F F,), 13 (S F F,), 1
4 (SF F,), 15 (SF F,) are scan flip-flops, CLK is a clock signal input terminal, 5
CNI is a data input terminal, and SCN○ is a data output terminal, which correspond to the same symbols in FIG.

Next, the operation of the above embodiment will be explained. In the above embodiment, the basic operation of the scan test method, which treats a synchronous sequential circuit as a combinational circuit by setting and retrieving data of flip-flops in the circuit using scan lines, is the same as that described in the conventional technology. Since they are the same, the shift operation of the scannable shift register, which deserves special attention, will be mainly explained here.

When the basic clock waveform shown by CLK in FIG. 2(B) is used as the input clock, the circuit configuration of the scannable shift register is as shown in FIG. 2(A), with all negative edge operation scan flip-flops (S F F...
S F FS) After configuring the shift register, all positive edge operation scan flip-flops (
SFF1. SFF, , SFF, ) shift registers are connected. With the above circuit configuration,
As shown in FIG. 2(B), the internal state of each scan flip-flop (S F Fl to S F F,) is determined between scan flip-flop 15 (S F F,) and scan flip-flop 11 (SFF,). Although the shift of data by half a cycle of the clock is accelerated, the operation in which data is shifted by one by one basic clock input is maintained, and the error in the shift operation described in the conventional example does not occur. As a result, each scan flip-flop (S F F, or S F F,) after inputting the 5 basic clocks
The setting data is set to L, H, H, H in the order from the scan flip-flop 11 (S F Fl) to the scan flip-flop 15 (S F F,) according to the input waveform.

(Effects of the Invention) As is clear from the above embodiments, the present invention is capable of using a scan flip-flop with a positive edge operation of the basic clock and a scan flip-flop with a negative edge operation on the same scan line. This has the effect that a logic circuit can be realized without requiring an increase in cost due to an increase in chip size or a package change due to an increase in test pins.

[Brief explanation of the drawing]

1 is a scan test method logic circuit diagram of an embodiment of the present invention, FIG. 2(A) is a schematic diagram of a shift register of the scan test method logic circuit in the embodiment of FIG.
B) is a waveform diagram of each part of FIG. 2(A). Figure 3 is a conventional scan test method logic circuit diagram, Figure 4 is an internal circuit diagram of a scan flip-flop with positive edge operation of the basic clock, and Figure 5 (A) is a scan flip-flop with positive edge operation and negative edge operation. FIG. 5(B) is a schematic diagram of a shift register section when scan flip-flops are randomly mixed on one scan line, and FIG. 5(B) is a waveform diagram of each part in FIG. 5(A). 1, 2.3.11.12.13.31.32.33゜5
1, 52.53 (S F Fl, S F F,, S
F F3)...Scan flip-flop with positive edge operation, 4, 5, 14.15.34.3
5゜54, 55 (S F F4. S F F,)...
・Scan flip-flop with negative edge operation, 6, 36...Combination circuit, 41...Selector, 42...D-type flip-flop, NT...
Switching signal input terminal, SET...Set signal input terminal, CLK...Clock signal input terminal, 5CNI
. 5CNI□, 5CN1. ...Data input terminal, 5CN
O, 5CNO1, 5CNO2...data output terminal,
IDT1 to IDTゎ...input signal terminal, ○DT,
Or○DTa... Output signal terminal, DT...
Data input terminal during shift register, D: Data input terminal during normal operation, Q: Data output terminal, ■, ■
...Scan line. Patent applicant: Matsushita Electric Industrial Co., Ltd. (Figure (A) 1st)

Claims (1)

[Claims] A scan flip-flop of positive edge operation and a scan flip-flop of negative edge operation that operate with the same basic clock are provided on the same scan line, and a scannable shift register constituting the scan line is included on the scan line. first of all
a first scannable shift register composed of only edge-operated scan flip-flops; and a second scanable shift register composed only of all second edge-operated scan flip-flops included on the scan line. A scan test type logic circuit characterized by being configured with cascade connections.