JPH02218092A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To attain the high speed of equalization, etc. by equalizing a bit line, etc., according to a transit detecting pulse from write to read. CONSTITUTION:When the rise of a write enable signal, which indicates the transit from the write to the read, is detected a pulse signal phiEOW is generated from a phiEOW generating circuit 1, and a signal phiB is outputted from a bit line equalization/precharge control circuit 2. By this signal phiB, a p-channel transistor (TR) 21 of an equalizer is turned on, a pair of bit lines 12 and 13 are short-circuited, equalized, and the bit lines 12 and 13 are precharged through the p-channel TR 22, which is connected to a high power source. A common data line pair 14 and 15 are equalized and precharged through a common data line equalization/precharge control circuit 3 in the same way, when the write is shifted to the read, the bit line pair and the common data line pair are equalized and precharged at high speed, and the semiconductor memory is operated at high speed.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a semiconductor memory device in which information is written to and read from a plurality of memory cells, and particularly relates to an improved static RAM (SRAM). .

[Summary of the invention]

The present invention relates to a bit line pair connected to a memory cell.

In a semiconductor memory device that has a common data line pair and writes or reads data based on the potential difference between the via 1 line pair and the common data line pair, a transition from write to read is detected and the pulse generation circuit By generating a pulse and using that pulse to equalize and precharge the bit line and common data line,
[Conventional technology] - In one-conductor memory devices such as stateac RAMs, ICs, etc., a signal potential difference is applied to a pair of bit lines or a pair of common data lines. It is currently reading and writing data. However, in order to perform high-speed read and write operations, it is necessary to change the logic level quickly, so a pair of bit lines or a pair of common data lines with a signal potential difference are shorted together.
Techniques for equalizing (balancing) logic levels are known. Further, when a bit line having a logic level opposite to that of the cell is connected to a memory cell when selecting a row, the data in the memory cell may be inverted. Therefore,
A precharging technique is also known in which the bit line is temporarily raised to the power supply voltage side before row selection (word line selection) of the bit line.

Such equalization technology and precharge technology are normally performed during read or write operations, and the timing is determined by the address transition detection circuit that generates pulses due to address changes. (A
T D ; address Cransitior+
deteeLor). For example, according to JP-A-57-74884 or US Pat. No. 4,355,377, a change in address causes an address transition detection circuit to generate a pulse, which is sent to a clock generator. Then, a signal to control equalization and precharge is output from the clock generator, and this signal activates the equalization circuit and precharge circuit provided in the bit line pair, thereby speeding up the access time. There is.

[Problem to be solved by the invention] In recent technology, higher speed is required.
The speed of word line selection is also becoming faster.

However, when transitioning from a write operation to a read operation, the bit line and common data line are in a full swing state. For this reason, equalization and precharge require sufficient time, and it has become difficult to complete equalization and precharge operations before selecting the word line.

On the other hand, if the pulses from the address transition detection circuit can be generated faster, the equalization and precharge operations can be completed faster. However, as schematically shown in FIG. 5, the address transition detection circuit lO1 is a circuit that compiles data from each address manual section 100a to 100g, detects transitions of address data, and sends pulses to the clock generator 102. However, since each address manual section Iota-100g is scattered throughout the chimbu 103, it is not easy to detect data transitions at each address at high speed. The scale of the detection circuit 101 also becomes large, and it takes time to generate a pulse.

SUMMARY OF THE INVENTION In view of the above-mentioned technical problems, it is an object of the present invention to provide a semiconductor memory device that performs high-speed equalization and precharge operations when transitioning from a write operation to a read operation.

[Means to solve the problem]

In order to achieve the above object, the semiconductor memory device of the present invention includes a pulse generation circuit that detects a transition from write to read and generates a pulse, and uses the pulse to equalize or equalize the bit line or common data line. It is characterized by being precharged.

Here, a W (write enable) signal can be used as a signal for detecting ill transition from writing to reading, and in the semiconductor memory device of the present invention, the bit line and the common data line are only equalized, respectively. The configuration may include only precharge or both equalization and precharge.

Further, in detail, the semiconductor memory device of the present invention can have a structure having memory cells arranged in a matrix, and Sr! In AM, the memory cell circuit is formed by a flip-flop circuit, and the flip-flop circuit has at least a drive transistor and a word line connected to each other so as to connect input and output parts of a pair of inverter circuits to each other. a word transistor connected to
It has a load element consisting of a high resistance element or an active element. The plurality of memory cells are connected to a pair of node lines using their word transistors, and the bit line pair is connected to a common data line pair via a column selection switch. This common data line is connected to the sense amplifier, and the output from the sense amplifier is performed by the main data line. Similar to a normal semiconductor memory device, word line selection is performed by a row decoder, and bit line pair selection is performed by a column decoder.

In the semiconductor memory device of the present invention, the pulse signal from the pulse generating circuit is transmitted to the bit line equalize control circuit, the bit line precharge control circuit, or the common data line equalize control circuit or the common data line precharge control circuit. The signal is sent to the control circuit, and control signals for the equalization circuit and the precharge circuit are sent from each of these control circuits. Each control circuit can receive not only pulse signals from the pulse generation circuit but also signals from the address transition detection circuit.

Note that a load element that terminates the bit line can be formed on the bit line, and may be a variable resistance element, for example. Further, a bull-assist circuit or a pull-down circuit can be added to the common data line.

[Effect]

Instead of always starting a precharge operation or an equalization operation by an address transition, in the semiconductor memory device of the present invention, when transitioning from a write operation to a read operation, the WE multiplier signal containing the transition information is directly activated from which signal. A pulse is generated by a pulse generation circuit. Therefore, compared to the case where a circuit such as an address transition detection circuit that requires collection of address data is used, it is possible to speed up the so-called write recovery time.

〔Example〕

Preferred embodiments of the present invention will be described with reference to the drawings.

This embodiment is an SRAM having a CMO3 configuration, and has a configuration in which bit lines are equalized and precharged, and common data lines are equalized and precharged. The main circuit configuration is shown in FIG. 1. Memory cells 11 are arranged in a matrix, and each memory cell 11 is connected to a pair of bit lines 12 and 13. These bit lines 12 and 13 form a bit line pair, and a potential difference appears during reading and writing. Word lines X;, X;, +, . . . , which are arranged orthogonally to the bit lines 12, 13, are connected to the memory cell 11, respectively. These word lines Xi, Xi, .

. . . is set to a high level when a row is selected by a signal from a row decoder, and turns on a word transistor of a memory cell 11 (not shown).

The source or drain of a pMOS transistor 21 is connected to the pair of bit lines 12 and 13, respectively. This p
MOS transistor 21 constitutes a bit line equalization circuit and can short-circuit the pair of bit lines 12 and 13. p~(05 A signal ΦB from the bit line equalization precharge control circuit 2 is supplied to the gate of the transistor 21. Also, a pair of bit lines 12.
A pMOS transistor 22 constituting a bit line precharge circuit is provided between the high-level power source voltage and the high-level source voltage. , connect to 2.13. This p
Similarly to the pMOS transistor 2I, the signal ΦB from the bit line equalize/precharge control circuit 2 is also supplied to the gate of the MOS transistor 22.

Further, a bit line load transistor 31 is provided terminating the bit lines 12,13. The source of this bit line load transistor 31 is set to the power supply voltage, and the gate is set to the ground voltage GND. And a bit like this! 1il1
In 2.13, there is a pMO that functions as a length switch (column selection).
3l-transistors 111, 18 are provided. The bit line 12 is connected to the common data line 14 via a ρMOS transistor 18, and the bit, vA13, is connected to the common data line 15 via a PMOS transistor 18. Here, when paired, pMO3l- applied to throat line 12.13
The gate of transistor 18.18 has a common column selection IJW.
The lines Y,, Y1.1, . . . are connected to the column selection line Y+.

Y+-i, . . . are selectively brought to a high level by a signal from a column decoder (not shown) L7. The signal from the column decoder is based on the address signal, and is used together with the word lines X, , X, . . . each time a specific memory cell 11 is selected.

A pair of common data lines 14 and 15 are wiring lines for commonizing a specific number of each bit line pair and connecting them to the sense amplifier 16. A sense amplifier 16 that can amplify the signal potential difference between the common data lines 14 and 15 is provided at the end of the common data lines 14 and 15. A main data line 17 is taken out from the sense amplifier 16 for I10, and data is output using the main data line 17. The pair of common data 114 and 15 are connected to pMO3) transistors 32 and 32 which function as common data line loads. Furthermore, common data lines 14 and 15 each have p
The source or drain of MO3 transistor 23 is connected. This PMOS transistor 23 constitutes a common data line equalization circuit, and is connected to a pair of common data lines 14.1.
5 can be shorted. A signal ΦC from the common data line equalize/precharge control circuit 3 is supplied to the gate of the pMO5) transistor 23. In addition, between the pair of common data lines 1415 and the voltage B, pMO transistors 24 and 24 constituting a common data precharge circuit are provided, and PMOS
The source of the transistor 24 is connected to the power supply voltage, and the drain is connected to the common data line 14.15. The signal ΦC from the common data line equalize/precharge control circuit 3 is also supplied to the gate of this pMO3) transistor 24. Next, we will explain the circuit for operating the equalize circuit and precharge circuit. In the embodiment, the equalizing operation and precharging operation of the bit lines 12 and 13 are as follows:
1 by signal ΦB from bit line equalize/precharge control circuit 2, common data line 1
4. The equalize operation and precharge operation of J5 are performed by the signal ΦC from the common data line equalize/precharge control circuit 3. When the bit line equalize/precharge control circuit 2 and the common data line equalize/precharge control circuit 3 change from writing to reading,
The control operation is performed by the pulse signal ΦEQW from the ΦEQW generation circuit 1. Therefore, as will be explained next, high-speed equalization and precharging are performed when changing from writing to reading. In addition, each control circuit 2
．． 3 is a pulse signal ΦE from the Cronk generator 4 which is generated in response to a signal (ΦAO to Φ80) from an address transition detection circuit (not shown) during other address transitions.
Q performs the required control operation.

The ΦEQW generation circuit 1 will be explained with reference to FIGS. 2 and 3. As shown in FIG. 2, the ΦEQW generation circuit 1 generates a pulse (No. When the write enable signal WE is at a low level, the chip is in a write state, and conversely, when the write enable signal WE is at a high level, the chip is in a read state. , the rise of the signal WE is the time of transition from writing to reading, and by utilizing this timing, high-speed equalization and precharging can be performed.

To briefly explain the circuit, as shown in FIG.
The output of the R circuit 42 is converted to NA via an inverter circuit 43.
It is input to the NDl path 44. The output of the inverter circuit 43 is further composed of multiple stages of inverters! ! The signal is input to the same NAND circuit 44 via the extension circuit 45. The delay circuit 45 determines the pulse width of ΦEQW. NAND
The output of the circuit 44 is supplied as a pulse signal ΦE Q W to the L bit/t line equalize/precharge control circuit 2 and the common data line equalize/precharge control circuit 3 via the inverter circuit 46 . In this way, the ΦEQW generation circuit 1 generates pulses directly from the signal WE, and there is no need to organize address transitions in multiple stages, so the ΦEQW generation circuit 1 generates pulses directly from the signal WE, so it is possible to quickly generate pulses from each control circuit 2.
It is possible to send the pulse signal ΦEQW to 3, thereby making it possible to shorten the recovery time.

Next, while referring to FIG. 4 and FIG.
The operation of AM will be explained. At time 1°, the address signal (a) changes, and at the same time, the write enable (WE) changes.
) Signal (C) also changes from low level to high level. This change in the write enable signal causes the chip to change from a write operation to a read operation.

This write-even-pull signal is immediately applied to ΦEQ in Figure 1.
Time 1 after an extremely short time has elapsed after being sent to W generation circuit 1
A pulse signal ΦE Q W (ci) is generated at +. This is because the pulse signal ΦEQW is generated from the write enable signal by the ΦEQW generating circuit 1 with good responsiveness. The generated pulse signal ΦEQW is applied to the bit line equalize/precharge/control circuit 2 and the common data line equalize/precharge/control circuit 3.
The control signals ΦB and ΦC from these control circuits 2 and 3 perform the following operations: bit line equalization operation, bit line precharge operation 1, common data line equalization operation, and common data line precharge operation. will be held. That is, at the via line 12°+3, the 9MO5) transistor 21, which is the equalization circuit, is turned on, and the 9MO3 transistor 22, which is the precharge circuit, is turned on.
is turned on. As a result, the level (el) of the bit line pair, which was in full swing, changes as current flows from the high level bit line to the low level bit line due to equalization.
By turning on the pMOS transistor 22 for precharging, the voltage a″:4 is raised to an overwhelming level, and the potentials of the bit lines 12 and 13 become equal at time L2. The level becomes low level, and the equalize operation and precharge operation are completed.Similarly, the common data line 14.1
5, the pMOS transistor 23, which is an equalization circuit, is turned on, and the pMOS transistor 23, which is a precharge circuit, is turned on.
S transistor 24 is turned on. As a result, the level (f) of the common data line pair that was in full swing is changed by equalization, which causes current to flow from the high level common data line to the low level common data line, and the common data line becomes pMO.
3) After the resistor 24 pulls it up to the power supply voltage side, the potentials of the common data lines 111 and 15 become equal.

In this way, the bit lines 12 and 13 and the common data 114,
At +5, equalization and precharging operations are performed at high speed based on ΦEQW, and around the end of the equalization and precharging operations, the time [,
The '1st position (b) of the word line to be selected rises, and a row selection operation is performed. The selection operation of the word line turns on the word transistor of the memory cell ll in one column and row, activating the drive transistor, and bit)! +
A signal potential difference will appear in 2.1.3. Also,
The signal potential difference is p Ivi as a column selection switch.
Common data line 14 via OS l transistor 18
．． It will also appear on the 15th. Then, the sense amplifier 1G outputs data, and the data is read.

For comparison, we will also explain the operation based on the pulse signal ΦEQ based on the address transition detection circuit (signals indicated by broken lines in FIG. 11 (see F!5 to (+)). After the change, a delay occurs when using the address transition detection circuit, and the pulse signal ΦEQ ((to)
occurs. As a result, the level of the bit line (c) and the level of the common data (i) are also delayed compared to when using the ΦEQW pulse signal. [The levels of each line forming the bit line pair at I□ and the common data line pair at time cps become equal, but this is due to the pulse signal
There is a time difference of approximately ΔT on the bit line, and ΦEQV
,' It can be seen that the speed can be increased by generating the ΦEQW pulse from the pulse generating circuit 1 and performing the equalizing operation and the precharging operation.

In this way, in the SRAM of this embodiment, when changing from a write operation to a read operation, even though the bit line and the common data line are in full swing, the ΦEQW pulse generation circuit 1 generates ΦEQW from the write enable signal WE.
Since pulses are generated at high speed to perform equalization and precharge operations, high-speed access times can be achieved, and since word lines can be selected at high speed, data corruption in memory cells can also be prevented.

Note that in the above embodiment, the bit line and the common data line are equalized and precharged, but it is also possible to equalize and/or precharge only the bit line, or equalize and/or precharge only the common data line. It can be configured to pre-charge or a combination of these.

In addition, the precharge circuit and equalization circuit can be set to one pM.
Although it is composed of Os transistors, it is not limited to this and other transistors can also be combined. In order to adjust the impedance, the dark value voltage can be adjusted, adjusted, and supplied to the base, gate, and gate. It is also possible to make the signal bell/bell made of steel and adjust the element size. Further, it is also possible to use variable load means for the bit line load and the common data load.

(Effects of the Invention) In the semiconductor memory device of the present invention, a pulse is generated from the pulse generation circuit based on the transition from writing to reading, and
Equalization operation and precharge operation are performed by the pulse. Therefore, the so-called rewrite recovery time is shortened, and a high-speed word line selection operation becomes possible.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing the main circuit configuration of an example of the semiconductor memory device of the present invention, FIG. 2 is a waveform diagram showing the operation of the ΦE QW generation circuit of the above-mentioned example, and FIG. 3 is the ΦEQW generation circuit thereof. An example circuit diagram, FIG. 4 is a waveform diagram for explaining the operation of an example of the above-mentioned ゛R conductor memory device, and FIG. 5 is a schematic diagram for explaining the amplifier of the -C type semiconductor memory device. . 16...Sense amplifier 17...Main data lines 21.22, 23.24...PMO3l-ransistor Patent applicant Sony Corporation patent attorney Akira Kobu (and 2 others) Shi...Φmi QW Generation circuit 2...Bit line equalize/pre-chillage control circuit 3...Common data line equalize/precharge control circuit 4...Cronx generator ~ 11...Memory cell 12.13...Bit Line 14.15... Common data line Figure 5 Figure 4 Procedural amendment (voluntary) Commissioner of the Japan Patent Office November 16, 1999 1. Case description 1999 Patent application No. 39039 26 Title of the invention Semiconductor memory device 3, relationship with the amended person case Patent applicant address: 6-7-35, Kitashinyo, Tokyo Parts Store Name (2)
18) Sony Corporation Representative Norio Ohga 4, Agent Address 11, 2-6-4 Toranomon, Minato-ku, Tokyo 0105
Mori Building 11P1 Sho (508) 8266 “
Part 4 of "Detailed Description of the Invention", Drawing 7, Contents of Amendment (1) From page 4, line 18 of the specification to line 6 of the same page, the statement "The common data line is in full swing" has been changed to F common. The data line is corrected to almost full swing J. (2) rpMOs transistor], 8.18 is provided from line 1 to line 6 of page 11 of the specification. The via bit line 12 is connected to the common data line 14 via the run disk 18 (9MO3), and the bit line 13 is connected to the common data line 14 (9MO3).
It is connected to the common data line 15 via the transistor 18. The pair here is Pinot N, 9112. 13 Nikaru P
An MO5 transistor h and a rnMOs transistor 18.18 are provided. The bit line 12 is connected to the common data line 14 via an nMOS transistor 18,
The bit line 13 is connected to the common data line 5 via an nMO3 transistor 18. Here, the paired bit line 1
2.13 nMO5) transistor'. (3) The statement "J was in full swing" on page 16, line 19 of the specification is corrected to "J was in full swing. (4) Figure 1 of the attached drawings is as shown in the attached sheet. Correct. That's all.

Claims (4)

[Claims] (1) A semiconductor memory device characterized by having a pulse generation circuit that detects a transition from writing to reading and generates a pulse, and equalizes at least a bit line by the pulse. (2) A semiconductor memory device characterized by having a pulse generation circuit that detects a transition from writing to reading and generates a pulse, and precharging at least a bit line with the pulse. (3) A semiconductor memory device comprising a pulse generating circuit that detects a transition from writing to reading and generates a pulse, and equalizes at least a common data line by the pulse. (4) A semiconductor memory device comprising a pulse generation circuit that detects a transition from write to read and generates a pulse, and precharges at least a common data line with the pulse.