JPH02215121A - Protective structure for annealing treatment - Google Patents

Abstract

PURPOSE:To eliminate the inner stress in a compound semiconductor containing phosphorus during the annealing process in high temperature atmosphere thereby preventing the cracking in an insulating film from occurring by a method wherein a semiconductor crystal layer and an insulating film lattice matching with the said compound semiconductor are laminated on the surface of the compound semiconductor containing phosphorus. CONSTITUTION:An InP layer 5 is epitaxially formed on a semiconductor substrate 4' impurity ion is implanted (a) in the InP layer 5; a GaAl As layer 6 and an Si3N4 film 7 as annealing protective films are laminated. The impurity is annealed in N2 at 800 deg.C for 20 minutes to successively etch away the Si3N4 film 7 and te GaAlAs layer 6. In such a constitution, the inner stress of InP is eliminated during the annealing process so that the phosphorus may not be taken out of the layer 2 through cracks made in the insulating film 5.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a protective structure for annealing a compound semiconductor containing phosphorus (CP).

(Prior art) Ion implantation is a technique in which a target impurity element is ionized, further accelerated to an energy of 10 to several hundred keV, and then implanted into a semiconductor substrate, and the concentration of impurity is increased from 0.1 ppm to approximately 10%. In this ion implantation, high-energy ions collide with the solid, and the energy is much larger than the atomic conversion energy in solid crystals (14 eV in St).
Many lattice defects occur in the crystal. ~1015/c
In high-concentration ion implantation of about m2, the implanted region becomes almost completely amorphous. For this reason, it is essential to recover the crystallinity by heat treatment and at the same time to perform annealing to replace the implanted impurities with lattice points (LSI Handbook, Institute of Electronics and Communication Engineers 1984, p. 324-325).

Conventionally, as a method for annealing compound semiconductors containing arsenic (As) and P, there has been a method in which annealing treatment is performed in a nitrogen (N2) atmosphere. However, at high temperatures of 750 to 850° C., a dissociation phenomenon of As and P contained in the compound semiconductor occurred, and the anilization treatment actually deteriorated the crystal. Therefore, in GaAs crystals and GaInAs crystals, dissociation of As has been suppressed by using an annealing structure in which an insulating film such as silicon nitride is deposited on the surface before annealing treatment.

This insulating film is removed after annealing.

FIG. 3 shows a conventional annealing structure in which the above technique is applied to a compound semiconductor containing P.

An InP crystal growth layer 2 is formed on the upper surface of the semiconductor substrate 1 . Impurities have already been implanted into this InP crystal growth layer 2, and a silicon nitride film 3 is formed on its upper surface as an annealing protection film.

[Problem to be solved by the invention]

However, since the dissociation pressure of P is higher than that of As, the silicon nitride film 3 alone cannot prevent the dissociation of P.
Anneal protection was insufficient.

Therefore, there was a drawback that stress was generated when P was removed from the InP crystal growth layer 2, and the insulating film 3 was cracked.

Therefore, an object of the present invention is to eliminate internal stress in a compound semiconductor containing P during annealing treatment in a high-temperature atmosphere, and to prevent cracking of an insulating film.

[Means to solve the problem]

In order to achieve the above object, the present invention provides an annealing protection structure for a compound semiconductor containing phosphorus (CP), including a semiconductor crystal growth layer formed on the upper surface of the compound semiconductor and lattice matched with the compound semiconductor, and a semiconductor crystal growth layer on the semiconductor crystal growth layer. The structure includes a formed insulating film.

[Effect]

Since the present invention is configured as described above, P is dissociated from the compound semiconductor because the semiconductor crystal growth layer is interposed between the insulating film and the compound semiconductor together with the insulating film during annealing treatment in a high-temperature atmosphere. A suppressive pressure higher than the dissociation pressure acts.

〔Example〕

Hereinafter, a method for annealing a compound semiconductor according to an embodiment of the present invention will be described with reference to the accompanying drawings. In the description, the same elements are denoted by the same reference numerals, and redundant description will be omitted.

FIG. 1 is a longitudinal cross-sectional view showing a protective structure for compound semiconductor annealing treatment according to one embodiment. This protective structure for annealing treatment includes a compound semiconductor layer 5 formed on a semiconductor substrate 4, a semiconductor crystal growth layer 6 formed on its upper surface, and an insulating film 7 formed on its upper surface. There is. The compound semiconductor layer 5 is formed of a compound semiconductor containing P, such as InP, and has defects in its crystal due to ion implantation. The semiconductor crystal growth layer 6 is formed of, for example, a Ga InAs crystal layer that is lattice matched with the compound semiconductor layer 5 . The insulating film 7 is formed of, for example, a silicon nitride film.

FIG. 2 is a process diagram showing an annealing method using the above-mentioned annealing structure. First, a compound semiconductor layer 5 such as InP is formed on the upper surface of the semiconductor substrate 4 by metal-organic vapor phase epitaxial method (FIG. 2(a)), and an impurity element is implanted into this compound semiconductor layer 5 ( Figure (b)).

Next, as an annealing protective film, a semiconductor crystal growth layer 6 such as Ga 1 nAs is formed to a thickness of 0.1 to 0.2 μm (FIG. 2(c)), and an insulating layer 6 such as a silicon nitride film is formed. I
7 with a thickness of 1000 angstroms (see the same figure).
d)). At this stage, an annealed structure according to the present invention is formed. Note that if the semiconductor crystal growth layer 6 is sufficiently thin, ion implantation may be performed after forming the semiconductor crystal growth layer 6.

Next, an annealing process is performed to activate the impurities incorporated into the crystal by ion implantation. This annealing structure allows annealing in a N2 atmosphere at an annealing temperature of 800° C. and an annealing time of 20 minutes, for example. After the annealing treatment, the semiconductor crystal growth layer 6 and the insulating film 7 are removed by etching or the like (FIG. 4(e)). Ga
InAs can be wet-etched with a phosphoric acid etchant, and the silicon nitride film can be wet-etched with buffered hydrofluoric acid (BHF).

Note that the present invention is not limited to the above embodiments.

For example, In formed on a substrate as a semiconductor containing P
The explanation is based on a crystal growth layer of P, etc., but the substrate itself is InP.
It can also be applied to cases where it is formed of, etc.

Further, although InP is used as a semiconductor containing P, Ga1nAs is used as a lattice-matched semiconductor, and silicon nitride is used as an insulating film, the present invention is not limited to these semiconductors. For example, silicon oxide can be used as the insulating film.

〔Effect of the invention〕

Since this invention is configured as explained above,
In particular, in annealing in a high-temperature atmosphere, internal stress in the P-containing compound semiconductor can be eliminated and cracking of the insulating film can be prevented.

[Brief explanation of the drawing]

FIG. 1 is a vertical cross-sectional view showing a protective structure for compound semiconductor annealing according to an embodiment of the present invention, FIG. 2 is a process diagram showing an annealing method using the annealing structure shown in FIG. 1, and FIG. FIG. 2 is a vertical cross-sectional view showing a protection structure for annealing treatment of a compound semiconductor according to the prior art. 1.4... Semiconductor substrate, 2... 1nP crystal growth layer,
3... Silicon nitride film, 5... Compound semiconductor layer, 6...
... Semiconductor crystal growth layer, 7... Insulating film.

Claims (1)

[Scope of Claims] A protective structure for annealing a compound semiconductor containing phosphorus (P), comprising: a semiconductor crystal growth layer formed on the upper surface of the compound semiconductor and lattice matched with the compound semiconductor; and a semiconductor crystal growth layer on the semiconductor crystal growth layer. A protective structure for annealing treatment, which includes an insulating film formed on the annealing process.