JPH02214152A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To easily obtain a semiconductor device provided with a high- breakdown-strength and comparatively-high-capacity MIS capacitor and with a high-speed COMS FET by forming the following: an insulating film composed of a thermal oxide film and a nitride film for a high-breakdown-strength MIS capacitor; a gate oxide film for a CMOSFET. CONSTITUTION:A field oxide film 2 for element isolation use, a silicon thermal oxide film 3 and a silicon nitride film 4 are formed one after another on a silicon substrate 1; a region used to form a high-breakdown-strength MIS(metal insulator semiconductor) capacitor is masked with a resist 5; only the nitride film 5 used to form a CMOSFET is removed. The oxide film 3 in the region used to form the CMOSFET is removed by making use of the nitride film 4 in the region used to form the MIS capacitor as a mask; a gate oxide film 6 is formed. Thereby, it is possible to easily obtain a bipolar CMOS semiconductor device which is provided with the following: the MIS capacitor whose reliability against a high voltage is high and whose capacity is comparatively large; the CMOSFET which is operated by a low voltage at high speed.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention is a semiconductor device, in particular, a bipolar transistor having a relatively high collector-emitter breakdown voltage and an 0MO3FET having a relatively thin gate insulating film. The present invention relates to a semiconductor device and its manufacturing method.

[Conventional technology]

BACKGROUND ART Conventionally, a so-called digital/analog mixed type bipolar/CMOS semiconductor device is known in which an OMO3FET for a digital circuit and a bipolar transistor for an analog circuit are integrated on the same substrate. In such bipolar CMOS semiconductor devices, 0M capacitors are used as capacitors for analog circuits because the voltage dependence of the capacitance is smaller than that of PN junction capacitors.
M I S (m
etalinsulator semiconductor
or) capacitors are commonly used.

[Problem to be solved by the invention]

By the way, when a MIS capacitor is formed using the gate oxide film of an 0MO3FET in this way, no particular problem occurs when the operating voltages of the digital circuit and the analog circuit are the same. However, as a digital circuit, an 0MO3FET with a thin gate oxide film that is highly miniaturized and operates at a low voltage of 5.5 V or less, is fast, and has low power consumption is required, while as an analog circuit, a 0MO3FET that operates at a low voltage of 5.5 V or less is required. When a relatively high operating voltage is required, MTS using a thin gate oxide film of 0MO3FET is recommended.
When capacitors are used in analog circuits, the electric field increases, reducing the reliability of the device.

To address this issue, MIS capacitors and 0MO
In the process of forming the gate oxide film of the 3FET, a thermal oxide film of an appropriate thickness is formed, the oxide film is removed in the area where the 0MO3FET is to be formed by a normal photolithography process, and then a predetermined gate oxide film is formed on the area. One possible method is to form a According to this method, the oxide film of the MIS capacitor can be made thicker than the gate oxide film, so even if a relatively high operating voltage is used for the analog circuit, the reliability of the MIS capacitor does not deteriorate.

However, when formed using this method, MI
Not only does the capacitance of the S capacitor become smaller and the degree of integration decreases, but also the thermal oxide film formed at the beginning of the 0MO3FET
When removing the area, the silicon surface is exposed. At this time, the resist in the etching system contaminates the exposed silicon surface, resulting in a problem that the quality of the gate oxide film subsequently formed is degraded.

The present invention was made to solve the above-mentioned problems in conventional bipolar/CMOS semiconductor devices, and includes a high-speed 0MO3FET with a thin gate oxide film and a MIS capacitor for analog circuits with high withstand voltage and relatively large capacity. An object of the present invention is to provide a bipolar CMOS semiconductor device equipped with the above-mentioned semiconductor device, and a method for manufacturing the semiconductor device, which eliminates contamination from a resist during the formation of a gate oxide film of an OMO3FET in the manufacturing process.

[Means and effects for solving the problem] In order to solve the above problems, the present invention provides a method for coexisting a bipolar transistor with a relatively high collector-emitter breakdown voltage and an 0MO3FET with a relatively thin gate insulating film. In a semiconductor device manufactured by
A semiconductor device is constructed by providing a capacitor and an OMO3FET having a gate insulating film formed only of a silicon thermal oxide film.

With this configuration, the insulating film of the MIS capacitor is thicker than the gate insulating film, so the average electric field is relaxed when a high voltage is applied, and the nitride film has a higher dielectric constant than the oxide film. Therefore, a bipolar CMOS semiconductor device equipped with a MIS capacitor having a high breakdown voltage and a relatively large capacity and a high-speed OMO3FET can be obtained.

The present invention also provides a method for manufacturing a semiconductor device in which a bipolar transistor having a relatively high collector-emitter breakdown voltage and an OMO3FET having a relatively thin gate insulating film coexist, in which a silicon thermal oxide film and a silicon nitride film are formed on a semiconductor substrate. and a step of sequentially forming 0MO3FET.
After removing the silicon nitride film in the region where the 0MO3FET is to be formed, using the silicon nitride film in another region as a mask, selectively removing the silicon thermal oxide film in the region where the 0MO3FET is to be formed;
By selectively oxidizing the region where the T is to be formed and forming a gate insulating film, the insulating film of the MIS capacitor and the 0M
It forms the gate insulating film of O3FET.

By manufacturing in this way, the removal of the lower oxide film of the two-layer film before the formation of the gate insulating film and the subsequent step of forming the gate insulating film are performed using the nitride film as a mask, so the silicon surface is contaminated by the resist. This makes it possible to form an OMO3FET with a high quality gate insulating film.

(Example) Next, an example will be described. Figs. Only a part of it is shown.

First, as shown in FIG. 1, a field oxide film 2 for element isolation is formed on a silicon substrate 1.

At this time, although not shown, the silicon substrate 1 has already been filled with a buried diffusion layer of a bipolar element and an 0MO3FE layer.
It is assumed that necessary diffusion layers such as a T well diffusion layer have been formed. Next, as shown in Figure 1), a silicon thermal oxide film 3 with a thickness of 100 thick and a silicon nitride film 4 with a thickness of 300 thick are successively formed. Next, as shown in FIG. 1 (0), the region where the high breakdown voltage MIS capacitor is to be formed is masked with resist 5 using a normal photolithography process, and 0MO3
Only the nitride film 4 in the region where the FET is to be formed is removed, for example, by plasma etching.

Next, as shown in FIG. 1), after removing the resist 5, using the nitride film 4 in the MIS capacitor formation region as a mask, the oxide film 3 in the region where the 0MO3FET is to be formed is removed with dilute hydrofluoric acid, for example. . In this step of removing the oxide film 3, the silicon surface in the region where the 0MO3FET is to be formed is exposed, but since the resist 5 has already been removed at this time, the silicon surface is not contaminated by the resist.

Next, as shown in FIG. 1 [F], the gate oxide film 6 is
Form to a thickness of 50 people. At this time, the region where the high voltage MIS capacitor is to be formed is hardly oxidized because the nitride film 4 serves as a mask, and only a small amount of oxynitride is formed on the surface.

In this way, an insulating film consisting of the thermal oxide film 3 and the nitride film 4 of the high voltage MS capacitor and the gate oxide film 6 of the OMO3FET are formed. The insulating film of the high-voltage MIS capacitor is 400 thick, so it has high reliability even when high voltage is applied, and the nitride film has a higher dielectric constant than the oxide film, so it has a relatively large capacity. is obtained. 0 again
The gate oxide film of MO3FET is as thin as 150mm thick.
Moreover, since it is formed using a nitride film as a mask, no contamination by resist occurs, and a high-quality gate oxide film suitable for forming a high-speed OMO3 FET can be obtained.

After the process shown in Figure 1 (■), a polysilicon layer or a high melting point metal layer, etc., which will become the upper electrode of the high voltage MIS capacitor and the gate electrode of the 0MO3FET, is formed, and then the necessary steps of the normal bipolar/CMOS process are performed. form an element.

In the above embodiment, a MIS capacitor for analog circuits has a two-layer structure of an oxide film and a nitride film, but after the nitride film is formed in the step shown in Figure 1), heat treatment is performed for a long time in an oxidizing atmosphere. It is also possible to further form an oxide film on the nitride film by doing the following. If you add this step,
The MIS capacitor has a three-layer structure of an oxide film, a nitride film, and an oxide film, and this makes it possible to further stabilize the interface between the upper electrode of the MIS capacitor and the insulating film.

〔Effect of the invention〕

As described above based on the embodiments, the present invention provides an MIs capacitor for analog circuits that has high reliability even with high applied voltages and has a relatively large capacity, and an MIs capacitor that can be used at low voltage and high speed. A bipolar CMO3 semiconductor device equipped with an operating OMO3FET can be easily provided.

Further, according to the manufacturing method of the present invention, it is possible to form a CMOS FET having a high quality gate oxide film free from contamination.

[Brief explanation of the drawing]

FIGS. 1 to 2 are diagrams showing the manufacturing process of an embodiment of the semiconductor device according to the present invention. In the figure, 1 is a silicon substrate, 2 is a field oxide film, 3 is a thermal oxide film, 4 is a nitride film, 5 is a resist, and 6 is a gate oxide film. Patent applicant: Olympus Optical Industry Co., Ltd. Figure 1: Silicon substrate 2: Field oxide film 3: Thermal oxide film 4: Nitride film 5 Resist 6: Kate oxidation back

Claims (1)

[Claims] 1. In a semiconductor device in which a bipolar transistor having a relatively high collector-emitter breakdown voltage and a CMOSFET having a relatively thin gate insulating film coexist, at least two layers of a silicon thermal oxide film and a silicon nitride film are used. A CMOS with a high-voltage MIS capacitor made of structural insulating film and a gate insulating film made only of silicon thermal oxide film.
A semiconductor device comprising a FET. 2. The bipolar transistor has a collector-emitter breakdown voltage of 9V or more, and the CMOSFET has a breakdown voltage of 250V or more.
2. The semiconductor device according to claim 1, having a gate insulating film having a thickness of Å or less. 3. The semiconductor device according to claim 1 or 2, wherein the insulating film of the MIS capacitor has a three-layer structure of a silicon thermal oxide film, a silicon nitride film, and a silicon thermal oxide film. 4. In a method for manufacturing a semiconductor device in which a bipolar transistor having a relatively high collector-emitter breakdown voltage and a CMOSFET having a relatively thin gate insulating film coexist, a silicon thermal oxide film and a silicon nitride film are sequentially deposited on a semiconductor substrate. a step of removing the silicon nitride film in the region where the CMOSFET is to be formed, and then selectively removing the silicon thermal oxide film in the region where the CMOSFET is to be formed using the silicon nitride film on another region as a mask; By selectively oxidizing the region where the CMOSFET is to be formed using the silicon nitride film as a mask to form a gate insulating film, the insulating film of the MIS capacitor and the CMOSFE are separated.
1. A method of manufacturing a semiconductor device, comprising forming a gate insulating film of T.