JPH0221376A - Picture processing system - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to an image processing system in which a host computer section and an image processing circuit section are connected by a bus.

<Conventional technology> When configuring an image processing system, from the viewpoint of the software development environment and achieving both high speed and versatility of image processing, etc.
A multiprocessor system configuration that combines a host computer and a dedicated image processing processor is often adopted.

Common bus coupling method, multi-board coupling method, matrix switch coupling method, etc. are known as multiprocessor coupling methods, but from the viewpoint of economy (circuit scale) and flexibility, bus connection via 2-port memory is recommended. A coupled circuit method is often used.

Methods for realizing 2-port memory can be roughly divided into the following two types.

■Method that uses dedicated 2-port memory that can be accessed simultaneously from both boats.

Several dedicated 2-port memories are already commercially available as LSIs (for example, Fujitsu's MB8421, M
B8422, IDT7130, IDT7 from IDT, USA
132 etc.). In the case of dedicated 2-port memory, simultaneous reading from both ports is always possible. Arbitration is performed by the internal bus arbiter circuit only when simultaneous writes to the same address occur from both ports.

■A method in which a bus arbiter circuit is added to general-purpose memory to form a 2-port memory.

In this case, arbitration is always performed by the bus arbiter circuit during reading and writing, and simultaneous access is not possible.

<Problems to be solved by the invention> In such conventional methods, the host computer and
When connecting an image processing processor that processes image data, there were the following problems.

Dedicated 2-port memory that can be accessed simultaneously from both boards makes it difficult to manufacture ICs with large memory capacity, so if you try to increase the capacity by using dedicated 2-port memory, the circuit scale will become large and it will be very difficult. This will result in high costs. On the other hand, when storing 2 files such as image data on a small memory
Because it is extremely difficult to process large amounts of data in dimensional arrays, when one host computer or image processor processes and transfers image data to the other, a large amount of separate working memory is required. In addition, the data in this working memory had to be transferred via a dedicated 2-port memory, which caused a lot of overhead and poor efficiency.

(2) In the case of a 2-port memory composed of a general-purpose memory and a bus arbiter circuit, a large-capacity 2-port memory can be constructed at low cost, but there is a problem in that the bus arbiter circuit reduces memory access speed.

Furthermore, since the image processing processor generally has to give up the bus each time the host computer accesses the two-port memory, there is a drawback that the processing efficiency of the image processing processor deteriorates. This drawback is particularly noticeable when frequent communications occur between the host computer and the image processing processor.

The present invention has been made in view of these points, and it is an object of the present invention to realize efficient communication between a host computer and an image processing processor at low cost, and to provide an image processing system with excellent economic efficiency and high processing capacity. The purpose is to

Means for Solving the Problems> In the image processing system of the present invention, a host computer unit including a CPU and a main memory, and an image processing circuit unit including an image processing processor and an image memory are connected by a bus, and the CPU and a 2-port memory that can be accessed simultaneously from the image processing processor, and a shared memory;
The present invention is characterized in that it includes a bus switching control circuit that is switched under program control of the CPU or the image processing processor and allows access to the shared memory only from any one of the CPU or the image processing processor.

Further, it is preferable that the image processing processor is configured so that it can simultaneously write to the shared memory and the image memory.

Effect> According to the image processing system of the present invention, in communication between the CPU of the host computer section and the image processing processor of the image processing circuit section, high-level information such as commands with a small number of data 1 is stored in the dedicated 2-port memory. Low-level information with a large amount of data, such as image data, is processed via a shared memory whose bus is switched by a bus switching control circuit.

Furthermore, data written by the image processing processor to the image memory can be simultaneously written to the bus-switched shared memory. Therefore, efficient communication between the CPU and the image processing processor is possible without requiring a large circuit scale.

<Example> DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to embodiments.

FIG. 1 is a block diagram of an image processing system of the present invention.

In FIG. 1, the image processing system is composed of a host computer section I and an image processing circuit section 2. As shown in FIG. Both are connected via a system bus 15.

The host computer unit 1 is composed of a CPU 3, a main memory 4, an input/output interface 5, an input/output device 6, etc., and the CPU, main memory 4, and input/output interface 5 are connected via a system bus 15. .

The image processing circuit section 2 includes an image processing processor 7 and an image memory 8 that are connected to each other via an image bus 16, as well as an interface circuit 9.11, a dedicated 2-port memory IO, a bus switching control circuit 12, and an output port 13. and a shared memory 14. The dedicated 2-port memory IO can be accessed simultaneously from both ports, and the commercially available tC mentioned above can be used. The interface circuits 9 and 11 are connected to a system bus 15, respectively.
This is a circuit for making the dedicated 2-port memory IO accessible from the image bus 16, and may have a very general circuit configuration as shown in FIG. 2, for example. In FIG. 2, the decoder 22 uses the upper bit A11 of the address bus.
Ass is decoded to generate a signal to be input to the chip enable σ■ terminal of the dedicated 2-port memory 10, and the bidirectional data bus buffer 23 is connected to the data bus D.
. - It acts as a transceiver/receiver for D7.

On the other hand, the output port 13 shown in FIG. 1 is for outputting a selection signal 17 that is manually input to the bus switching control circuit 12. The selection signal 17 is program-controlled by the image processing processor 7. The above bus switching control circuit 1
2 is the shared memory 14 and the system bus 15 or image bus! This circuit switches the bus so that it can be accessed from either one of the buses 6 and 6, and the selection signal 17 determines which way it can be accessed.

FIG. 3 is a diagram showing an example of the configuration of the bus switching control circuit.

The output boat 13 and shared memory 14 in FIG. 3 are the same as the output boat 13 and shared memory 14 in FIG. 1, respectively. In FIG. 3, a dynamic RAM (DRAM) whose capacity can easily be increased is used as the shared memory. In FIG. 3, decoders 31 and 32 decode signals from system bus 15 and image bus 16, respectively, and generate memory selection signals that become active when shared memory 14 is accessed. The multiplexers 33, 34, and 35 also function to select one of the signals from the system bus 15 and the image bus 16 in response to the selection signal 17 from the output port 13. Multiplexer 33 selects a write signal, multiplexer 34 selects an address signal, and multiplexer 35 selects a memory selection signal from decoders 31 and 32, respectively.

The RAS, CAS generation circuit 38 supplies RAS to the shared memory 14 from the memory selection signal from the multiplexer 35.
Generate AS and CAS signals. Further, the address conversion circuit 37 generates an address signal to be supplied to the shared memory 14 from the address signal selected by the multiplexer 34. The refresh control circuit 39 is for periodically refreshing the shared memory 14 composed of a dynamic RAM. Bidirectional data bus buffers 41 and 42 are connected to shared memory from system bus 15 and image bus 16, respectively! 4 is accessed, data is sent and received between each bus and the shared memory 14. However, although not shown, the selection signal 1
Accesses from the bus side not selected by 7 are ignored.

By applying the above-described bus switching control circuit of FIG. 3 to the bus switching control circuit of FIG. 4 can be accessed. In this case, there is no need to perform bus arbitration between the two buses, so the shared memory 14
This enables high-speed access according to the access speed of the memory used. Further, since the memory constituting the shared memory i4 uses a general-purpose memory IC, it is possible to increase the capacity at low cost. In the example of FIG. 3, the shared memory is a dynamic RAM, but of course it may be a static RAM. In addition, although an example was shown in which the output boat 13 (see Figures 1 and 3) is connected to the image bus side,
It may also be connected to the system bus side. In the embodiment of FIG.
When it is desired to control the selection signal 17 which is the output of the output port 13 from the CPU 3, the dedicated 2-port memory 10 is output from the CPU 3.
It is also possible to take an indirect method of sending control commands to the image processor 7 and controlling the image processor 7.

As shown in the address map of FIG. 4, there is an area 5 in a part of the address space of the image processing processor 7 that is commonly accessed by the image memory 8 and the shared memory 14 only when writing.
1, it is possible to ensure that part or all of the data written from the image processing processor 7 to the image memory 8 always exists in the common memory 14 as needed.

That is, when the image processing processor 7 writes the processing results to the image memory 8, if the common area 51 in FIG. 4 is accessed, the processing results are written to the image memory 8 and the common memory 14 at the same time. Therefore, when it is desired to read the contents of the image memory 8 from the CPU 3, the image processing processor 7 reads the data of the image memory 8 one by one from the common memory I.
4, it is only necessary to switch the selection signal 17 from the output port 13 to the system bus 15 side.

Such a simultaneous write function is achieved by decoding addresses in the image memory 8 and the common memory 14 so as to satisfy FIG. 4, and when the common area 51 is accessed, the image processing processor 7 is This can be easily achieved by matching the response signal sent back to memory with slow access speed.

<Effects of the Invention> As described above, according to the present invention, high-level information with a small amount of data such as commands is transmitted between the CPU of the host computer section and the image processing processor of the image processing circuit section. is efficiently communicated via a dedicated 2-port memory, and low-level information with a large amount of data, such as image data, is processed and transferred at high speed via a common memory that is bus-switched by a bus switching circuit, making it flexible. This enables highly efficient inter-processor communication and improves the performance of image processing systems.

Furthermore, a shared memory that stores a large amount of data has the advantage that a low-cost general-purpose memory IC can be used without reducing access speed.

Furthermore, by providing a function for simultaneous writing from the image processing processor to the image memory and shared memory, the number of data transfers between the image memory and shared memory can be reduced.
A higher performance image processing system can be obtained.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of the image processing system of the present invention, Fig. 2 is a diagram showing a circuit example of a dedicated 2-port memory, Fig. 3 is a block diagram of a bus switching control circuit, and Fig. 4 is an address of the image processing processor. It is a figure showing an example of a map. 1... Host computer section, 2... Image processing circuit section, 3... CPU. 4... Main memory, 7... Image processing processor, 8... Image memory, IO... Dedicated 2-port memory, 12... Bus switching control circuit, 14... Shared memory, 23.41. 42...Bidirectional bus buffer, 3
3.34.35...Multiplexer. Figure 2 If @2 Horde Memo Figure 3 Figure 4

Claims (1)

[Claims] (1) In an image processing system in which a host computer unit including a CPU and main memory and an image processing circuit unit including an image processing processor and image memory are connected by a bus, the CPU and the image processing processor can simultaneously access the image processing system. a 2-port memory, a shared memory, and a bus switching control circuit that is switched under program control of the CPU or the image processing processor and makes the shared memory accessible only from any one of the CPU or the image processing processor. An image processing system comprising: