JPH02213244A - Fault detector for switch - Google Patents

Abstract

PURPOSE:To find out a fault of a switch early by providing a fault check code addition circuit adding a fault check code to a data to an input stage of the switch and providing the fault check circuit to an output stage of the switch. CONSTITUTION:Fault check code addition circuits 13a, 13b are inserted respectively in lines L10a, 10b through which a data going to a switch 12 is sent from subscriber circuits 11a, 11b to test the switch 12. Moreover, fault check circuits 14a, 14b are inserted respectively in lines L11a, 11b through which a data going to a switch 12 is sent from the subscriber circuits 11a, 11b. The fault check circuit 14b detects the presence of a fault based on an added FCS code FCS, annunciates the fault when the fault takes place and eliminates the FCS code FCS when no fault exists, the data is restored to the original data DAT 1 and the result is outputted to a terminal equipment 10b.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a switch failure detection device for detecting a failure of a switch in a switching device.

[Prior Art] Conventionally, switches used in switching equipment include time division switches, space division switches, and ATM (asynchronous transfer mode; AsynchrOnOL) switches.
There are various types of switches such as IS rr, answer HOde) multiplex switches, but no matter which switch is used, the basic configuration for detecting a switch failure is as follows:
The configuration was shown in FIG.

In FIG. 2, a plurality of terminal devices 1a and 1b (only two terminal devices are shown in FIG. 2) are connected to a switch 3 via corresponding subscriber circuits 2a and 2b, respectively. There is.

Here, for data transmission between the terminal devices 1a and lb, the switch 3 connects the lines Lla and L2a connecting the subscriber circuit 2a and the switch 3, and the subscriber circuit 2b and the switch 3 based on the calling data. Connecting lines Llb and L
2b, and data from the terminal device 1a is transferred to the subscriber circuit 2a, line Lla, switch 3, line L2b,
Data is supplied to the terminal device 1b via the subscriber circuit 2b, and conversely, data from the terminal device 1b is sent to the subscriber circuit 2b, line Ll.
b, switch 3, line L2a, subscriber times M! This was done by giving it to the terminal device 1a via I2a.

However, if the switch 3 is out of order, the connection to the called terminal device may be incorrect, and even if the connection is correct, the transmitted data may be destroyed.

Therefore, a failure detection configuration for the switch 3 is provided.

That is, a test circuit 6 is provided which includes a test data generation circuit 4 that generates test data and a test data check circuit 5 that checks the test data. Further, each subscriber circuit 2a, 2b is provided with a configuration in which the test data given from the switch 3 is looped back to the switch 3 without being sent to the terminal device 1a, as shown for the subscriber circuit 2a. ing. More specifically,
The subscriber circuit 2a outputs the data directed to the terminal device 1a given from the line L2a to the line L3a connected to the terminal device 1a, and outputs the test data given from the line L2a to the return line L4a. The selector circuit 7a and the data outputted from the terminal device 1a via the line L5a are outputted to the line Lla, and the test data from the return line L4a is outputted to the line L.
A selector circuit 218a that outputs to 1a is provided.

In a test with this configuration, the test data generation circuit 4 generates test data including data specifying the subscriber circuit, and supplies the generated test data to the switch 3 via the line L6.
, a loopback configuration of a predetermined subscriber circuit, the test data checking circuit 5 receives the test data returned to the test circuit 6 via the switch 3 and the line L7, and the test data checking circuit 5 receives the test data. This is done by comparing the original test data output by the generation circuit 4 and the received test data. When the test data check circuit 5 detects a failure, it gives a notification using visual or auditory notification means.

For example, in a test that specifies the subscriber circuit 2a, the test data passes sequentially through line L6, switch 3, line L2a, selector circuit 7a, return line L4a, selector circuit 8a, line Lla, switch 3, and line L7. , it returned to the test circuit 6 and was used to detect a failure in the switch 3.

[Problems to be Solved by the Invention] By the way, since the switch 3 is always in an operating state or in an operable state, the timing at which the test circuit 6 generates test data and executes a test is conventionally limited. . In other words, when a call is made from either end* device, two tests are performed as a circuit that loops back the subscriber circuit connected to that terminal device and the called terminal device, and there is no failure. In this case, the terminal devices are then able to transfer data between the terminal devices.

However, testing at this timing requires extra time before starting data transmission, which poses a problem in terms of service to users.

For this reason, tests were sometimes performed at night when the occurrence of replacement using switch 3 was extremely rare.

At this test timing, if there are many switches that the test circuit 6 tests, or if there are many terminal devices connected to the switches, the , the tests will be performed several days or even four times apart.

Therefore, in the past, it was often impossible to detect a malfunction in a part of the switch at an early stage, which was a problem.

Furthermore, since conventional fault detection devices detect faults using test data, they cannot detect bit errors in data that occur during online data transmission between terminal devices. From this point of view, it is desirable to detect failures in an online state.
Although the system is equipped with a configuration that adds an error correction code and a configuration that corrects errors based on the correction code, it is not possible to identify whether or not the location where a bit error, etc. of data occurs is a switch. Can not.

The present invention has been made in consideration of the above points, and provides a switch that can detect a failure in a switch when transmitting data between terminal devices without delaying the start of data transmission. The present invention aims to provide a failure detection device.

[Means for Solving the Problem] In order to solve the problem, the present invention adds a failure check code to data on the data transmission line from the subscriber circuit connected to the terminal device to the switch. A failure check code addition circuit is installed. Additionally, switch failures are detected based on the failure check code added to the data on the data transmission line from the switch to the subscriber circuit, and if there is no failure, the failure check code is removed to restore the original data. A failure check circuit was installed to convert the data back into data and output it to the subscriber circuit.

[Operation] When transmitting data from one terminal device to another, the data from the transmitting terminal device passes through the subscriber circuit, is added with a fault check code by the fault check code adding circuit, and then sent to the switch. given to.

Data with a failure check code added from the switch to the receiving terminal device is provided to a failure check circuit. The failure check circuit determines whether or not there is a failure based on the failure check code, and detects the failure if it exists. If there is no failure, the original data from which the failure check code has been removed is restored and sent to the receiving terminal device via the subscriber circuit.

[Example] Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

Here, FIG. 1 is a block diagram showing the configuration of this embodiment,
FIG. 3 is a timing chart showing input/output data of the fault check code adding circuit or the fault check circuit, and FIG. 4 is a block diagram showing an example of the fault check code generating circuit.

In FIG. 1, a plurality of terminal devices are each connected to a corresponding subscriber circuit. In FIG. 1, only two terminal devices 10a and 10b are shown, and therefore only subscriber ports 2811a and ttb corresponding to the terminal devices 10a and 10b are shown as subscriber circuits.

In this embodiment, subscriber circuits 11a and llb are not provided with a loopback configuration for returning test data given from switch 12 to switch 12, unlike conventional circuits. That is, the subscriber circuits 11a and llb are configured to output data from the terminal device 10a and tab to the switch 12 to the lines L10a and L10b, and to output data sent from the switch 12 via the lines LLla and Lllb to the terminal device. 10a and 10a, and no selector circuit for loopback is provided.

In this embodiment, in order to test the switch 12, fault check code adding circuits 13a and 13b are interposed on the lines L10a and L10b that transmit data from the subscriber circuits 11a and llb to the switch 12, respectively. It is inserted. Further, the subscriber circuit ILa is connected from the switch 12 to the subscriber circuit ILa.
, llb, the lines LILa,L transmitting data destined for
Fault check circuits 14a and 14 are respectively provided on llb.
b is inserted.

In this embodiment, each failure check code addition circuit 13a, 13b uses a frame check sequence (Fe2) code as a failure check code, and
This FC3 code is added and the added data is transferred to switch 1.
This is what is output to 2.

Here, each failure check code addition circuit 13a, 13b compresses the input data DATI shown in FIG. 3(C) on the time axis for each frame represented by the frame pulse signal FP shown in FIG. 3(A). Then, a time in which FC8C2FC8 can be inserted is formed within one frame time, and FC8C2FC3 is inserted at the time formed as shown in FIG. 3(E) to form output data DAT2.

In addition, FIG. 3(B) shows each failure check code adding circuit 1.
3a and 13b, and FIG. 3(D) shows the output data DA to which FC8C2FC8 is added.
This shows a clock signal CK2 that instructs each bit of T2, and the period of the clock signal CK2 regarding the data DAT2 after adding the FCS code is equal to the period of the clock signal CK1 concerning the data DAT1 before adding the FCS code FC3.
The period T of is multiplied by x/(x+y).

Here, X indicates the number of bits in one frame of the original data DAT1, and y indicates the number of bits of the added FC8C2FC8.

The FC8 code is generated, for example, by the FC8 code generation circuit 20 shown in FIG. The FC8 code generation circuit 20 uses x16+x12+x5+1 as a generating polynomial. The FC8 code generation circuit 20 includes a 5-stage shift register circuit 21, a 7-stage shift register circuit 22 for lower-order bits, and a 4-stage shift register circuit 23 for lower-order bits.
Exclusive OR of the least significant bit and the input data is applied to the input stage of the shift register circuit j121.
Shiv-OR circuit 24 and this exclusive-OR circuit 2
4 and the last stage bit of the shift register circuit 21 and supplies it to the input stage of the shift register circuit 22; and the output of the exclusive OR circuit 24 and the shift register circuit 22.
and an exclusive OR circuit 26 which calculates an exclusive OR with the last stage bit of the bit and supplies it to the input stage of the shift register circuit 23.

When all data DATI for one frame has been input, the bit contents of each shift register circuit 21, 22, and 23 become FC3C2FC8, and as described above, one frame is created by compressing the original transmission data DAT1 on the time axis. will be inserted during free time.

On the other hand, the failure check circuits 14a and 14b are shown in FIG.
) Data DA with FC3C2FC8 added
From T2, a data abnormality, and therefore a failure of the switch 12, is detected. The same circuit as shown in FIG. 4 is also used to detect this failure. The data DAT2 to which FC8C2FC8 is added is sequentially input to the circuit shown in FIG.
If the value of each stage of 3 is "0", it is judged as normal and "1"
If so, it is determined that the switch 12 is malfunctioning.

When the failure check circuits 14a and 14b determine that it is normal, they remove FC8C2FC8 from the data DAT2 to which FC8C2FC8 shown in FIG. Data DAT over one frame period as shown in (C)
The signal is expanded to I and output to subscriber circuits 13a and 13b.

Next, the operation when transferring data from the terminal device 10a to the terminal device 10b will be described.

In this case, the data DAT output from the terminal device 10a
1 is given to the failure check code addition circuit 13a via the subscriber circuit 11a. Failure check code addition circuit 1
3a adds FC3C2FC8 to the input data DAT■ and supplies the added data DAT2 to the switch 12.

The switch 12 performs an exchange operation to add the data DAT2.
is given to the failure check circuit 14b.

The failure check circuit 14b is an attached FC8C2.
The presence or absence of a failure is detected based on FC8, and if a failure occurs, a notification operation is performed.On the other hand, if there is no failure, FC8C2FC8 is removed and the original data DAT1 is restored.
and output to the terminal device 10b via the subscriber circuit 11b.

Therefore, according to the embodiment described above, it is possible to test the switch 12 in an online state without sending any test data, and a failure can be detected at an early stage. In this way, although the test is performed in an online state, the test is not performed prior to transmission, so there is no wasted time during transmission. Further, bit errors other than fixed failures occurring in the switch 12 can also be detected. This bit error can be restored to correct data through a correction operation.

In the above-described embodiment, the failure check circuits 14a and 14b check for a failure when they are in the online state, but the switch 12 may always send a no-call pattern to the failure check code adding circuit when it is not in the online state. It is also possible to output the signal and send it back with an FC8 code added thereto, and provide the returned no-call pattern with the FC8 code added to the failure check circuit to constantly monitor failures. In this case, the switch 12
failures can be detected early.

The switches to which the present invention is applied include time division switches,
It may be a space division switch, an ATM multiplex switch, or the like. In the case of time division switches and space division switches, a certain fixed time (frame time) is determined and the FC8
It is sufficient to add a code, and in the case of an ATM multiplex switch, an FC8 code may be added for each cell.

Further, the number of bits of the FC8 code used as the fault check code and the generating polynomial to be applied may be selected as appropriate. Further, the failure check code is not limited to the FC8 code, and various types may be applied. Not only a fault check code determined depending on the data to be transmitted, but also a fixed pattern fault check code may be used. In this case,
Bit errors in data cannot be detected.

[Effects of the Invention] As described above, according to the present invention, a fault check code adding circuit for adding a fault check code to data is provided at the input stage of the switch, and the switch is controlled based on the added fault check code. Since a fault check circuit for detecting faults is provided at the output stage of the switch, faults can be detected online without affecting data transmission time, making it possible to discover switch faults at an early stage. can.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of the switch failure detection device of the present invention, FIG. 2 is a block diagram showing the configuration of a conventional device, and FIG. 3 is a block diagram showing the configuration of a conventional device. A timing chart showing input/output data, and FIG. 4 is a block diagram showing an example of an FC8 code generation circuit. 10a, l Ob ・, terminal device, lla, llb ・・
・Subscriber circuit, 12...switch, 13a, 13b・
・Failure check code addition circuit, 14a, 14b...
Failure check circuit, 20...FC3 code generation circuit. 51 Stator check circuit 7'iγ diagram of conventional failure detection device I! Figure 2

Claims (1)

[Scope of Claims] A fault check code adding circuit for adding a fault check code to data is provided on a data transmission line from a subscriber circuit connected to a terminal device to a switch, and a fault check code adding circuit is provided for adding a fault check code to data. A failure in the switch is detected based on a failure check code added to the data on the data transmission line going to the circuit, and if there is no failure, the failure check code is removed and the original data is returned to the above. A failure detection device for a switch, characterized in that it is provided with a failure check circuit that outputs to a subscriber circuit.