JPH02213153A - Block arrangement processing method - Google Patents

Abstract

PURPOSE:To make it possible to fulfill the restriction of the wiring length of a critical path which becomes necessary in design of a high-speed and highly efficient LSI, printed wiring board, etc., by providing a virtual signal line connecting means, a connecting information output means, and a block arranging means which are respectively specific. CONSTITUTION:In the block arrangement processing method to do arrangement processing of a block which becomes the unit for arrangement of an LSI, a printed board, etc., the virtual signal line connecting means 1 to input information on signal transmission between specified blocks which is electrically analyzed in advance when information on logical connection between blocks is being input and connect virtual signal lines, the connective information output means 2 to add virtual signal line information to logical connection information upon considering the line length restriction of the virtual signal line which is connected by the virtual signal line connecting means 1 and giving weight to the virtual signal line according to the necessity, and the block arranging means 3 to execute the initial arrangement processing and improved arrangement processing of a block on the basis of the logical connection information to which virtual signal line information is added by the connective information output means 2, are provided.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a block arrangement processing method, and in particular to an LSI
(Larga 5cale Integrated
The present invention relates to a block placement processing method for arranging a block that is a unit of placement of a printed circuit board or the like.

[Conventional technology]

Conventionally, in this type of block placement processing method, blocks were placed according to a predetermined evaluation function based only on the logical connection relationship with existing blocks in order to shorten the average distance between blocks as much as possible (Reference Literature "Logic 1st CADJ, Information Processing Society of Japan, published March 20, 1980)".

In recent years, high speed 5 high performance LS 1. Printed circuit boards, etc. are now required, and is it to reduce delay time?
j [It is becoming necessary to limit the wiring length of nets (critical buses) between blocks that span several blocks. Therefore, it has become necessary for the block placement means to perform processing to reduce the distance between blocks to a certain value or less for broncs on the critical bus.

[Problem to be solved by the invention]

In the conventional block placement processing method described above, blocks are placed according to a predetermined evaluation function based only on logical connection relationships, so it is effective for shortening the block interval on average (in fact, block placement processing (Generally, minimizing the total wiring length is used as the evaluation function for
However, in order to keep the block spacing below a certain value, the distance between specific blocks must be checked after the block placement is completed, and if the conditions are not met, the placement results must be corrected.

In view of the above-mentioned points, an object of the present invention is to input signal propagation information between blocks that has been electrically analyzed in advance during block placement processing, add virtual connection relationships to logical connection information, and place blocks. By performing processing, we provide a block placement processing method that satisfies the limitations on critical path wiring lengths required when designing high-speed, high-performance LSIs, printed circuit boards, etc. (Means for solving the problem) The block placement processing method of the present invention is a block placement processing method for placing blocks that are placement units for LSIs, printed circuit boards, etc. When logical connection information between blocks is input, electrical analysis is performed in advance. A virtual signal line connecting means that connects virtual signal lines by inputting signal propagation information between specific blocks, and a virtual signal line connecting means that inputs signal propagation information between specific blocks, and a virtual signal line connecting means that connects virtual signal lines by inputting signal propagation information between specific blocks. Connection information output means adds virtual signal line information to the logical connection information after weighting the virtual signal line, and initialization of the block is performed based on the logical connection information to which the virtual signal line information is added by the connection information output means. and block placement means for executing placement processing and improved placement processing.

[Effect]

In the block placement processing method of the present invention, the virtual signal line connection means manually creates the virtual signal line using signal propagation information between specific blocks that has been electrically analyzed in advance when the logical connection information between the blocks is input. The connection information output means adds weight to the virtual signal line as necessary in consideration of the line length limit of the virtual signal line connected by the virtual signal line connection means, and then outputs the virtual signal line information to the logical connection information. is added, and the block placement means executes initial placement processing and improved placement processing of the block based on the logical connection information to which the virtual signal line information is added by the connection information output means.

〔Example〕

Next, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a diagram showing the configuration and processing flow of a block placement processing method according to an embodiment of the present invention.

The block placement processing method of this embodiment is comprised of virtual signal line connection means 1, connection information output means 2, and block placement means 3.

Further, the processing in the block arrangement processing method of this embodiment includes a logical connection information input step 11, a specific inter-block signal propagation information input step 12, a virtual signal line connection step 13, a virtual signal line selection step 14, Line length restriction presence/absence determination step 15, weight addition step 16, virtual signal line information addition determination step 17, virtual signal line information addition step 8, and block placement processing execution step 19
It consists of

Next, the operation of the block arrangement processing method of this embodiment configured as described above will be explained.

The virtual signal connection line means 1 manually inputs logical connection information indicating the logical connection relationship between the block to be placed and other blocks (step 11), and connects it to a specific block such as a flip-flop block that has been electrically analyzed in advance. (Step 12) Next, the virtual signal line connecting means I connects a virtual signal &Jl (hereinafter referred to as a virtual signal line) between the specific blocks (Step 13). , transfers control to the connection information output means 2.

The connection information output means 2, which has been given control from the virtual signal line connection means 1, selects one virtual signal line (step 14).
, at this time, if there is no virtual signal line to be selected, the connection information output means 2 passes the control m to the block arrangement means 3.

Next, the connection information output means 2 outputs the provisional 9! ! Check whether there is a line length restriction between the specific blocks to which the signal lines are connected (step 15). If there is a line length restriction, the connection information output means 2 outputs the predetermined information as necessary. Giving weight to the virtual signal line according to the evaluation function (step 16),
If the virtual signal line information is added to the logical connection information (step 1), the control returns to step 14. If there is no line length restriction, the connection information output means 2 adds the virtual signal line information to the logical connection information.
Step 17) to decide whether to add line information or not.
When adding virtual signal line information, control is performed in step 18.
If virtual signal line information is not to be added, control is returned to step 14.

The block arrangement means 3, which has been given control by the connection information output means 2, performs block arrangement processing based on the logical connection information (step 19).

Next, for example, as shown in FIG.
l, B2. B3. Consider the case where block Bl is rearranged when B4, B5, and B6 are arranged.

Here, block B1 has a logical connection relationship between block B3, which is connected by signal &1lSl, and blocks B4 and B5, which are connected by signal lines S2 and B5.

Furthermore, it is assumed that block Bl and block B2 are specific blocks that take into consideration the relationship between line lengths whose signal propagation information has been electrically analyzed in advance.

The virtual signal line connection means 1 inputs the logical connection information of the block B1, that is, the information of the signal &@Sl, S2 and B5 (step 11). Next, the virtual signal line connection means 1
Step 12) inputs signal propagation information between the specific block Bl and the specific block B2.
A virtual signal line VSI is connected between 1 and the specific block B2 (step 13), and control is passed to the connection information output means 2.

The connection information output means 2, which has been given control from the virtual signal line connection means 1, selects the virtual signal line VSI (step 14).
), it is determined that there is a line length restriction between the specific block B2 connected by the virtual line 43 VSI (step 15
)0 Next, the connection information output means 2 gives weight to the virtual signal vAVs1 according to a predetermined evaluation function as necessary (step 16), and inputs the virtual signal line information of the virtual signal line VSI in step 11. Then, control returns to step 14, and since there is no virtual signal line to be selected, the connection information output means 2 passes control to the block arrangement means 3 (step 18).

The block arrangement means 3, which has been given control by the connection information output means 2, executes the arrangement process of the block B1 based on the logical connection information to which the virtual signal line information of the virtual signal line VSI has been added (step 19).

Here, block B1 is a specific block that takes into consideration the line length relationship whose signal propagation information has been electrically analyzed in advance, so block B3. Virtual signal line information of a virtual signal line vsi with a wiring length restriction with block B2 is added to the logical connection information with B4 and B5. Therefore, when no weight is added to the virtual signal line vSl in the process of step 16, the information about the signal lines St, S2, and B5 and the virtual signal line vS1 determines whether the block B3. B4,
The center of gravity position G1 of B5 and B2 is the improved layout candidate position of block Bl. Furthermore, if a positive weight is given to the virtual signal line VSt in the process of step 16, for example, block B'3. B4. If the center of gravity position G3 of B5 and B2 becomes the improved placement candidate position and a negative weight is given to the virtual signal line VSI, for example, block B3. B4. The center of gravity position G4 of B5' and B2 becomes the improved arrangement candidate position.

As a result, by manipulating the evaluation function that gives the weight of the virtual signal line depending on the case, it is possible to produce a placement result that shortens the wiring length of the critical bus, and conversely, it is possible to produce a placement result that shortens the wiring length of the critical bus. It can be seen that it is also possible to produce a placement result that increases the wiring length.

On the other hand, in the conventional block arrangement processing method, since the information of the virtual signal IVsI is not added to the logical connection information, the block B3. Center of gravity position G of block B4 and block B5
2 is the improved placement candidate position.

FIG. 4 shows a diagram in which the block B1 is arranged in an improved manner at the center of gravity position G2, which is a candidate position for improved arrangement according to the conventional block arrangement processing method.

For example, if block B1 is arranged in an improved manner as shown in FIG. 3 using the block arrangement processing method of this embodiment, the critical bus CP! between block Bl and block B2! The wiring length of (signal line S2, sum of signal line S3 and signal ms4) is the wiring length of critical bus CP2 between block B1 and block B2 in FIG. It is shorter than the line length.

Note that the block arrangement processing method of the present invention can be realized by creating a program and operating it on a computer, or by implementing it in hardware and operating it.

〔Effect of the invention〕

As explained above, the present invention inputs signal propagation information between specific blocks that has been electrically analyzed in advance, adds virtual connection relationships to logical connection information, and performs block placement processing at high speed. The present invention has the advantage that it is possible to satisfy the limitations on the wiring length of a critical bus, which is required when designing high-performance LSIs, printed circuit boards, and the like.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the configuration and processing flow of a block placement processing method according to an embodiment of the present invention, FIG. 2 is a diagram for explaining the processing in the block arrangement processing method of this embodiment, and FIG. FIG. 4 is a diagram showing an example of a block arrangement result obtained by the block arrangement processing method of this embodiment, and FIG. 4 is a diagram showing an example of a block arrangement result obtained by the conventional block arrangement processing method. In the figure, l...virtual signal line connection means, 2...connection information output means, 3...block arrangement means, B1-86...block, 81-S5...signal line, VSI... ...Virtual signal line, 01-G4... Center of gravity position, CPI, CF2/critical bus.

Claims (1)

[Claims] In a block placement processing method for arranging blocks that are units of arrangement for LSIs, printed circuit boards, etc., a specific block that has been electrically analyzed in advance when logical connection information between blocks is input. A virtual signal line connection means that connects virtual signal lines by inputting signal propagation information between them, and a virtual signal line connection means that connects virtual signal lines by inputting signal propagation information between A connection information output means for adding virtual signal line information to the logical connection information after giving a weight to the logical connection information; and a block initial placement process and 1. A block placement processing method comprising block placement means for performing improved placement processing.