JPH02211521A - Display controller - Google Patents

Abstract

PURPOSE:To load the large quantity of screen attribute data by reading the screen attribute data during a horizontal display period, setting them in a register with the use of a DMA function, and preventing character data from being displayed during the horizontal display period. CONSTITUTION:A bus controller 15 accesses a DMA row starting address in a row table area by a row table address signal in the last horizontal fly-back interval during a horizontal scanning fly-back interval. According to an accessed DMA row starting address, a DMA row in a display data area 9 is read in the horizontal display interval continuously after the horizontal fly-back interval. The screen attribute data on the read DMA row are supplied to the buffer of the controller 15, and supplied to a DMA controller 17 of a display controller 16 by a prescribed timing signal. The controller 17 DMA-transfered the set data and pallet data out of the supplied data respectively to an I/O register 18 and to the memory of a pallet mechanism 19.

Description

DETAILED DESCRIPTION OF THE INVENTION A. Field of Industrial Application The present invention relates to a display control device.
More specifically, the present invention relates to a display control device for displaying character data related to multiple applications or multiple host computers on a split screen when multiple applications or multiple host computers use one display device at the same time.

B. Prior art When displaying character data in color on a split screen in a scanning display device, background color, cursor color, maximum number of display lines, number of scanning lines per line, cursor scanning line position, etc. Since screen-specific attributes such as screen attributes cannot be changed for each screen, each screen is displayed in the same mode. To solve this problem, one idea is to prepare multiple sets of registers in which screen attributes are set, set screen attributes for each screen in each register, and then switch to the horizontal blanking period at the screen split position. However, since the number of registers increases, it is a problem in terms of cost.

JP-A No. 59-160176 discloses that display specification data, such as the presence or absence of high-intensity display, the presence or absence of reverse display, the presence or absence of blinking display, cursor display color, etc., is stored in a memory corresponding to each split screen. , discloses a system in which the information is read out during the horizontal retrace period at the screen division position and set in the control section.

However, since the horizontal retrace period is usually a short time of about 5 microseconds, only about 20 bytes of data can be read at most, and generally 50 bytes of screen attribute data can be read.
More than a byte of data is required, and thus this prior art would severely limit the amount of display specification data for each split screen. Moreover, in this conventional technology,
It is not possible to control attributes for each display line.

In addition, Japanese Patent Application Laid-Open No. 61-212892 stores display characters and display character start address data in line units for each split screen, and stores display character start address data during the horizontal retrace period before the start of display. It is disclosed that display characters of the relevant line are read by reading them and setting them in an address counter. This simply manages the display data of the split screen on a line-by-line basis, and cannot control screen attributes on a screen-by-screen basis.

C1 Problem to be Solved by the Invention It has been impossible to set a large amount of screen attribute data for multiple split screens that are displayed simultaneously in the display controller during the screen scanning period; however, the present invention solves this problem. It is what makes it possible.

Means and operation for solving problem D1 In the present invention, the screen attribute data and the address of the data for each split screen are stored in a playback buffer, and the data is stored in the horizontal retrace period at the start of scanning each screen. The stored address is read out, screen attribute data is read out according to the read address during the subsequent horizontal display period, and it is set in the register of the display controller using the DMA mechanism, and the character data is not displayed during the horizontal display period. The display device is controlled so as not to display or to display a predetermined screen dividing line.

E. By using the horizontal display period to read out the effect screen attribute data, it is possible to read out a large amount of data, and by using the DMA mechanism to set the data in the register, high-speed setting operation is possible.

Furthermore, since the reading operation of screen attribute data and the reading operation of display data characters are performed by the same mechanism and control, the control device is simplified and a low-cost device becomes possible.

F. Embodiment In FIG. 1, two host computers are connected to one CR.
An embodiment of the present invention is shown in which data is displayed on the screen of a display device by screen division.As shown in the figure, a host computer 1 and a host computer 2 communicate with a display control device via a communication control device 3. 4, the output of the host computer 1 is displayed on the upper split screen 6 of the CRT display device 5 under the control of the controller 4, and the output of the host computer 2 is displayed on the lower split screen 7 of the CRT display device 5. shall be displayed.

The display control device 4 has a playback buffer 8, which buffer 8 has a data line containing screen attribute data regarding the upper split screen 6 of the display device 5 and a data line containing character data to be displayed on the screen 6. a display data area 9 for storing data lines containing screen attribute data regarding the lower split screen 7 and a display data area 10 for storing data lines containing character data to be displayed on the screen 7; It consists of a row table 11 for storing the starting address of a data row, a row table 12 for storing the starting address of each data row in area 10, and a character transfer system from host computers 1 and 2 to areas 9 and 10. Data writing is done by MPU13
carried out under the control of Further, reading of data from buffer 8 is performed by bus controller 15 under the control of timing signals from timing signal generator 14. The display controller 16 uses the DMA (direct memory access) mechanism 17 to receive the screen attribute data given from the bus controller 15! 10 register 1
8 or pallet mechanism 19. The display controller 16 also converts the character data given from the bus controller 15 into a font using the character generator 20.
The data is converted into data, colored by a palette mechanism, and output to the display 5.

An area 9 for storing 0-screen attribute data and character data will be explained with reference to FIG. 2 to outline the configuration of the playback buffer 8.
and 10 have similar configurations, so
In this area, one of which is shown in FIG. 2, character data consisting of a character code and a character attribute code is stored for each display line, and screen attribute data for that screen is stored in the DMA line. Also, since areas 11 and 12 both have similar configurations, one of them is shown in FIG. Row attribute codes are stored in the form of a table. This row attribute code is
For example, it is a code that indicates whether double-width or double-height characters are displayed in that line, whether a separator line is displayed, etc.

FIG. 3 is a block diagram of bus controller 15. This bus controller is a timing signal generator 14.
Its operation is controlled by various timing signals given from the . The timing signal generator 14 consists of a large number of counters, and is configured to supply signals to each circuit in the bus controller 15 and display controller 16 at predetermined timings, and is basically similar to existing timing signal generators. They have essentially the same configuration and functionality.

A row table address generation circuit 21 in the bus controller 15 responds to a predetermined signal from the timing signal generator 14 to address the row table area 11 in the buffer 8.
Or 12 addresses are generated sequentially. The reproduction address generation circuit 22 receives the address read from the row table area of the buffer 8, and outputs the address read from the row table area of the buffer 8.
The address of each screen attribute data or character data in the MA line is generated. The selector 23 receives the address signal from the row table address generation circuit 21 and the reproduced address generator! according to the timing signal. The address signals from 822 are selectively switched. Buffer A receives character codes from the character data read from the display data area of playback buffer 8 and sends them to display controller 16. Buffer B also receives screen attribute data read from the display data area, character attribute codes in character data, and line attribute codes read from the line table area, and supplies them to the display controller 16. This bus controller 15 also has basically the same configuration and functions as existing bus controllers.

FIG. 4 shows the configuration of the display controller 16 in a block diagram. Display controller 1
6 has a character code latch 24 that receives a character code of character data supplied from the bus controller 15, and an attribute code latch 25 that receives a character attribute code or a line attribute code. The output of character code latch 24 is converted into an address signal by character generator address generation circuit 26 and applied to character generator 20. In the character generator 20, font data is read out according to the address signal. The output of the attribute code latch 25 is also provided to an attribute controller 27 which converts the font data supplied from the character generator 20 according to its specified attributes, e.g., the scan line position specified by the character attribute code. Underline. Shift register 28 converts the parallel bits supplied from attribute controller 27 into serial bits and supplies them to selector 30 in color controller 29 .

The color controller 29 includes a foreground color control section 31 and a background color control section 32, and includes a foreground color control section 31 and a background color control section 32.
1 has a pallet mechanism 19.

The color specification data from the foreground color control section 31 and the background color control section 32 are supplied to a selector 30 via a blue forcing circuit 33 and a black forcing circuit 34, respectively, and the selector 30 converts the data into serial bits from the shift register 28. The signal is added to the video signal controller 35. The video signal controller 35 supplies a video signal colored in the specified color to the CRT display device for display. Note that the blue forcing circuit 33 and black forcing circuit 35 in the color controller 29 are controlled by the timing signal from the timing signal generator 14, and can selectively generate a color designation signal forced to blue or black. be.

The DMA controller 17 DMA transfers the palette data among the screen attribute data supplied from the bus controller 15 to the memory of the palette mechanism 19 in the @scape color control section 31 of the color controller 29, and transfers the setting data to the I10 register 18. Transfer it to and set it.

Next, the operation of this display control device will be explained. First, the operator inputs that the display device connected to this display controller is to be used by two host computers, and that it is connected to the timing signal generator 14.
is set to Therefore, the timing signal generator then generates timing signals for display control by the two split screens. A row table with starting addresses and row attribute data for DMA rows and display data rows is written. Furthermore, display data areas 9 and 1 specified by the DMA row start address in this row table
Screen attribute data for each split screen is written in the 0 row position (DMA row). Note that this screen attribute data includes color palette data as well as setting data such as the background color of the screen, the color of the cursor, and the maximum number of display lines.

In this way, the row table area 11 of the playback buffer 8
When the row table is written in and 12 and the screen attribute data is written in display data areas 9 and 10, the preparation state is reached.

When the host computer 1 or 2 supplies character data to be displayed to the buffer of the communication control device 3, the MPU
13 writes the character data into the display data area 9 or 10 according to the line table in the line table area 11 or 12 in the reproduction buffer 8.

In order to display the character data written in the display data area on the display device, the bus controller 15:
First, during the last horizontal retrace period during the vertical scanning retrace period, the DM in the row table area is
Access the start address of line A. According to the accessed DMA row start address, the DMA row in the display data area 9 is read out during the horizontal display period following the horizontal retrace period. The screen attribute data in the DMA row thus read out is supplied to buffer B, and further supplied to the DMA controller 17 in the display controller 16 in accordance with a predetermined timing signal. D
Of the supplied data, the MA controller 17 stores the setting data in the I10 register 18 and the palette.
The data is transferred to the memory of the pallet mechanism 19 by DMA.

As described above, screen attribute data is stored in I10 register 1.
8 and loaded onto the pallet mechanism 19. In this way, this loading operation is performed during the horizontal display period following the horizontal retrace period, and is performed at high speed using the DMA mechanism, so it is possible to load a large amount of screen attribute data of 50 bytes or more. Become. Also, since the screen attribute data loading operation for this upper split screen is performed during the horizontal display period during the vertical retrace period, the display controller 1
6 to the display device 5 is suppressed. Therefore, even though this loading operation is performed during the horizontal display period, no scanning signal of character data is displayed on the screen.

For example, when the screen attribute data for the upper split screen 6 is loaded into the display controller 16 in this way, the bus controller 15 selects the next address according to the address signal in the row table address generation circuit 21 set by the timing signal. During the horizontal retrace period, the first row character data start address and row attribute data in the row table area 11 of the buffer 8 are read out. It is applied to the attribute controller 27 via the attribute latch 25.

Further, during the horizontal display period following the horizontal retrace period, the bus controller 15 reads out the first line character data in the display data area 9 according to the read first line character data start address, and selects among the character data. Give the character code to buffer A and the character attribute code to buffer B. Furthermore, the data in these buffers A and B are provided to latches 24 and 25 of display controller 16. The output of latch 24 generates font data from character generator 20 via character generator address generation circuit 26. The font data is converted by the attribute controller 27 according to the attribute code of the latch 25 and sent to the color controller 29 via the shift register 28.
given to. Therefore, the font data is colored and output to the display device 5, and the upper split screen 6
The text is displayed above. During this character display operation, the blue forcing circuit 33 and the black forcing circuit 34 are selectively activated by the signal from the timing signal generator 14, so that the characters on the screen are displayed as in the case of conventional color character display. In the summer, depending on the screen attribute data in the 10 register 18 and the control of the palette mechanism 19, the image is displayed in color or with a blue foreground and a black background.

Once the upper split screen 6 has been displayed, the timing signal generator 14 uses the row table address of the bus controller 15 to generate the DMA row start address for the lower split screen 7 during the next horizontal blanking period. The generator circuit 21 is controlled. Accordingly, the screen attribute data for the lower split screen 7 is loaded into the I10 register 18 and palette mechanism 19, as described above. During this loading operation, the blue forcing circuit 33 or the black forcing circuit 34 is selectively activated by the signal from the timing signal generator 14 as described above, and therefore the scanning line during this period is forcibly displayed in blue or black. be done. That is, a dividing line is displayed between screens 6 and 7. Thereafter, characters are displayed on the lower split screen 7 in the same way as the characters are displayed on the upper split screen 6 described above.

FIG. 5 shows the timing of the operations of the bus controller 15 and display controller 16 in the load operation described above, and those skilled in the art will easily understand the present invention without further detailed explanation. It is considered possible.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a display control device implementing the present invention;
FIG. 2 is a diagram showing the configuration concept of a reproduction buffer in the display control device, FIG. 3 is a block diagram of a bus controller in the display control device, and FIG. 4 is a block diagram of a display controller in the display control device.
FIG. 5 is a diagram showing the timing of data read by the bus controller and data transfer by the disk controller.

Claims (4)

[Claims] (1) In a display control device for controlling a scanning display device so that character data from multiple independent applications is displayed on vertically divided split screens, the attributes of each split screen are displayed. a first storage means for storing screen attribute data and character data to be displayed on each split screen line by line; and storing a line address of the screen attribute data and a line address of the character data in the first storage means. a second storage means for reading a row address from the second storage means during a horizontal retrace period, and reading data from the first storage means according to the read row address during a horizontal display period following the horizontal retrace period; a bus controller for reading, during the horizontal display period, setting screen attribute data read by the bus controller in a register, and setting character data read by the bus controller in the register; A display control device comprising: a display controller that processes screen attribute data and supplies the data to the display device. (2) The second storage means stores row attribute data of the row along with the row address of the character data, and the bus controller reads the row attribute data during the horizontal blanking period, and the bus controller reads the row attribute data during the horizontal retrace period, and The display control device according to claim 1, characterized in that the display control device is supplied with a display control device. (3) The display controller controls the display device to display a screen dividing line during the horizontal display period.
The display control device described in Section 1. (4) The display control device according to claim 1, wherein the display controller sets the screen attribute data in a register using a DMA mechanism.