JPH02210840A - Field-effect transistor - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a field effect transistor in which an active layer and two buried layers are formed by epitaxial growth.

[Conventional technology]

Compound semiconductor MES (metal semiconductor: M
etal Sem1conductor ) F' E
T (field effect transistor: Fi
An example of providing two buried layers under the active layer in order to suppress the short channel effect and improve the pinch-off characteristics in the 14effect Transistor is disclosed in Japanese Patent Publication No. 81-4352.

and JP-A-60-27173.

[Problem to be solved by the invention]

By the way, the active layer provided with two buried layers has a problem in that the impurity density in the active layer becomes high and carrier mobility decreases. This is because, in addition to normal donor impurities for generating carriers, the active layer contains acceptor impurities diffused from the buried two layers into the active layer and donor impurities added to compensate for the acceptor impurities.

For example, the electron mobility of undoped GaAs is about 8500 cm"/V-Ste at room temperature, but it is about 4200 cm"/V-8 in the FET (7) active layer, and in the buried double layer tM. It drops to about 3300aIz/v-8. In F'ET, where both the active layer and the buried two layers are thinned, the thickness is approximately 1500.
In some cases, it may be as low as ~2500 layers m''/V-8.

A decrease in mobility poses a problem because it hinders the speeding up of FETs. However, conventionally, even if the buried double layer reduces carrier mobility, if the gate length can be shortened by the short channel effect suppressed by the buried double layer, the FET can be made faster, so no countermeasures have been taken to solve this problem. I hadn't done it.

That is, the buried two layers have the effect of suppressing the short channel effect and making it possible to shorten the gate length.

Shortening the gate length increases the speed of the FET, and even if the buried double layer reduces the mobility, the overall speed of the FET can be increased, so the decrease in mobility has been ignored in the past.

However, it is clear that higher mobility is preferable in order to increase the speed of an FET.An object of the present invention is to provide an FET with improved carrier mobility in an active layer provided with two buried layers. It is in.

[Means to solve the problem]

In the present invention, an undoped layer is inserted between the active layer and the buried two layers in order to improve carrier mobility.

[Effect]

The interface between the active layer and the buried two layers is depleted by the pn junction, but since it contains pJPJ acceptors and nM donors, the impurity density is high and carrier mobility is low. By using an undoped layer with high mobility, the speed of the FET can be increased.

A pn junction generates a pn junction appearance and acts as a parasitic capacitance for the FET, but a structure in which an undoped layer is inserted between the layers can reduce the parasitic capacitance.

However, if the thickness of the undoped layer is large, the active layer and the buried layer 2
The undoped layer has no effect due to the diffusion of impurities from the layer, and if it is thick, the effect of the buried two layers on the active layer is lost and the short channel effect increases, so the thickness of the undoped layer is preferably 5 to 20 nm. .

The on-state operation of F E 'l' can be divided into a linear region and a saturated region. In the linear region, most of the carriers flow in the active layer, so the present invention has no effect; in the saturated region, the current is limited to a nearly constant value by the depletion layer extended by the electric field between the gate and drain; The effectiveness of the present invention is compromised when the layer extends to the bottom of the channel (where the gate voltage is slightly greater than the threshold voltage). The situation at this time is shown in Figure 4, (a) is the conventional FET, (b)
This is the case in the present invention. Arrows indicate the flow of electrons.

In (a), electrons flowing from the source are pushed to the interface between the active layer and the second layer and head toward the drain.

In (b), there is an undoped layer in the middle, and electrons in the undoped layer can move at high speed.

Figure 5 shows the F E 'l' characteristic, the threshold voltage is approximately Ov.
It is. (a) is the relationship between drain current and drain voltage,
(b) shows the relationship between drain current and gate voltage, and (C) shows the relationship between conductance (gm) and gate voltage. In both cases, the broken line represents the conventional FET, and the solid line represents the FET of the present invention.

(a) has the effect of increasing the saturation current in a region where the gate voltage is low, and (b) has the effect of increasing the change in the rise and fall of the current near the threshold. The performance of a FET is determined by its ability to supply current to the load.
According to the present invention, performance can be improved when the gate voltage is near the threshold value. (C) shows the situation.

[Example] Hereinafter, as an example of the present invention, GaAsMESFE'
This will be explained with reference to FIG. 1, taking l' as an example.

It is possible to use other compound semiconductors, and MESF
In addition to E”r, J (junction; Junctlo
n) F E '1'', D M T (Doped Channel Metal Insulator Transistor: Do
ped-channel Matal In5ulat
IO (Insulated Gate)
It is also applicable to FET etc.

FIG. 1 shows an example in which the n0 layer 5 is formed by ion implantation, and FIG. 2 shows an example in which it is formed by epitaxial growth. In both cases, 1-GaAs is placed between the active layer 2 and the second layer 4.
A feature of the present invention is that 3 is sandwiched by about 7 nm.

The reason why the thickness of 1-GaAs3 is 7 nm is 2X 10
When the n-layer of "cm-" and the p-layer of 3x101' (1m-8) are in contact, the thickness of the depletion layer extending toward the n-layer side is about 7 nm.
That's why. At this time, the thickness of the depletion layer extending toward the p-layer side is approximately 25 nm. Also, if the undoped layer and the above n
The depletion layer extending toward the n-layer side when the two layers are in contact with each other is almost negligible.

The manufacturing process will be explained using the case of FIG. 1 as an example.

MBE (Molecular beam epitaxy: Mo1e
A buffer layer 1 of i-GaAs was deposited to a thickness of approximately 700 nm and Be ions were deposited at approximately 3X on a semi-insulating GaAs substrate using
IO"cm-" doped p-G a As 4
about 300 nm, i-G a As 3 about 7 nm,
Approximately 2 x 10"arm-" Si ions as active layer
About 30 nm of doped n-GaAs 2 is grown.

Leave only the active layer of the FET, or the part that will become the diode or resistance layer, and wet-etch the other regions with a mixed solution of hydrofluoric acid and hydrogen peroxide (1:2) until the p-GaAs4 is completely exposed. I do.

On top of this, approximately 200 nm of WSi is applied as a heat-resistant gate.
After deposition by sputtering, the gate 6 is processed by lithography and dry etching.

It is possible to use other materials for the gate 6, and it is also possible to form a composite gate made of several materials.

After depositing about 150 nm of 5iOz, Sx was deposited using 5ins of the sides as a mask, leaving SiOz only on the sides of the gate.
The present invention is completed by implanting + ions under the conditions of 75 keV 5 × 10 "cm-" and performing activation annealing at 800° C. for 15 minutes to form an ohmic electrode (AuGg/N1) 7.

Other embodiments of the invention are shown in FIGS. 2 and 3.

In FIG. 2, using the 5ift sidewall of the gate as a mask, n
Layer--GaAs5 was selectively epitaxially formed by MOC'Vl) (metal-organic chemical vapor phase epitaxy).

After forming the n10 layers, the ohmic electrode 7 is formed.

Figure 3 shows another semiconductor 8 with a large energy gap between the gate 6 and the active layer 2 in order to improve the Schottky characteristic.
It has a heterojunction structure with the two sides sandwiched together. The manufacturing process will be explained below.

i-GaAs is grown by MBE on a semiconductor substrate.
1 to about 700 nm, Be-doped (3X1018a++-
”) p-G a As 4 at about 300 nm, i
G a a! ! 3 to about 7 nm, Si-doped (3X1
0"am-") n-G a As 2 to about 15 nm
, undoped AJiGaAs8 is grown to a thickness of about 11 nm,
The parts other than the active layer are made of p-GaA by wet etching.
s4 is exposed, the gate 6 is processed, and about 150 nm of SiOx is deposited by normal pressure CVD (chemical vapor deposition). This 5iOz was removed by dry etching leaving only the side of the gate, and the 5ins remaining on the side of the gate.
Cut undoped AQGaAs 8 using as a mask,
Expose the n-GaAs2, and remove the n-layer-GaA by MOCVD.
The FET according to the present invention in the case of a heterojunction is completed by forming s5 by selective growth, depositing an ohmic electrode 7, and performing wiring.

Undoped A Q G a A s 8 is another semiconductor,
Alternatively, it is possible to use an insulator, and it is also possible to remove the undoped A jl G a Am 8 using the gate 6 as a mask instead of the 5 ins on the side surface of the gate.

Also, undoped A Q Ga As 8 is i-G
A homojunction may be used as aAs8. In this case, 1-GaAs8 must be made as thin as 1 to 3 nm, but it improves the Schottky characteristics of the gate and acts as a protective film for the active layer. , it becomes possible to make the concentrated layer thinner and highly concentrated without deteriorating the Schottky characteristics of the gate.

In another embodiment of the invention, the device structure is the same as in FIG. 2, with the active layer 2 being p-GaAs.

P-channel Ga using iGaAg for undoped layer 3
A s M E S F E T is mentioned.

The hole mobility of G a A a at room temperature is about 420 co”
/V-8, but Ga is 1900cm+”/V-8, which is more than 4 times faster.
The so-called HEMT (high-speed conductive layer) is used for the following reasons: 1. Dimensional electron (hole) gas is not used, and the conductive layer 2 is not an electron (hole) supply layer to the channel, but is a channel.
Electron mobility-transistor: light
IElectron NobilityTransi
stor), it is a MESFET, and only when operating in the saturation region, holes pass through 1-GaAsa, which has high mobility, to improve conductance. In this case,
The buffer layer 1 is formed of n-GaAs, and the source and drain 5 are formed of p-layer GaAs.

〔Effect of the invention〕

The operation of FET in the saturation region is governed by the saturation velocity of electrons. Electrons reach a saturation speed near the drain end of the gate, but the depletion layer from the gate extends the longest in this region, and the electrons in this region pass through the interface between the active layer and the p layer. Making the region an undoped layer has the effect of increasing the saturation velocity of electrons and improving the conductance of the FET.

Also, the parasitic force generated between the active layer and the buried two layers is as follows.

An undoped layer has the effect of making it smaller. It is also possible to use other semiconductors with high mobility in the undoped layer, which has the effect of further improving conductance.

[Brief explanation of the drawing]

FIGS. 1 to 3 show an embodiment of the present invention.
FIGS. 4a and 4b are cross-sectional views of an element portion for explaining the present invention in detail, and FIG. 5 is a characteristic diagram of the MESFET for explaining the present invention in detail. ■...Semiconductor substrate or buffer layer, 2...Active layer (n-GaAs), 3-i-G
a As, 4-p -G a As, 5-n+-G
aAs, 6... Gate electrode, 7... Source, drain electrode, 8... un-.AQGaAs or insulator. 4th entrance 1f-1

Claims (1)

[Claims] 1. In a field effect transistor having an active layer on a semiconductor substrate or a buffer layer, and an impurity layer having an opposite conductivity type below the active layer, the active layer and the impurity layer have an opposite conductivity type. A field effect transistor characterized in that it has a semiconductor layer that is not intentionally doped between impurity layers. 2. In a field effect transistor having an active layer on a semiconductor substrate or a buffer layer, and an impurity layer having an opposite conductivity type below the active layer, the above-mentioned structure is provided between the active layer and the impurity layer. A field effect transistor characterized by having another semiconductor layer having a higher carrier mobility than an active layer. 3. The field effect transistor according to claim 1 or 2, further comprising a semiconductor layer which is not intentionally doped between the active layer and the gate electrode provided on the active layer.