JPH02201965A - Semiconductor device and its manufacturing method - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [1'7i! TECHNICAL FIELD The present invention relates to an insulated gate field effect semiconductor device (hereinafter abbreviated as IG-FET) having a thin channel region and a method for manufacturing the same.

[Prior art] As an example of a conventional IG-FET, an n-channel type IG-FET is an example of a conventional IG-FET.
The case of FET will be explained below.

In the case of a p-channel type IG-FET, the n-type semiconductor and the p-type semiconductor may be interchanged, the holes and electrons may be interchanged, and the potential rise and fall may be interchanged.

The maximum depletion layer width W in the channel region of an IG-FET formed on an infinitely large semiconductor substrate. 1x is expressed by the following equation when no bias is applied to any of the source electrode, drain electrode, and semiconductor substrate.

Lax-(24s ” εo'φt/q N) ”2(
1) Here, 5 in Ks is the relative dielectric constant of the semiconductor, ε. is the vacuum conductivity, q is the electron charge, φ is the difference between the Fermi level and the intrinsic Fermi level, and N is the active dopant density.

In recent years, the thickness of the semiconductor layer in the channel region has been made smaller than Wmax in equation (1) for the purpose of increasing the mutual conductance (the value obtained by differentiating the drain current with the gate voltage) of IG-FETs and shortening the channel. Several structures have been proposed in which the entire channel region is depleted. The first example is
Shown in FIGS. 2 to 14.

Figures 12(a) and (b) show 5ol (Silico
A semiconductor layer having a thickness D smaller than the maximum depletion layer width Wmax is formed on an insulating layer 12 made of silicon oxide disposed on a semiconductor substrate 11 made of Tokyo Crystal Silicon using the Insulator technology. T inside
G-FET source region6. Channel region 3. The drain region 7 is built in (Reference: IEICE Technical Report (Nobu Yoshimi et al., Vol. SDM)
87-154, pp, 13-18)). 4 is a gate oxide film made of silicon oxide; 5 is a gate electrode made of polysilicon; and 15 is a gate electrode extension part.

D? As a result of making W+max smaller, the channel region 3 is completely depleted, and the total amount of charges in the depletion layer is q −D −
It can be suppressed to H. Due to this effect, the electric field in the vertical direction of the channel is relaxed, carrier mobility increases, and IG-
The transconductance of the FET increases.

Furthermore, even if the channel surface potential increases from the source region 6 to the drain region 7, the total charge l in the depletion layer does not increase, so the degree of decrease in induced carriers is infinitely large on the semiconductor substrate. It is smaller than that of an IG-FET formed in This effect increases D, the saturated drain current, and therefore the transconductance of the TG-FET.

Furthermore, since the total amount of charge in the depletion layer is constant, the depletion layer capacitance is approximately zero. Due to this effect, D has a small subthreshold coefficient (a value obtained by differentiating the logarithm of the drain current with respect to the gate voltage), and the on/off ratio of the drain current becomes large.

In addition to the above, in the structure of FIG. 12, as a result of reducing D, the channel region 3 has a small D, and the gate voltage
5, the influence of the drain electric field on the channel region 3 is blocked by the gate electrode 8i5. This effect suppresses so-called short channel effects such as a decrease in threshold voltage and an increase in subthreshold coefficient when the channel length is set to less than a square, and enables high-performance IGs with short channel lengths.
-FET becomes possible.

However, in the structure shown in FIG. 12, the potential of the entire channel region increases due to the sum of the electric fields in the direction perpendicular to the channel.
The potential barrier between source region 6 and channel region 3 is lowered. Due to this lowering of the potential barrier, D, when holes generated by impact ionization in the vicinity of the drain flow into the source region 6, a large amount of electrons are injected from the source region 6 into the channel region 3, causing the problem of lowering the drain breakdown voltage. .

In addition to this problem, the structure of Ks shown in FIG. 12 has the problem that the crystal quality of the semiconductor layer is poor because SOI technology is generally immature.

FIG. 13 shows a structure in which a lower gate electrode 5' is added below the channel region of the IG-FET shown in FIG.・“Solid-state electronics J
(T, Sekigawa and Y, Hayas
hi,5solid-5tateElectronics
, Vol, 27, pp, 827-p28, 19
84) ).

In the structure of FIG. 13, the channel region 3 is connected to the upper gate h T
K because it is sandwiched between the a electrode and the lower gate electrode 5'
sThe shielding effect of the drain electric field is even greater than the structure shown in Figure 12D, and the high performance IG-FE has a shorter channel length.
T is realizable.

Further, by electrically connecting the two gate electrodes 5 and 5', D, the gate electrodes 5 and 5' and the channel region 3
The capacitance between the two is doubled, and the mutual conductance is also doubled.
Can be doubled.

Furthermore, by similarly electrically connecting the two gate electrodes 5 and 5', the upper limit of D at which the entire channel region 3 can be depleted is reduced to 2, which is twice that of the structure shown in FIG.
・Wllllllll can be used. As a result, difficulties in manufacturing processes such as thinning of semiconductor layers can be alleviated.

However, the structure shown in FIG. 13 has exactly the same problem as the structure shown in FIG. 12. That is, there are problems of a decrease in drain breakdown voltage and a problem of poor crystal quality of the semiconductor layer.

Figure 14 shows the structure shown in Figure 13 realized without using the Sol technology (Reference: "Collection of Proceedings of the 5th Applied Physics Association Conference" (Tomohisa Mizuno et al.).

Vol.2. p. 592, 1988)). In this case, since the semiconductor layer can be fabricated by processing the bulk crystal, the problem of poor crystal quality does not occur.

Furthermore, in the structure of FIG. 14, since the channel region 3 is connected to the semiconductor substrate 1, holes generated by impact ionization near the Ks drain region 7 flow into the semiconductor substrate 1. Therefore, the problem of lowering the drain breakdown voltage does not occur.

However, the structure shown in FIG. 14 has a problem in that since the current flows in a direction perpendicular to the surface of the semiconductor substrate 1, a special layout different from that of an integrated circuit using a normal IG-FET is required. For example, the inability to use a method to reduce the area occupied by a circuit by sharing the source and drain regions between multiple elements not only increases design effort but also reduces the overall area of the integrated circuit. It will increase it.

Furthermore, in the structure of FIG. 14, since the source regions 6 and 6' are in contact with the semiconductor substrate 1 over a wide area, there is a problem in that the parasitic capacitance between them is large. In transfer gates, enhancement/enhancement type gates, enhancement/depression type gates, etc., the source region is connected to the output node, so an increase in parasitic capacitance with the substrate 1 may lead to undesirable results such as a decrease in operating speed. I don't like it.

[Problems to be Solved by the Invention] In view of the above-mentioned points, an object of the present invention is to solve the problem that the drain breakdown voltage decreases in the conventional structure shown in FIGS. 12 and 13 and the crystallization of the semiconductor layer. An insulated gate field effect semiconductor device having an appropriate structure to solve the problem of poor quality, the problem of requiring a special layout in the structure of the conventional example shown in FIG. 14, and the problem of large parasitic capacitance, and its The purpose is to provide a manufacturing method.

[Means for Solving the Problems] In the present invention, the above-mentioned problems are solved by the following means.

The problem of reduced drain breakdown voltage can be solved by creating a structure in which a portion of the channel region is in contact with the substrate semiconductor, thereby allowing holes generated by impact ionization near the drain to flow toward the substrate.

The problem of poor crystal quality of the semiconductor layer can be solved by creating an element structure in which a part of the channel region is in contact with the substrate semiconductor, in which a bulk semiconductor crystal of good quality can be used.

The problem that requires a special layout can be solved by making the direction of current flow (the direction that connects the source and drain regions) parallel to the substrate surface. This state can be achieved by creating a structure in which the channel region is in contact with the substrate along a plane including the direction connecting the source region and the drain region.

The problem of large parasitic capacitance can also be solved by determining the portion where the channel region contacts the substrate as described above and reducing the area where both contact.

That is, the semiconductor device of the present invention includes a semiconductor substrate, a semiconductor source region in contact with the semiconductor substrate, a semiconductor drain region in contact with the semiconductor substrate, a semiconductor box-shaped channel region in contact with the semiconductor substrate, and a surface of the box-shaped channel region. gate insulation; a gate electrode formed through the pattern; the box-shaped channel region is surrounded by six sides;
The surface of the box-shaped channel region is in contact with the source region, the second surface of the box-shaped channel region opposite to the first surface is in contact with the drain region, and the third surface of the box-shaped channel region including the direction connecting the source region and the drain region is An insulating film having a ratio of thickness to dielectric constant greater than that of the gate insulating film is formed on the fourth surface of the box-shaped channel region that is in contact with the semiconductor substrate and is opposite to the third surface. A gate insulating film is formed on the mutually opposing fifth and sixth surfaces of the region.D, the thickness of the box-shaped channel region defined by the interval between the fifth and sixth surfaces constitutes the channel region. :F-relative dielectric constant KS of conductor, dielectric constant ε0 of vacuum. Unit charge q of electron, energy difference φ2 between the Fermi level and the intrinsic Fermi level of the semiconductor forming the channel region. It is characterized in that, with respect to the active dopant density N in the semiconductor constituting the channel region, D <(4-KS·εo'φf/q N) 1/2.

The manufacturing method of the present invention includes a step of forming a first insulating film on a semiconductor substrate, selectively etching the semiconductor substrate and the first insulating film in a direction perpendicular to the semiconductor substrate surface, and etching the semiconductor substrate surface. A step of forming a convex semiconductor region having a first insulating film on the upper surface, the thickness D in the direction parallel to the first insulating film satisfying the conditions set forth in claim 1, and a surface portion of the semiconductor substrate other than the convex semiconductor region. forming a second insulating film on the side surface of the convex semiconductor region; forming a gate electrode selectively on the gate insulating film;
The method is characterized by comprising a step of introducing a dopant into the convex semiconductor region other than the portion covered by the gate electrode to form a source region and a drain region.

Further, the manufacturing method of the present invention selectively etches the semiconductor substrate in a direction perpendicular to the semiconductor substrate to form a convex structure whose thickness D in a direction parallel to the surface of the semiconductor substrate satisfies the conditions set forth in claim 1. A step of forming a semiconductor region, a step of forming an insulating film on the top surface of the convex semiconductor region other than the side surface of the convex semiconductor region and a surface of the semiconductor substrate, and a step of forming a gate insulating film on the side surface of the convex semiconductor region. and a step of selectively forming a gate electrode on the gate insulating film, and a step of introducing a dopant into the convex semiconductor region other than the portion covered by the gate electrode to form a source region and a drain region. It is characterized by:

[Function] According to the present invention, there are advantages of a thin layer IG-FET in which the entire Ks channel region is depleted without the problem of lowering the drain breakdown voltage.
i.e. an increase in transconductance.

It is possible to reduce the subthreshold coefficient, suppress the short channel effect, etc.

In the present invention, since a high-quality bulk semiconductor crystal can be used, the device characteristics are good.

In the present invention, since the direction in which current flows is parallel to the substrate surface, it is possible to arrange elements at high density.

In addition, according to the present invention, the area where the element is in contact with the substrate is small, and the increase in parasitic capacitance is also small.

[Example] Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

In the embodiments shown below, silicon (hereinafter abbreviated as Si) is used as the semiconductor material, but the present invention is not limited to Si, and the present invention can also be applied to germanium (Ge), gallium arsenide (GaAs), etc.
Needless to say, the present invention can also be applied to other semiconductor materials such as indium phosphide (InP). The oxide film, nitride film, etc. used in the embodiments may also be made of other materials as long as they are functionally equivalent. Metal also refers to materials with metallic properties in general, and highly doped semiconductors, silicides, etc. also fall into this category. Furthermore, in the following, we will mainly focus on n-channel type, or it is of course possible to create p-channel TG-FETs by using dopants of opposite polarity. It also sources dopants for the channel region.

If the polarity is the same as that of the drain, it is possible to perform an accumulation type operation instead of a numerical inversion type operation, but this distinction will not be specifically explained below.

Example 1: A first embodiment of the present invention is shown in FIGS. 1(a) to (e).

FIG. 1(a) is a planar layout diagram viewed from the direction perpendicular to the substrate surface, FIG. 1(b) is a side view with the interlayer insulating film 8 removed, and FIG. 1(c) is a cross-sectional view taken parallel to the substrate surface along line c-c' in FIG. 1(b), and FIG.
d) is a cross-sectional view cut perpendicular to the substrate surface along line a-a' in Fig. 1(a), and Fig. 1(e) is a cross-sectional view taken along line bb-b in Fig. 1(a).
FIG. Figure 1 (
Active S1 in the legend shown in tl) refers to the source region,
Refers to the channel region and drain region together. Poly S1
D is highly doped polycrystalline Si, which is used for the gate electrode 5 and the gate electrode extension portion 15 in this embodiment. The contact hole is the source region 6.
Drain region7. These are holes made in the interlayer insulating film 8 to electrically connect the gate electrode extension portions 15 to the metal wiring layers 26, 27, and 25, respectively.

As shown in FIGS. 1(a) to (e), KsI of this embodiment
The G-FET is formed in a thin plate-shaped Si 9 having a height H1 and a thickness D, which is arranged perpendicularly to a single-crystal Si substrate 1. That is, a source region 6 and a drain region 7 are provided at both ends of a thin plate-shaped Si 9 that is in contact with the substrate 1 and arranged perpendicularly to the substrate 1, and a gate insulator made of Si oxide is provided on the sides of the central portion. 4, an insulating film 14 having a ratio of thickness to dielectric constant larger than that of the gate insulating film 4 is formed on top of the insulating film 14, and the gate insulating film 4 and the insulating film 14 are
A gate electrode 5 made of poly-Si is provided covering it (FIG. 1(C)).

(d)) A metal wiring layer 25 is connected to the electrode extension portion I5 of the gate electrode 5 (see FIG. 1(d)).

A metal wiring layer 2 is provided in the source region 6 and drain region 7.
6 and 27, respectively (see FIGS. 1(c) and (e)). Reference numeral 2 denotes a field oxide film for isolation between elements, for example an oxide S1 film D, and the thin plate-shaped Si 9 described above is in contact with the substrate 1 through an opening formed in this film 2.

With the above structure, the box-shaped channel region 3 defined by the gate oxide film 4 is surrounded by six faces D, the first face of which is in contact with the source region 6, and the first face facing the first face. The second surface thereof is in contact with the drain region 7. The third surface including the direction connecting the source region 6 and the drain region 7 is the substrate 1
is in contact with On the fourth surface facing this S3 surface,
An oxide film having a thickness to dielectric constant ratio greater than that of the gate oxide film 4 is formed, and the gate insulating film 4 is formed on the fifth and sixth surfaces facing each other. As a result, the plate-like S
If the threshold voltage of the top surface is sufficiently larger than the threshold voltage of the side surface, the phenomenon in which the subthreshold characteristics of the formed element deteriorate due to the influence of the channel current on the soil surface is prevented.

The thickness D of the box-shaped channel region 3 defined by the distance between the fifth and sixth surfaces is D<(4.5.60.φ/q N ) I/2. Here, 5 is the specific conductivity of the semiconductor constituting the channel region 3, co is the permittivity of vacuum, q is the unit charge of electron, and φ is the Fermi level and intrinsic Fermi level of the semiconductor constituting the channel region 3. , N is the active dopant density in the semiconductor constituting the channel region 3.

The thickness D of the plate-shaped Si is made thin enough so that the depletion layers extending from both sides of the plate-shaped Si 9 are in contact with each other (D<
2.W, l1ax), the entire channel region 3 is depleted. As a result, the electric field in the direction perpendicular to the channel surface is relaxed and carrier mobility increases.

In addition, since the total amount of charge in the depletion layer is fixed, even if the channel surface potential increases from the source region 6 to the drain region 7, the degree of decrease in induced carriers is limited. , thus increasing the saturated drain current.

Similarly, since the total charge in the depletion layer is fixed,
The depletion layer capacitance becomes almost zero, and the subthread and threshold coefficients become small.

Due to the above effect of depletion of the channel region, the IG-FET of this example has a large mutual conductance and
It has a large current on/off ratio and has high performance.

Furthermore, since the Ks channel region 3 is sandwiched between the Ks channel region 3 and the D1-electrode 5, the influence σ of the drain electric field hardly affects the channel region. For this reason, the short tea tree effect is prevented! ! A thin and high-performance element is realized.

Further, as can be seen from the cross-sectional views of FIGS. 1(d) and 1(e), source region 6 of the IG-FET of this embodiment is shown as D. Channel region 3 and drain region 7 are in contact with Si substrate 1 at the bottom of each region. As a result, holes generated by impact ionization near the drain quickly flow to the Si substrate, 1, so in the case of an IG-FET on a sor in which the active Si region is electrically floating, the drain No drop in pressure resistance occurs.

Furthermore, since the width of each region in contact with the Si substrate 1 is very narrow, less than D, the parasitic capacitance between the substrate and the substrate is small, and the TG-FET of this example can be expected to operate at high speed. .

In addition, the IG-FET of this example has a plate-like Si9
Since the side surface of the channel is used as a channel surface, even if the planar dimension seen from the direction perpendicular to the substrate surface is small, the effective channel width can be increased, and the degree of integration can be improved. Furthermore, the direction in which the current flows is parallel to the substrate surface. The design of the button may be the same, and there are fewer difficulties in designing the button.

Figure 2 (a), (b) Ks A plan layout diagram of the second embodiment in which a plurality of elements shown in Figure 1 are connected in parallel, and a.
-a' line and bb' line sectional views are shown, respectively. Here, a plurality of thin plate-shaped Si
9, and each plate-like Si 9 is provided with an IG-
Each source region of the FET6. Drain region 7 and gate electrode 5 are commonly connected to metal wiring layers 26, 27 and 25, respectively.

In the IG-FET of the present invention, the effective channel width is 2.
H → D, D and D are depletion conditions (O〈2・
Lax), it is not possible to arbitrarily increase the effective channel width by increasing the planar element dimensions as viewed from the direction perpendicular to the substrate surface. However, by adopting the structure shown in FIG. 2, an element with a large channel width can be obtained. Moreover, the IG-
Since the FET uses the side surface of the Si9 plate as a channel surface, by connecting multiple Si9 plates in parallel at intervals close to Ks as shown in Figure 2, a large number of Si9 plates can be formed in a small planar area. A device having a large effective channel width can be realized.

Next, referring to FIGS. 3 and 4, an embodiment of the manufacturing method of the present invention will be described for manufacturing the IG-FET of Example 1.

In this example, since an n-channel MO5FET is assumed, the starting material is a p-type Si single crystal substrate. Since the crystallographic orientation of the channel plane can be selected by changing the direction of the planar layout pattern, the orientation of the single crystal substrate can also be selected in various ways.

Figures 3(a) to (h) and Figures 4(a) to (h)
2A and 2B show cross-sections taken along line cc' and a-a', respectively, and the manufacturing process will be explained step by step using these cross-sectional views.

(1) Thickness 100 to 500 on the surface of single crystal Si substrate 1
An oxide film 14 of r+m is formed by thermal oxidation, and a nitride film 62 is further formed on the oxide film 14 to a thickness of 100 to 2
00 nm was deposited. Next Ks nitride film 62. Oxide film 14
Then, directional etching was performed on the Si substrate 1 using a single resist pattern as a mask, as shown in FIG. 3(a).
Then, a convex or plate-like Si9 structure shown in FIG. 4(a) was obtained. Directional etching of the Si substrate may be done by dry etching such as RIE, but using a (110) plane Si substrate, the direction connecting the source region and drain region is set to [1].
, 1, 2], then potassium hydroxide (KOH)
Anisotropic wet etching using an aqueous solution or the like may also be used.

(2) A thin oxide film 63 was formed on the surface of the Si plate 9, and a nitride film 64 was deposited thereon with good coverage. Thereafter, directional etching was performed on the nitride film 64 and the oxide film 63 to obtain the shapes shown in FIGS. 3(b) and 4(b). Subsequently, a p-type dopant for channel cutting was introduced into the surface of the substrate 1 by ion implantation.

(3) Nitride films 62 and 64 attached around the plate-shaped Si9
Using as a mask, cover the flat part of the substrate 1 with a thickness of 200 to 6
A field oxide film 2 was formed by selective thermal oxidation by 00 nm. Next, after removing the nitride films 62 and 64 with hot phosphoric acid, a thin oxide layer @61 and 63 covering the plate-shaped Si9 is removed.
was removed to obtain the structures shown in FIGS. 3(C) and 4(c).

(4) A thin gate oxide film 4 with a thickness of 3 to 25 nm is formed on the exposed side surface of the Si plate 9 by thermal oxidation, and CV
A polycrystalline Si layer 5 is formed by depositing heavily doped polycrystalline St using the D method, and as shown in FIGS.
I removed the structure of d).

(5) The polycrystalline Si layer 5 is directionally etched using a resist batten as a mask to form the Ks gate electrode 5 and the gate electrode extension part 15 as shown in FIG. 3(e) and FIG. 4(e). Formed. At this time, in order to completely remove the polycrystalline Si5 adhering to the side surfaces of the plate-shaped Si9, even if the underlying oxide film 2.14 is partially exposed, over-etching is performed for a long time. Both membranes 2, 14 are sufficiently thick so that no problem arises. Thereafter, a source region 6 and a drain region 7 doped with plate-like Si9Ks in an n-type manner were formed using techniques such as oblique ion implantation and in-phase diffusion from a heavily doped oxide film.

(6) Depositing the interlayer insulating film 8, and flattening the surface of the insulating film by using techniques such as fluidizing the insulating film itself through heat treatment and constant-speed etch-back with the applied resist, as shown in FIG. 3(f). The structure shown in FIG. 4(f) was obtained.

(7) Ks as shown in Figure 3 (g) and Figure 4 (g)
The contact holes 65, 66 and 67 are connected to the gate electrode extension portion 15. The source region 6 and the drain region 7Ks were formed corresponding to each other.

(8) Metal is deposited in these contact holes 55, 68 and 57, and then etched using the resist pattern as a mask to form metal wiring layers 25, 26 and 27, as shown in FIGS. The structure of the IG-FET shown in Figure 4 (h) was obtained.

Next, another manufacturing method for obtaining the structure shown in FIGS. 3(c) and 4(c) will be described. FIGS. 5(a) to 5(c) show cross sections taken along line a-a' of the structure obtained in each manufacturing process.

(1) Directional etching of Si substrate as shown in Figure 5(a)
We obtain the structure shown in . Nothing is attached to the upper surface of the plate-like Si9.

(2) Forming an oxide film 63 on the surface and forming the oxide film 63
A Ks nitride film 64 is deposited on top with good coverage. after that,
These oxide film 63 and nitride film 64 are directionally etched,
The structure shown in FIG. 5(b) is obtained. The nitride film on the top surface of the plate-like St has been removed.

(3) A thick oxide film 14 is formed on the top surface of the plate-like Si by oxidation, then a field oxide film 2 is formed by selectively thermally oxidizing the planar portion of the substrate, and then a nitride film 6 and an oxide film 14 are formed. The film δ3 is removed to obtain the structure shown in FIG. 5(c).

In addition, in the IG-FET of the present invention, the height H of the plate-shaped Si9
Since it is not necessary to bury metal into a contact hole that is deeper than the above, it is desirable to use a low pressure CVD method or the like, which has excellent burying characteristics, as a metal deposition method. Decompression C
Polycrystalline Si produced by the VD method is known as a material with excellent embedding properties, so the contact hole is filled with highly doped, low-resistance polycrystalline Si, and a metal wiring layer is formed on the surface of the interlayer insulation@8. You can also connect it with A cross section taken along line bb' of the structure thus obtained is shown in FIG.

Alternatively, the polycrystalline Si of the gate electrode and the source.

When the polarities of the dopants of the drain are the same, the process can be simplified by sequentially depositing polycrystalline Si and metal and etching the two layers simultaneously as a wiring layer. A cross section taken along line bb' of the structure thus obtained is shown in FIG.

Embodiment 3: A third embodiment of the present invention is shown in FIGS. 8(a) to 8(e). FIG. 8(a) is a planar layout diagram viewed from a direction perpendicular to the substrate surface, FIG. 8(b) is a side view viewed with the interlayer insulating film 8 removed, and FIG. 8(c) is c in Figure 8(b)
Sectional view taken along line -c' parallel to the substrate surface, No. 8
Figure (d) is a cross-sectional view taken perpendicular to the substrate surface along the line a-a in Figure 8 (a), and Figure 8 (e) is a cross-sectional view of Figure 8 (a).
FIG. 3 is a cross-sectional view taken perpendicularly to the substrate surface along the line bb' inside. Active Si in the legend shown in FIG. 8(f) refers to source region 6, channel region 3, and drain region 7.
collectively refer to. Poly-Si is highly doped polycrystalline Si. In this embodiment, polySt is used for the gate electrode, Ks as a dopant diffusion source for the source region 6 and drain region 7, and lead electrodes 16 and 17 connected from these regions 6 and 7 to metal wiring layers 26 and 27, respectively. used as. In the following, the poly Si used as the lead electrode of the source region 6 will be abbreviated as source poly S1.1, and the poly Si used as the lead electrode of the rain region 7 will be abbreviated as drain poly Si.

In this third embodiment, the structure in which elements are formed in a convex or plate-shaped SiQ formed perpendicularly to the substrate surface is the same as in the first embodiment. Since D is thin, the entire channel region 3 is depleted, improving performance. (1) The basic advantages such as the channel region 3 being connected to the substrate 1 and the fact that current flows in a direction parallel to the substrate surface are the same as those of the first embodiment.

The main difference from the first embodiment is that in this embodiment, active St.
In the two steps of etching the region and etching the poly-Si for the gate electrode, the positional relationship between the active S, the gate electrode, and the contact is determined, and there is a large margin for processing variations in lithography, etching, etc. . Furthermore, in this embodiment, since contact is made with the metal wiring layer 25 directly above the active St, there is no need for a gate electrode lead-out portion, and the area can be used more effectively. Furthermore, in the first embodiment, the source contact hole 66 and the drain contact hole 67 (the ninth
Since there is no Ks etching stop layer, it was difficult to control the contact hole so that it did not reach the underlying Si substrate 1, but this problem does not occur in this example. .

This embodiment also has the advantage that the source poly 5i16 and drain poly 5i17 can be used as wiring layers on the field insulating film 2.

Below, Fig. 9(a) to (i) and Fig. 1θ(a) to (
An example of the process of manufacturing the IG-FET of the S3 example will be described step by step using i).

(1) Figures 9 (a) to (c) and Figure 10 (a) to
The steps up to the formation of the field oxide film 2 shown in (c) are shown in FIGS. 3(a) to (C) and 4(a) to (C).
) is exactly the same as the case of the first embodiment shown in .

(2) In the state shown in FIGS. 9(C) and 10(C), a thin gate oxide film 4 of 3 to 25 nm is formed by thermal oxidation, and a polycrystalline Sj 5 is doped with a high concentration by CVD on top of the thin gate oxide film 4 of 3 to 25 nm. was deposited to obtain the structures shown in FIGS. 9(d) and 10(d).

(3) Using the resist pattern as a mask, polycrystalline Si5 is directionally etched to form the portions that will become the gate electrode, source poly-Si, and drain poly-Si as shown in Figures 9(e) and 10(e). did. Thereafter, using techniques such as oblique ion implantation and solid phase diffusion from a heavily doped oxide film, the source region 6 and drain region 7 are
Three high concentration areas were formed.

(4) The interlayer insulating film 8 is deposited, and the insulating film surface is made flat by methods such as fluidization of the insulating film itself through heat treatment or constant-speed etch pack with the applied resist, and further etching of an appropriate amount of the interlayer film 8. was added to expose the upper end of the poly-Si5 to obtain the structure shown in FIG. 9(f) and FIG. 1θ(f).

(5) The gate electrode 5 was covered with a resist mask, and the gate electrode polySt buried in the portions that would become the source polySi and drain polySt was removed. Thereafter, the gate oxide film 4 formed on the source and drain regions was removed to obtain the structures shown in FIG. 9(g) and FIG. 10(8).

(6) Poly S for the source poly 5i16 and drain poly 5 i17 is added to the part where the poly St for the gate electrode has been removed.
i was deposited. Thereafter, this poly-Si was etched back to expose the surface of the interlayer film 8, resulting in the structures shown in FIGS. 9(h) and 10(h). Here, heat treatment is performed to diffuse the dopant from the source poly 5i16 and drain poly 5i17, and to diffuse the dopants from the source poly 5i16 and drain poly 5i17, which are already formed in the high concentration n' region source poly 5illi of the source region 6 and drain region 7.
and the drain poly 5i17 were electrically connected.

(7) Finally, metal wiring layers 25, 26 and 27 are deposited and processed on the Ks poly-Si 5.16 and 17, respectively, to form the IG-FET shown in FIG. I got the structure.

As explained in the first embodiment, the source poly 5i16
and drain poly 5i17 and gate electrode poly Si5
If the polarities of the dopants are the same, the above step (6
), the process can be simplified by depositing metal immediately without performing Ks etchback after depositing polySt, and then processing polySi5 and metal 25 in a stacked manner to form a wiring layer. In this case, the sectional view taken along the line a-a' is as shown in FIG. 11(a), and the sectional view taken along the line bb' is shown in FIG. 11(b).

[Effects of the Invention] As is clear from the above, in the present invention, a convex or plate-shaped semiconductor region is disposed vertically on a substrate, and in the plate-shaped semiconductor region, an active region connects a source region and a drain region. Since the structure is designed so that the narrow surface including the direction is in contact with the semiconductor substrate, the thickness of the channel region can be made thin (D〈2・W□X). It becomes possible to form on the top. As a result, according to the present invention, the problem of decrease in drain breakdown voltage does not occur, the mutual conductance is large, the subthreshold coefficient is small, the parasitic capacitance is small, the channel can be shortened, and it can be mounted more densely. A high performance TG-FET can be provided.

In addition, in the present invention, since the convex semiconductor region is formed by etching a semiconductor substrate such as single crystal Si, there is no crystal quality problem as in the conventional method, and each of the steps themselves are commonly used. Using the existing method, we can create a +G-FET without increasing the number of manufacturing steps! ! ! Can be built.

[Brief explanation of the drawing]

FIGS. 1(a), (b), (c), (d) and (e) respectively show the IG-1 of the first embodiment of the present invention.
Planar layout diagram showing FET 1 Side view with interlayer film 8 removed, sectional view taken along line CC' in FIG. 1(b),
A cross-sectional view taken along line a-a' in Fig. 1(a) and the same <b
-b' line sectional view, Figure 1 (f) is an explanatory diagram of the legend of each part in Figures 1 (a) to (e), Figure 2 (a) and (b) are shown in the first embodiment. A plan layout diagram of the second embodiment of the present invention in which a plurality of elements connected in parallel and a sectional view taken along the line a-a', FIG. 2(C) is an explanatory diagram of the representation of each part, and FIG. 3(a) to
(h) and FIGS. 4(a) to (h) are cuts taken along the C-C' line and the a-a line, respectively, during the manufacturing process of the IG-FET of the first embodiment of the present invention. 5(a) to (C) are cross-sectional views shown in FIG. 3(C) and FIG. 4(C).
) a-a′ in each step obtained by another method
6 is a cross-sectional view along line bb' of a structure obtained by another contact forming method in the first embodiment, and FIG. 7 is a structure obtained by yet another contact forming method in the first embodiment. b of
-b' line sectional view, FIGS. 8(a), (b), (c), (d) and (e) are the IG-
Planar layout diagram of FET 1 Side view with interlayer film 8 removed, c-C' line sectional view, a-a' line sectional view, and b
-b' line sectional view, Figure 8(f) is an explanatory diagram of the legend of each part in Figures 8(a) to (e), Figures 9(a) to (i) and Figures 10(a) to (i) is a cross-sectional view taken along line c-c' and line a-a, respectively, during the manufacturing process of the IG-FET according to the third embodiment of the present invention. aa and j of the structures obtained by different contact formation methods in 3 Examples, respectively.
12(a) and (b) are respectively a plan view and a sectional view along c-c' of a conventional IG-FET, and FIG. 14 is a sectional view showing an IG-FET with another conventional structure, and FIG. 14 is a sectional view showing an IG-FET with still another conventional structure. DESCRIPTION OF SYMBOLS 1... Single-crystal St substrate, 2... Field oxide film, 3... Channel region, 4.4'... Kate oxide film, 5.5'... Poly-Si for gate electrode, 6... ... Source region, 7... Drain region, 8... Interlayer insulating film, 9... Plate-shaped St. 11...Sol support substrate, 12...SOI base insulating film, 14...oxide film sufficiently thicker than gate oxide film, 15...
・Gate electrode extraction part, 16... Source region j4 extraction electrode (source poly Si
), 17... drain region extraction electrode (drain poly S
abbreviated as i), 25... metal wiring layer connected to the gate electrode, 26.
...Metal wiring layer connected to the source region, 27...Metal wiring layer connected to the drain region, 61.63...
Thin oxide film, 82.64... Nitride film that serves as an oxidation mask, 65...
- Gate contact hole, 66... Source contact hole, 67... Drain contact hole.

Claims (3)

[Claims] (1) a semiconductor substrate; a semiconductor source region in contact with the semiconductor substrate; a semiconductor drain region in contact with the semiconductor substrate; a semiconductor box-shaped channel region in contact with the semiconductor substrate; a gate electrode formed through a gate insulating film, the box-shaped channel region is surrounded by six surfaces, a first surface of the box-shaped channel region is in contact with the source region, and a first surface of the box-shaped channel region is in contact with the source region; A second surface of the box-shaped channel region opposite to the drain region is in contact with the drain region, and a third surface of the box-shaped channel region including the direction connecting the source region and the drain region is in contact with the drain region.
A surface of the box-shaped channel region is in contact with the semiconductor substrate, and an insulating film having a thickness to dielectric constant ratio larger than that of the gate insulating film is formed on a fourth surface of the box-shaped channel region opposite to the third surface. The gate insulating film is formed on fifth and sixth surfaces facing each other of the box-shaped channel region, and the box-shaped channel region is defined by an interval between the fifth and sixth surfaces. thickness D, relative permittivity K_s of the semiconductor forming the channel region, dielectric constant ε_o of vacuum, unit charge q of electrons, energy difference φ_f between the Fermi level and the intrinsic Fermi level of the semiconductor forming the channel region, For the active dopant density N in the semiconductor constituting the channel region, D<(4・K_s・ε_o・φ_f/qN)^1^/^
2. A semiconductor device characterized by: (2) forming a first insulating film on the semiconductor substrate; selectively etching the semiconductor substrate and the first insulating film in a direction perpendicular to the semiconductor substrate surface; forming a convex semiconductor region having the first insulating film on the upper surface, the thickness D in the direction parallel to the surface satisfying the condition according to claim 1; and the semiconductor substrate other than the convex semiconductor region. forming a second insulating film on a surface portion of the convex semiconductor region; forming a gate insulating film on the side surface of the convex semiconductor region; selectively forming a gate electrode on the gate insulating film; A method for manufacturing a semiconductor device, comprising the step of introducing a dopant into a convex semiconductor region other than a portion covered by the gate electrode to form a source region and a drain region. (3) A semiconductor substrate is selectively etched in a direction perpendicular to the semiconductor substrate to form a convex semiconductor region whose thickness D in a direction parallel to the surface of the semiconductor substrate satisfies the condition set forth in claim 1. forming an insulating film on the upper surface of the convex semiconductor region other than the side surface of the convex semiconductor region and the surface of the semiconductor substrate; and forming a gate insulating film on the side surface of the convex semiconductor region. a step of selectively forming a gate electrode on the gate insulating film; and a step of introducing a dopant into the convex semiconductor region other than the portion covered by the gate electrode to form a source region and a drain region. A method for manufacturing a semiconductor device, comprising: