JPH02200036A - Packet communication system - Google Patents

Abstract

PURPOSE:To improve the transmission efficiency by using a memory buffer which is used in common, a packet detecting circuit, and a memory buffer control circuit in order to avoid such a case where a packet signal is kept waiting for a time longer than the prescribed value. CONSTITUTION:A memory buffer 5 which is used in common is prepared together with a packet detecting circuit 3. A memory buffer control circuit 4 performs the conflict control of packet signals for centralized control of the packet writing/reading operations. Then the packet signal is never kept waiting within the buffer 5 for a prescribed time or longer owing to the function of the circuit 4 which controls the scale of the buffer 5 that prescribes the maximum allowable waiting time and the packet waiting time. Thus it is possible to reduce the circuit scale of a transmission controller, especially the scale of the buffer 5 in a packet communication system and to prevent the transmission of an invalid packet which is delayed by the maximum allowable delay time or more. Then, the transmission efficiency is improved.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a transmission control device for a packet communication system [Prior Art] The configuration of a conventional transmission control device for a packet communication system is shown in FIGS. Shown below. In the conventional system, a transmission control device is configured by arranging a memory buffer, a buffer control circuit, and a packet detection circuit for each channel. Here, the conventional system is described in detail, for example, in the document [Takamura, Aoki, Kuribayashi, Imai "Study of buffer control system in I5DN exchange" IEICE Technical Report 5sE86-56].

When receiving packet signals individually from multiple channels (
(Fig. 4), a node 1 that transmits packets is connected to each channel. This packet/7t sending node 1 is
Send the packet signal ■ individually. Next, the packet detection circuit 3 installed in each channel detects the presence or absence of a packet, and when detecting a packet, sends a packet detection signal ``■'' to the memory buffer control circuit 4. Next, this memory buffer control circuit transmits the write address (■) and the write signal (■) to the memory buffer 5 installed in that channel, and stores the packet. When the packet transmission is finished, the packet detection circuit outputs the packet end signal ■
is sent to the memory buffer control circuit, and storage of the packet is completed. When each memory buffer control device completes writing, it transmits a packet write end signal 0 to the read control circuit 7. The read control circuit transmits the read signal (2) to the memory buffer control device of the channel that transmitted the packet write end signal earliest.

The memory buffer control device that receives the read signal reads out the stored packet in the memory buffer of its own channel as soon as possible.
When reading out one packet is completed,
The memory buffer control circuit sends a read end signal ■ to the read control circuit. The read control circuit similarly transmits a read signal to the memory buffer control circuit of the next channel and reads the packet.

Next, when receiving a packet signal from the high-speed multiplex transmission line (Fig. 5), the demultiplexing circuit 8 first separates the divided and transmitted packet signal ■ for each channel from the high-speed multiplex transmission line 9, Reproduce as continuous signal 0. Thereafter, packet readout control is performed in the same manner as when packet signals are individually received from a plurality of channels. When reading, it is transmitted as a complete l packet [phase].

Regarding the hardware scale when using the conventional method, a packet detection circuit and a buffer memory control circuit are required for each channel. Therefore, when a large number of channels are accommodated, the total circuit scale is enormous.

[Problem to be solved by the invention]

An object of the present invention is to reduce the circuit size of a transmission control device in a packet communication system, particularly the memory buffer size, and to avoid sending invalid packets delayed by more than the maximum allowable delay time, thereby improving transmission efficiency. It is to do so.

[Means to solve the problem]

The present invention does not provide a memory buffer, a buffer control circuit, and a packet detection circuit for each channel as in the conventional system, but instead provides a single commonly used memory buffer and a packet detection circuit, and the memory buffer control circuit This is a packet communication method in a transmission system that performs competitive control of packet signals that centrally controls writing and reading of packets.

Furthermore, the memory buffer size that defines the maximum allowable waiting number and the function of the memory buffer control circuit that controls the packet waiting time are configured to prevent packet signals from waiting in the memory buffer for a predetermined period of time or more. The above are the most important features of the present invention.

〔Example〕

A first embodiment of the present invention in which packet signals are received individually from a plurality of channels and contention control of the packet signals is performed is described below.
As shown in the figure. A node 1 that transmits packets is connected to each channel. The multiplexing circuit 2 detects the presence or absence of a packet in each multiplexed channel, and the packet detection circuit 3 detects the presence or absence of a packet in each multiplexed channel.
When a packet 7 is detected, a packet detection signal ■ is sent to the memory buffer control circuit 4. The multiplexing circuit also transmits a transmission channel notification signal ■ to the memory buffer control circuit. The memory buffer control circuit determines that a packet is being transmitted to that channel based on the timing at which the packet detection signal is received and the transmission channel notification signal, and sends a write signal at the timing of every frame when the signal of that channel is transmitted. (2) and the write address (2) are output to the memory buffer 5, and the divided and transmitted packet signals are stored for each frame. When the transmission of the packet ends in that channel, the packet detection circuit detects the end of the packet and sends a packet end signal (■) to the memory buffer control circuit. The memory buffer control circuit determines that the transmission of the packet on that channel has ended based on the timing of receiving the packet end signal and the transmission channel notification signal,
The read address (■) where the packet of that channel is stored in the memory buffer and the read signal (■) are output, and the packet is read out as one complete packet [phase]. If a packet end signal of another channel is received while a packet is being read, the packet of that channel is placed in a state of waiting to be read. After reading out the packet, the memory buffer control circuit immediately reads out the packet of the channel that outputs the packet end signal first. Further, the memory buffer control circuit controls to immediately discard a packet that has been kept waiting for longer than the maximum allowable delay time, and to use the area where the discarded packet was stored as the storage area for a new packet.

FIG. 2 shows another embodiment of the present invention in the case of receiving a packet 7) signal from a high-speed multiplexed transmission line. High-speed multiplex transmission line 6
When a packet signal is received from a packet signal and packet signal competition control is performed, the direct packet detection circuit 3 detects the packet. Thereafter, packet writing and reading control is performed in the same manner as when packet signals are individually received from a plurality of channels.

〔Effect of the invention〕

As explained above, the present invention provides a single commonly used memory buffer, a packet detection circuit, a memory By using a buffer control circuit and using a circuit configuration that does not allow packet signals to wait in the memory buffer for more than a specified period of time, it is possible to significantly reduce the bird size, especially the memory buffer size, and avoid sending invalid packets. It is possible to improve transmission efficiency.

One effective application field is satellite communication systems.

The outline is shown in Figure 3. In this system, a large number of subscriber stations 31 are accommodated, and a terminal 32 is connected to each station. The control signal is in the form of a packet and is transmitted by Dch. A thick line in the figure indicates a Dch line. Control signals are transmitted and received between one base station 33 and multiple subscriber stations. Also connected to the base station is a high-speed multiplex transmission line 34 in which Dchs for the number of subscribers are multiplexed, and signals are exchanged with the call control device 3 on the exchange side. The present invention is effective for the transmission control device 36 of a base station that controls packet formats for downstream subscriber stations. 37 is a base station transceiver; 38
is the subscriber station transceiver.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an embodiment in which the present invention is applied when packet signals are individually received from a plurality of channels. FIG. 2 is a diagram showing an embodiment in which the present invention is applied when a packet signal is received from a high-speed multiplex transmission line. FIG. 3 is a diagram showing an outline of the l5DN satellite subscriber communication system. FIG. 4 is a diagram showing a configuration when a conventional method for individually receiving packet signals from a plurality of channels is applied to this device. FIG. 5 is a diagram showing a configuration when a conventional method for receiving packet signals from a high-speed multiplex transmission line is applied to this device. 1... Packet transmission node, 2... Multiplexing circuit, 3
Packet detection circuit, 4 Memory buffer control circuit, 5 Memory buffer, 6 Multiplex transmission line, 7 Read control circuit, 8 Demultiplex circuit,
9...High-speed multiplex transmission line, 31...Subscriber station, 32
... l5DN terminal, 33... Base station, 34... High-speed multiplex transmission line, 35... Exchange call control device, 36...
... Transmission control device, 37... Base station transceiver, 38.
...Subscriber station transceiver, ■...Packet signal, ■...
・Multiplexed packet signal, ■...Packet detection signal, ■
...Transmission channel notification signal, ■...Write signal,
■Write address, ■...Packet end signal, ■Read address, ■...Read signal, [phase]...Packet signal, ■...Multiplexed packet signal, @...Packet signal (continuous signal ), ■...Packet write end signal,
■...Reading end signal, ■...Packet signal Figure 2: Configuration diagram of the implementation of the present invention in the pigeon loft, which is the main cause of the present invention.

Claims (1)

[Claims] Packet signals sent individually from multiple channels,
Alternatively, in a system that performs contention control and transmits multiplexed packet signals sent through a high-speed multiplexed transmission line that multiplexes and transmits multiple channels, multiple channels are connected to a control circuit that centrally controls memory buffers. A packet communication system characterized in that a packet detection circuit is commonly used, and the memory buffer has a circuit configuration that does not allow packet waiting time longer than a certain time.