JPH02198186A - Printed wiring board shield layer inspection method and inspection means - Google Patents
Printed wiring board shield layer inspection method and inspection meansInfo
- Publication number
- JPH02198186A JPH02198186A JP1832989A JP1832989A JPH02198186A JP H02198186 A JPH02198186 A JP H02198186A JP 1832989 A JP1832989 A JP 1832989A JP 1832989 A JP1832989 A JP 1832989A JP H02198186 A JPH02198186 A JP H02198186A
- Authority
- JP
- Japan
- Prior art keywords
- printed wiring
- wiring board
- shield layer
- layer
- circuit pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000007689 inspection Methods 0.000 title claims description 9
- 238000000034 method Methods 0.000 title claims description 8
- 238000012360 testing method Methods 0.000 description 13
- 229910000679 solder Inorganic materials 0.000 description 8
- 230000015572 biosynthetic process Effects 0.000 description 7
- 230000000694 effects Effects 0.000 description 3
- 239000000758 substrate Substances 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
- H05K1/0218—Reduction of cross-talk, noise or electromagnetic interference by printed shielding conductors, ground planes or power plane
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0266—Marks, test patterns or identification means
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0097—Processing two or more printed circuits simultaneously, e.g. made from a common substrate, or temporarily stacked circuit boards
Landscapes
- Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
- Structure Of Printed Boards (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はプリント配線板に関し、特にシールド層を有す
るプリント配線板のシールド層の検査に関する。DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to printed wiring boards, and more particularly to inspection of a shield layer of a printed wiring board having a shield layer.
従来はプリント配線板の所定の回路パターン上のソルダ
ーレジスト層上に導電性インキを塗膜形成してシールド
層とする。Conventionally, a conductive ink film is formed on a solder resist layer on a predetermined circuit pattern of a printed wiring board to form a shield layer.
すなわち、第３図および第４図に示す如（、絶縁基板１
の片面に形成された回路パターン２のうちの接続ランド
３を残して回路パターン２の上側にソルダーレジスト層
４をシルク印刷により形成するとともに当該ソルダーレ
ジスト層４上偏にシールド層５を導電性インキをシルク
印刷により塗布することにより前記回路パターン２の所
要の範囲にわたってシールド層５を形成する。That is, as shown in FIGS. 3 and 4, the insulating substrate 1
A solder resist layer 4 is formed on the upper side of the circuit pattern 2 by silk printing, leaving the connection lands 3 of the circuit pattern 2 formed on one side of the circuit pattern 2, and a shield layer 5 is coated with conductive ink on the upper part of the solder resist layer 4. A shield layer 5 is formed over a required range of the circuit pattern 2 by applying the above by silk printing.
尚、図中、６は回路パターン２の接続ランド３に形成し
たスルホール、７はオーバーコート層をそれぞれ示すも
のである。In the figure, 6 indicates a through hole formed in the connection land 3 of the circuit pattern 2, and 7 indicates an overcoat layer.
上述のシールド層５のシールド効果を判定するにはシー
ルド層５の厚さと導電性とを知る必要を生ずる。しかし
、シールド層５は導電性インキのシルク印刷技法による
塗布であるため各プリント配線板においてシールド特性
のばらつきが多いが、現在では特性検査の方法がない０
通常はシールド層５の上の全面にオーバーコート層７を
印刷塗布するため検査は不可能である。In order to judge the shielding effect of the above-mentioned shield layer 5, it is necessary to know the thickness and conductivity of the shield layer 5. However, since the shield layer 5 is coated with conductive ink using a silk printing technique, there are many variations in the shielding characteristics of each printed wiring board, but there is currently no method for testing the characteristics.
Normally, the overcoat layer 7 is printed and coated on the entire surface of the shield layer 5, so inspection is impossible.
本発明の目的はプリント配線板のシールド層の検査方法
を提供し、個々のプリント配線板のシールド層の特性を
プリント配線板自体に影響させずに検査可能とするにあ
る。An object of the present invention is to provide a method for inspecting the shield layer of a printed wiring board, and to enable inspection of the characteristics of the shield layer of each printed wiring board without affecting the printed wiring board itself.
〔課題を解決するための手段］
上述の目的を達するための本発明によるプリント配線板
のシールド層検査方法は、プリント配線板の回路パター
ン上にシールド層を施す場合に、プリント配線板内に独
立したチェックランドとこれに連通したシールド層回路
を上記シールド層と同時に形成し、プリント配線板の基
板完成後にシールド層の性能を検査する。[Means for Solving the Problems] A method for inspecting a shield layer of a printed wiring board according to the present invention in order to achieve the above-mentioned object, when a shield layer is applied on a circuit pattern of a printed wiring board, A check land and a shield layer circuit connected thereto are formed at the same time as the shield layer, and the performance of the shield layer is inspected after the printed wiring board is completed.
本発明によるシールド屓検査手段を有するプリント配線
板は、プリント配線板の回路パターン上に施したシール
ド層を有する場合に、プリント配線板内に独立した２個
のランドと、ランド間に形成した所定寸法のシールド層
回路とを形成し、シールド層検査を可能とする。When a printed wiring board having a shield layer inspection means according to the present invention has a shield layer formed on a circuit pattern of the printed wiring board, two independent lands in the printed wiring board and a predetermined area formed between the lands are provided. This enables shield layer inspection by forming a shield layer circuit with the following dimensions.
本発明の上述の構成によって、プリント配線板の基板完
成後にプリント配線板自体に悪影響を生ずることなく、
シールド層の特性の適確な検査を行い得る。With the above-described configuration of the present invention, the printed wiring board itself is not adversely affected after the printed wiring board board is completed.
It is possible to accurately test the characteristics of the shield layer.
〔実施例］ 以下本発明の実施例を図面とともに説明する。〔Example] Embodiments of the present invention will be described below with reference to the drawings.
第１図および第２図は本発明プリント配線板の部分的な
平面図および第１図Ｂ−Ｂ拡大断面図である。1 and 2 are a partial plan view and an enlarged sectional view taken along the line BB in FIG. 1 of the printed wiring board of the present invention.
しかして、第１図のプリント配線板１０は前述した第３
図および第４図示のプリント配線板と同様に絶縁基板１
の片面に回路パターン２を形成するとともにこの回路パ
ターン２の上側にソルダーレジスト層４を介してシール
ド層５を形成することにより構成されている。Therefore, the printed wiring board 10 of FIG.
An insulating substrate 1 similar to the printed wiring board shown in the figure and the fourth figure.
A circuit pattern 2 is formed on one side of the circuit pattern 2, and a shield layer 5 is formed above the circuit pattern 2 via a solder resist layer 4.
また、かかるプリント配線板１０の形成に当たり、予め
、プリント配線板１０の所要位置に、切取孔１１を配孔
した切取部１２を介してテストピース部１３を設け、こ
のテストピース部１３上側にも前記回路パターン２の形
成と同時にテスト用のランド１４．１５を形成するとと
もにソルダーレジスト層４の形成と同時にテストピース
部１３上側のテスト用のランド１４．１５を残してソル
ダーレジスト層１６を形成し、さらに前記シールド層５
の形成に関連してテスト用のランド１４゜１５間を接続
するシールド回路１７を形成し、かつプリント配線板１
０のオーバーコート層７の形成に関連してオーバーコー
ト層１８を施すものである。Further, in forming such a printed wiring board 10, a test piece part 13 is provided in advance at a required position of the printed wiring board 10 through a cutout part 12 in which a cutout hole 11 is provided, and the test piece part 13 is also provided on the upper side of this test piece part 13. Test lands 14.15 are formed simultaneously with the formation of the circuit pattern 2, and at the same time as the solder resist layer 4 is formed, a solder resist layer 16 is formed leaving the test lands 14.15 above the test piece portion 13. , and further the shield layer 5
In connection with the formation of the printed wiring board 1, a shield circuit 17 is formed to connect between the lands 14 and 15 for testing.
The overcoat layer 18 is applied in conjunction with the formation of the overcoat layer 7 of No. 0.
すなわち、テストピース部１３におけるランド１４．１
５、ソルダーレジスト層１６、シールド回路１７および
オーバーコート層１８は、それぞれプリント配線板ｌＯ
の回路パターン２、ソルダーレジスト層４、シールド層
５およびオーバーコート層７の製造工程と同一工程にて
形成する。That is, the land 14.1 in the test piece portion 13
5, the solder resist layer 16, the shield circuit 17 and the overcoat layer 18 are each printed wiring board lO
It is formed in the same process as the circuit pattern 2, solder resist layer 4, shield layer 5, and overcoat layer 7.
特に、シールド回路１７の長さおよび幅については、予
めシールド回路１７の形成に使用される導電性インキ、
すなわち前記プリント配線板１０のシールド層５の形成
に使用される導電性インキの組成における抵抗値に対応
する基準設定値と比較し得る長さおよび幅（体積）例え
ば長さ１０ｍ、幅５ａｍ等のものとなるように設計して
形成するものである。In particular, regarding the length and width of the shield circuit 17, the conductive ink used to form the shield circuit 17,
That is, the length and width (volume) can be compared with the reference setting value corresponding to the resistance value in the composition of the conductive ink used to form the shield layer 5 of the printed wiring board 10, for example, a length of 10 m, a width of 5 am, etc. It is designed and formed to become something.
尚、ランド１４．１５の一部は測定を可能とする為にオ
ーバーコート層１８の形成時に一部をｎ出せしめて形成
する。Incidentally, in order to enable measurement, some of the lands 14 and 15 are formed so as to be exposed during the formation of the overcoat layer 18.
図中、３は回路パターン２における接続ランド、６はス
ルーホールである。In the figure, 3 is a connection land in the circuit pattern 2, and 6 is a through hole.
以上の構成から成るプリント配線板１０におけるシール
ド層５はオーバーコートＮ７の形成により、その特性を
測定することが不可能であるが、かかるシールド層５の
形成と同一工程、すなわち、同一形成条件（同一の組成
から成る導電性インキによる同一の条件によるシルク印
刷等）による膜厚のシールド回路１７が形成されるので
、かかるシールド回路１７の電気的な抵抗値をランド１
４゜１５を介して測定することが可能である。Although it is impossible to measure the characteristics of the shield layer 5 in the printed wiring board 10 having the above structure due to the formation of the overcoat N7, the shield layer 5 is formed in the same process as the formation of the shield layer 5, that is, under the same formation conditions ( A shield circuit 17 with a film thickness is formed using conductive ink of the same composition under the same conditions (silk printing, etc.), so the electrical resistance of the shield circuit 17 is determined by the land 1.
It is possible to measure through 4°15.
従って、この測定値を予め同一組成の導電性インキによ
り形成された所定の膜厚、長さ（体積）における基準設
定値と比較することにより、プリント配線板１０におい
て形成されたシールド層５の特性を間接的に検知するこ
とができる。Therefore, by comparing this measured value with a standard set value at a predetermined film thickness and length (volume) formed using conductive ink of the same composition, the characteristics of the shield layer 5 formed on the printed wiring board 10 can be determined. can be detected indirectly.
尚、テストピース部１３は必要に応じて切取部１２によ
りプリント配線板１０より切り離すことが可能である。Incidentally, the test piece portion 13 can be separated from the printed wiring board 10 using the cutout portion 12 if necessary.
〔発明の効果］
従来はプリント配線板のシールド層の特性の測定は不可
能であったが本発明によって初めて可能となった。[Effects of the Invention] Conventionally, it was impossible to measure the characteristics of the shield layer of a printed wiring board, but the present invention has made it possible for the first time.
第１図および第２図は本発明の実施例を示すプリント配
線板の部分的な平面図、第１図Ｂ−Ｂ拡大断面図、第３
図および第４図は従来のプリント配線板の部分的な平面
図および第３図Ａ−Ａ断面図である。
１・・・絶縁基板 ２・・・回路パターン３
・・・接続ランド
４．１６ソルダ一レジスト層
５．１７・・・シールド層 ６・・・スルホール７．
１８・・・オーバーコート層
１０・・・プリント配線板 １１・・・切取孔１２・
・・切取部 １３・・・テストピース部特許
出廓人 日本シイエムケイ株式会社第１図
２・・・回路パターン
３・・・接続ランド
５．１７・・・シールド層
６・・・スルホール
７・・・オーバーコート層
１０・・・プリント配線板
１１・・・切取孔
１２・・・切取部
１３・・・テストピース部1 and 2 are a partial plan view of a printed wiring board showing an embodiment of the present invention, FIG. 1 is an enlarged sectional view taken along line B-B, and FIG.
The figure and FIG. 4 are a partial plan view and a sectional view taken along the line AA in FIG. 3 of a conventional printed wiring board. 1... Insulating board 2... Circuit pattern 3
...Connection land 4.16 Solder-resist layer 5.17...Shield layer 6...Through hole 7.
18... Overcoat layer 10... Printed wiring board 11... Cutout hole 12.
...Cut-out part 13...Test piece part patent distributor Japan CMK Co., Ltd. Figure 1 2...Circuit pattern 3...Connection land 5.17...Shield layer 6...Through hole 7...・Overcoat layer 10...Printed wiring board 11...Cutout hole 12...Cutout part 13...Test piece part
Claims (2)
施す場合に、 プリント配線板内に独立したチェックランドとこれに連
通したシールド層回路を上記シールド層と同時に形成し
、プリント配線板の基板完成後にシールド層の性能を検
査することを特徴とするプリント配線板のシールド層検
査方法。(1) When applying a shield layer on the circuit pattern of a printed wiring board, an independent check land and a shield layer circuit connected to this are formed on the printed wiring board at the same time as the above shield layer, and the board of the printed wiring board is completed. A method for inspecting a shield layer of a printed wiring board, characterized in that the performance of the shield layer is subsequently inspected.
ド層を有する場合に、 プリント配線板内に独立した２個のランドと、ランド間
に形成した所定寸法のシールド層回路とを形成し、シー
ルド層検査を可能とすることを特徴とするシールド層検
査手段を有するプリント配線板。(2) When the printed wiring board has a shield layer applied on the circuit pattern, two independent lands and a shield layer circuit of a predetermined size formed between the lands are formed in the printed wiring board, and the shield layer is formed on the printed wiring board. A printed wiring board having a shield layer inspection means that enables layer inspection.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1832989A JPH02198186A (en) | 1989-01-27 | 1989-01-27 | Printed wiring board shield layer inspection method and inspection means |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1832989A JPH02198186A (en) | 1989-01-27 | 1989-01-27 | Printed wiring board shield layer inspection method and inspection means |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02198186A true JPH02198186A (en) | 1990-08-06 |
Family
ID=11968588
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1832989A Pending JPH02198186A (en) | 1989-01-27 | 1989-01-27 | Printed wiring board shield layer inspection method and inspection means |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02198186A (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05283822A (en) * | 1992-03-30 | 1993-10-29 | Toppan Printing Co Ltd | Printed circuit board equipped with electromagnetic wave shield layer |
| JP2008085051A (en) * | 2006-09-27 | 2008-04-10 | Nitto Denko Corp | Wired circuit board and its manufacturing method |
| JP2013162055A (en) * | 2012-02-08 | 2013-08-19 | Panasonic Corp | Electronic device manufacturing method and hot press device |
| JP2021186275A (en) * | 2020-05-29 | 2021-12-13 | 株式会社大一商会 | Game machine |
| JP2022074384A (en) * | 2020-11-04 | 2022-05-18 | 株式会社大一商会 | Pachinko machine |
| JP2022074382A (en) * | 2020-11-04 | 2022-05-18 | 株式会社大一商会 | Game machine |
| JP2022074383A (en) * | 2020-11-04 | 2022-05-18 | 株式会社大一商会 | Pachinko machine |
-
1989
- 1989-01-27 JP JP1832989A patent/JPH02198186A/en active Pending
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05283822A (en) * | 1992-03-30 | 1993-10-29 | Toppan Printing Co Ltd | Printed circuit board equipped with electromagnetic wave shield layer |
| JP2008085051A (en) * | 2006-09-27 | 2008-04-10 | Nitto Denko Corp | Wired circuit board and its manufacturing method |
| US8063312B2 (en) | 2006-09-27 | 2011-11-22 | Nitto Denko Corporation | Wired circuit board and producing method thereof |
| US8327535B2 (en) | 2006-09-27 | 2012-12-11 | Nitto Denko Corporation | Wired circuit board and producing method thereof |
| JP2013162055A (en) * | 2012-02-08 | 2013-08-19 | Panasonic Corp | Electronic device manufacturing method and hot press device |
| JP2021186275A (en) * | 2020-05-29 | 2021-12-13 | 株式会社大一商会 | Game machine |
| JP2022074384A (en) * | 2020-11-04 | 2022-05-18 | 株式会社大一商会 | Pachinko machine |
| JP2022074382A (en) * | 2020-11-04 | 2022-05-18 | 株式会社大一商会 | Game machine |
| JP2022074383A (en) * | 2020-11-04 | 2022-05-18 | 株式会社大一商会 | Pachinko machine |
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