JPH02195456A - Cache storage system - Google Patents

Abstract

PURPOSE:To improve a cache hit ratio by allowing effective bits stored in a cache memory to correspond to the number of data words constituting one block. CONSTITUTION:Each word constituting one block of data stored in the cache memory 70 registers an effective bit in a cache directory writing circuit 40 in each word by the action of a control circuit 90. Cache coincidence at the time of writing data in a main memory is checked by a coincidence detecting circuit 80 in each word. At the time of generating a cache miss hit, only the ineffective word in the blocks stored in the cache memory 70 is read out again from the main memory and written in the cache memory 70, a cache directory 60 is updated and required data are sent to a CPU.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a cache storage system, and particularly to a storage system including a cache memory and a cache directory.

[Conventional technology]

FIG. 2 shows a conventional example.

The conventional example shown in FIG. 2 includes a cache memory 70 that stores part of main memory data in blocks, and stores address information and validity bits of the main memory data blocks stored in the cache memory 70. A coincidence detection circuit 8 that checks whether the cache directory 60 and the main memory address match the storage address information of the cache directory 60 when writing data to the main memory.
0, and a control circuit 90 that controls writing to the cache memory 70 and cache directory 60 and reading data from the main memory.

In the cache memory 70, several bytes of data are defined as one word, several consecutive words are defined as one block, and part of main memory data and validity bits are stored in block units.

When a main memory data read command is sent from the CPU, a part of the main memory data read address is output to the cache memory 70 and the cache directory 60.

Then, the negative number output circuit 80 checks whether valid data is stored in the cache memory 70 (hit) or not (miss) in block units, and the control circuit 90
In the case of a hit, the data sold out from the cache memory 70 is sent to the CPU. In the case of a miss, the block containing the data requested by the CPU is read from the main memory, the necessary data is sent to the CPU and written to the cache memory 70, and the contents of the cache directory 60 are updated.

In the case of data writing to the main memory, the coincidence detection circuit 80 checks whether a block corresponding to the write address exists in the cache memory IJ 70 (cache coincidence check), and if it exists, the control circuit 9
0, sets the validity bit of cache directory 60 to an invalid state to invalidate this block.

[Problem that the invention sought to solve]

However, in the above conventional example, validity bits are registered in the cache directory for each block of data stored in the cache memory, so a cache match check is performed for each block, and the main memory Even if the data write is one word, if the main memory data write address exists in the cache memory, the entire block becomes invalid, which causes the inconvenience that the cache hit rate when reading main memory data decreases and the data processing speed slows down. .

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a cache storage system that improves the disadvantages of the conventional example and, in particular, improves the cache hit rate.

(Means for Solving the Problems) Therefore, in the present invention, main memory data is divided into blocks and a cache memory for storing several blocks thereof, and address information and validity bits of each main memory data block stored in the cache memory are provided. a cache directory that stores the cache directory, a match detection circuit that checks whether the main memory address matches the storage address information of the cache directory when writing main memory data, and a match detection circuit that checks whether the main memory address matches the storage address information of the cache directory when writing data to the cache memory and and a control circuit that controls data reading from the memory. A configuration is adopted in which the validity bits stored in the cache memory are made to correspond to the number of data words constituting one block. This is an attempt to achieve the above-mentioned purpose.

[For production]

By the action of the control circuit, the validity bit of each word constituting one block of data stored in the cache memory is registered in the cache directory, and the cache consistency check is performed on a word-by-word basis when main memory data is written. It will be done. Furthermore, in the event of a cache miss, only invalid words in the block stored in the cache memory are reread.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to FIG.

In the embodiment shown in FIG. 1, there is a cache memory 70 that blocks main memory data and stores several blocks thereof, and stores address information and validity bits of each main memory data block stored in the cache memory 70. A cache directory 60 , a coincidence detection circuit 80 that checks whether the main memory address and the storage address information of the cache directory 60 match when writing data to the main memory, and a match detection circuit 80 that checks whether the main memory address matches the storage address information of the cache directory 60 and the cache memory 70 and the main memory when writing data to the cache directory 60 . It has a control circuit 90 that controls data reading from the memory.

The number of validity bits of each block stored in the cache directory 60 corresponds to the number of words in one block (4 words in this embodiment) (VO~3).

Furthermore, there is a read address register 20 that sets the address (ADDC) output from the CPU, and an address (ADDC) used when other processing devices write main memory data.
a write address register 10 for setting DM);
Address selection circuit 30 that selects either read address register 20 or write address register IO
It has

Moreover, the output signal of the address selection circuit 30 and the control circuit 9
cache directory write circuit 40 that writes to the cache directory 60 with an output signal of 0;
and a cache memory write circuit 50 for writing into the cache memory 70 from the output signal of the control circuit 90 and the output signal from the main memory.

The coincidence detection circuit 80 uses the output signal of the address selection circuit 30 and the output signal of the cache directory 60 to perform a cache coincidence check when writing main memory data and a cache hit/miss check when reading main memory data.

The control circuit 90 uses the main memory data read command (CMDC) from the CPU, the main memory data write command (CMDM) from another processing device, the output signal of the address selection circuit 30, and the output signal of the coincidence detection circuit 80 to A command (CMDC') is sent to the memory and various control signals are output.

Next, the operation of this embodiment will be explained.

First, when reading main memory data from the CPU, the read address register 20 is selected by the address selection circuit 30, and the middle bit (ADM) of the read address 20 is selected.
is the cache directory 60 and cache memory 70
is output to. Upper bit of read address 20 (A
DH) is output to the -number output circuit 80, and the cache direct! It is checked whether the address information matches the address information output from J60. Furthermore, the minus number configuration circuit 80 checks whether the validity bit of the selected word is valid or not based on the lower bit (ADL) of the read address 20 output from the address selection circuit 30. As a result, the control circuit 90
In the case of a cash hit, data read from the cache memory 70 is sent to the CPU. In the case of a cache miss, only the invalid words in the block are reread from the main memory, written to the cache memory 70, the cache directory 60 is updated, and the desired data is sent to the CPU.

When writing data to the main memory from another processing device, the write address register 10 is selected by the address selection circuit 30. Then, the middle bit (ADM) of write address 10 is output to cache directory 60. Address information output from cache directory 60 and upper bits (ADH) of write address 10
is compared by the -number output circuit 80, and as a result, the control circuit 9
0, if they match, the validity bit (VO to V
3) Disable. At this time, the number of words written to the main memory from another processing device is determined by the write command (CMDM).
For example, when writing four words in succession (all words in one block), all validity bits (VO to V3) are invalidated.

〔Effect of the invention〕

As described above, according to the present invention, one of the cache memory
Because the configuration is such that a validity bit is registered in the cache directory for each word that makes up a block, it is possible to check cache consistency on a word-by-word basis when writing data to main memory, and it also prevents cache errors. When hit, only invalid words in the block stored in the cache memory can be reread. Therefore, it is possible to provide an unprecedented and excellent cache storage system in which the cache hit rate can be increased and the processing speed can be dramatically increased.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG. 2 is a block diagram showing a conventional example. 60... Cache directory, 70...
. . . Cache memory, 80 . . . -number output circuit, 90 . . . Control circuit. (Main structure Figure 2

Claims (2)

[Claims] (1) A cache memory that stores part of main memory data in blocks, a cache directory that stores address information and validity bits of main memory data blocks stored in the cache memory, and main memory data a coincidence detection circuit that checks whether a main memory address and storage address information of the cache directory match when writing; and a control circuit that controls writing to the cache memory and the cache directory or reading data from the main memory. In a cache storage system having a cache memory, a validity bit stored in the cache memory is 1.
A cache storage method characterized by being compatible with the number of data words forming a block. (2) When reading main memory data, check whether valid data exists in the cache memory word by word, and if it does not exist, read only invalid words from the main memory and read the contents of the cache memory and cache directory. The cache storage method according to claim (1), characterized in that the cache storage method updates the .