JPH02193430A - Frequency network synchronization system - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Summary] It is equipped with a first and a second terminating device connected via a data transmission path, and each of these terminating devices synchronizes the terminating device with a clock from a master station. Regarding a frequency network synchronization method that has network synchronization means to operate and is configured to perform pointer processing based on CCITY recommendations, it is possible to prevent erroneous pointer transmission or improve reliability against noise on the data transmission path. For this purpose, the transmitting end device is configured to hold the current pointer, or to notify the result of pointer processing if data changes related to pointer processing continue multiple times.

[Industrial application field]

The present invention relates to a synchronous network communication system, and particularly to a frequency network synchronization system that achieves frequency synchronization using pointers.

When constructing a digital switching network, each station is connected to each other via a digital transmission path, so a common synchronized clock is required for each station. If the synchronous clock does not operate normally, there will be a difference between the signal transmission speed and reception speed at each station, and errors will occur in the information being sent and received. Furthermore, if the transmitted bit string is connected to a time division switch in a multiplexed state as in a digital switch, the clock speed of the digital transmission path and the clock speed of the digital switch must be the same. .

Therefore, network synchronization is required to match the clock frequencies of these stations and transmission lines.

Network synchronization methods include independent synchronization methods and dependent synchronization methods. The independent synchronization method is used for international network synchronization, and a highly accurate oscillator is installed at the main station in each country, and synchronization is achieved using the clock from the independently accurate oscillator in each country. The slave synchronization method is used for domestic network synchronization, and a synchronization clock is sent from the main station to each station through a transmission path, and a network synchronization device (DC5: Digital C1ock 5) installed at each station that generates and supplies the clock is used.
The present invention particularly relates to a dependent synchronization system.

[Conventional technology]

FIG. 18 shows a configuration diagram of a synchronization network in Japan. In the figure, when slave stations Sl and 32 are configured to synchronize, the slave station S1 is connected to the subordinate station of this slave station S1. A slight deviation occurs in the frequency with that of the local slave station LS. Similarly, there is a slight difference in frequency between the slave station s2 and the local slave station LS connected below this slave station S2. Therefore,
Even if the slave stations S1, 32 are synchronized and operate with a unified clock, these slave stations S1. When data is transmitted between local slave stations LS via S2, a shift occurs in the transmitted and received data due to the frequency shift described above.

Therefore, for example, CCITT recommendations have been established in order to synchronize the data difference based on the difference in clock frequency between the slave station Sl and the local slave station LS by using a pointer indicating the start position of the data. The basics are positive staff, negative staff, new data flag, pass Al5 (^tars Indi
cation Signal). Also, CCIT
The recommendations of T include, for example, ρ for low-order groups such as the first-order group in ultra-large capacity optical transmission systems, and those for high-order groups such as the third-order group. For lower-order groups, a VT (Virtual Tributary) pointer is used as a pointer, and as described later, VTl,5,
There are VT2, VT3, and VT6. On the other hand, for higher-order groups, 5PE (Synchronous Pay
loadEnvelope) frame rate to 5TS
Adjust to O frame rate.

[Problem to be solved by the invention]

Although the CCITT Recommendations stipulate basic matters, when we specifically designed and prototyped the actual equipment, various issues that were not included in the CCITT Recommendations arose.For example, on the sending side,
The problems include that erroneous data transmission may occur, and that no measures are taken in the event that the receiving side cannot read the data due to bursts, etc.

Therefore, an object of the present invention is to solve problems that may occur when actually operating a frequency network synchronization method based on CCITT recommendations.
The goal is to solve the problem while matching it with the Y recommendation.

[Means to solve the problem]

A block diagram of the principle of the frequency synchronization method of the present invention is shown in FIG.

Network synchronization means 31 includes first and second termination devices 3.5 connected via a data transmission path 4, each of which operates in synchronization with a clock from a master station; It has 51.

The first terminal device detects the phase difference of the data from the first terminal 2 connected to the terminal device with respect to the synchronization clock, and performs pointer processing regarding at least positive stuff, negative stuff, and new data flag. It has a transmitting side network synchronization control means 32 that performs the following. The second terminal device synchronizes the received data from the first terminal device with the synchronization clock based on the pointer from the first terminal device, and the second terminal 6 connected to the second terminal device synchronizes the received data from the first terminal device with the synchronization clock. It has a receiving side network synchronization control means 53 for transmitting data to the network.

The transmitting side network synchronization control means is configured to maintain a current pointer and prevent erroneous transmission.

In addition, the transmitting side network synchronization control means may control, when data changes from the first terminal related to pointer processing continue multiple times,
The pointer processing result is configured to be notified to the second terminal device.

Furthermore, the transmitting side network synchronization control means is configured to perform the pointer holding process and the pointer notification process when the data change continues a plurality of times.

The receiving side network synchronization control means is configured to perform processing corresponding to the transmitting side synchronization control means.

More preferably, the first termination device 3 is provided with multiplexing means 33 and the second termination device 5 is provided with decoupling means 52.

(Function) First, the pointer used in the present invention will be explained in detail.The pointer is used to indicate the starting position of data within a frame to the opponent side. There are staff, negative staff, new data flag, and bus AIS.

The method of notifying the shift of the pointer and its leading position will be exemplified in the case where it is used for a higher-order group.

Figure 2 shows the configuration of a pointer. In this example, the pointer is called a payload pointer, and contains 8-bit H1 data, 8-bit H2 data,
and H3 data. The 4 bits on the MSB side of the Hl data (indicated by NNNN) are the new data flag (
NDF) and 1 that spans H1 and H2 data.
The 0 bit (10 repeats) indicates the number of bytes from H3 data to Jl, where Jl is SPH (SPH
ynchronousPayload Envelop
e) Indicates the starting position of the SPH to match the frame rate of 5TS-1, and can be freely placed within the frame of 5TS-1. It is defined as follows.

Normal case: NDF-'″01
10"When sending a new pointer value: NDF-"
1001" 10-bit pointer, as mentioned above,
This indicates the number of bytes from 3 data to Jl, and consists of an "I (increment)" bit used for positive stuffing and a "D (decrement)" bit used for negative stuffing.

Positive staff has an SPE frame rate of 5T.
This is performed when the frame rate is slower than S-1.

The transmitting side inverts 1 bit of the IO bit pointer and stores dummy data (“oooo
The pointer value is incremented by 1 from the 0th frame where "oooo") is inserted. An example will be described with reference to FIG. 3.
Figures (a) and (b) are normal cases because they are NDF-0110, and the 10-bit pointer (PNTR) -0
011010101 (binary) = 213 (decimal)
This indicates that Jl is the 213th byte from H3. Figure 3 (C) shows a case where Jl is delayed by one byte and a positive stuff occurs, and the ■ bit of the 10-bit pointer mentioned above is inverted to 1'' (as a result, the pointer = 639). A positive stuff byte (PSB) consisting of 1 byte of dummy data (all zeros) is inserted after , H3.This allows the opponent (receiving side) to be notified that positive stuffing has been performed.Figure 3 (d) is unchanged from the case of Figure 3 (C), so as a pointer at that time,
214 is set.

FIG. 4 is a diagram illustrating negative stuff. Fourth
In figure (C), as Jl advances by one byte, the D bit of the 10-bit pointer is inverted and PNTR=
384, and in Fig. 4(d), Fig. 4(a),
PNTR=214 has been changed from PNTR=213 in (b).

As described above, the receiving side can know the starting position by changing the positive stuff or negative stuff and sending the starting position (Jl) information to the receiving side.

On the other hand, since a change in the position of Jl means a change in the actual number of data accommodated between H3 and Jl, that is, a change in the data rate, it also indicates a change in the clock frequency. ing. That is, in the case of a positive stuff, the clock is slow (and in the case of a negative stuff), the clock is fast.

FIG. 5 shows NDF processing. NDF indicates a difference of 2 or more bytes, whereas positive stuff and negative stuff have a difference of 1 byte. In the example of FIG. 5, in FIG. 5(b), PNTR-
213 was PNTR-4 in Figure 5 (C).
35, and in FIG. 5(d), ND
F=0110, indicating that a significant byte shift has occurred.

Pass Al5 (^farm Indication Si
gnal) is Hl.

Insert all "1" into H2 and H3.

The operation of the transmitting side network synchronization control means 32 will be described below with reference to FIG.

(a) Initial Settings It is reset at power-on (S001), and the next initial value is set (3002).

lO bit pointer (PNTR) =00000011
10 (141°) NDF=0110 (normal) (b) Hold the pointer for multiple frames, for example, 3 frames (S003), this pointer holding is performed after positive stuff, negative stuff, and NDF operations.
This is to prevent increment or decrement processing within one frame.

(C) Compare the phase of data from terminal 2 with the synchronous clock, check for byte changes (retention), positive stuff processing, negative stuff processing, NDF processing, path AI
It is determined whether S processing is necessary (S004).

(d) When holding, hold the pointer for one frame (S005),
The process returns to step 004 (S004). By holding this pointer, the transmitting side can know the transmission status, thereby preventing erroneous sending of the pointer.

(e) For positive staff (S 011~5O1
3) Incrementing the pointer! Bit inversion processing is performed (S011). Next, the pointer is held for one frame (S012).

This pointer holding is similar to the pointer holding in step 005 (S005). Furthermore, the pointer (PNTR
) is added by one, a positive stuff byte is added after H3, and Jl is shifted by one (S013). Through this process, the data becomes the state shown in FIG. 3(C).

After the above processing, the process returns to step 003 (S 003), and no increment or decrement processing is performed for three frames. In other words, once a positive stuff occurs, the receiving side is synchronized in that state. Furthermore, if the receiving side continuously receives pointer changes such as positive stuff, negative stuff, and NDF, it can be determined that these are caused by burst noise on the transmission path. .

(f) In the case of negative stuff (S 021-302
3) Perform pointer D bit inversion processing (S 021)
, hold the pointer for one frame (S 022), and perform the decrement process shown in FIG. 4(g) (S 023).
).

Thereafter, the process returns to step 003 (S003).

The meaning of pointer retention (SO22, 5003) is the same as in the case of positive stuff described above.

(h) In the case of NDF (SO31 to S033) Figure 5 (
As shown in C), invert the NDF and get NDF = 1
001 and set the pointer (PNTR) to a new pointer value from H3 to Jl (SO31).

Hold the inter-frame pointer (S032), fifth
As shown in Figure (d), return NDF to 0110 (S
033), return to step 003.

(i) In the case of bus AIS (3041 to S042), all "1" bits of Hl, H2, and H3 of the pointer are set (SO41), and the pointer is held for one frame (
S 042).

Thereafter, the process returns to step 004 (S004). In other words, as in positive staff processing, step 0
03 (S 003) (Similar to the case of "hold", the process returns to step 004. This is because there is no need to hold the pointer related to the path AIS for three frames.

The processing operation of the receiving side network synchronization control means 53 will be described with reference to the flowchart of FIG.

(aa) Initial settings Reset at power-on (S 101) and set the receiving side pointer (PNTR) to all zeros (S 102)
).

(bb) Path AIS processing (S103, 5151) If H1 and H2 of the received pointer are all "1" for three consecutive frames, it is determined that it is path AIS (S103)
.

Bus AIS is canceled when NDF=0110 and valid reception pointers are received for three consecutive frames (
S 151).

(cc) New pointer processing (3104, 5141) As shown in Figure 8 (b) to (d), when the same pointer (PNTR=214) is received for three consecutive frames (
S104), the reception pointer is updated as a new pointer (3141).

(dd) Positive stuff processing (Sill, 3
112) When the reception pointer indicates a positive stuff, increment the receiving side pointer by 1 (3.111). Note that it is determined that the positive stuff is valid by 5.
This is a case where three or more of the ■ bits are inverted.

The receiving side pointer is held for three frames (S112
). This pointer holding corresponds to the pointer holding (S003) shown in FIG.

(ee) Negative stuff processing (S121, 51
12) Decrement the receiving side pointer by 1 (S121). In this case as well, only when 3 or more of the 5 D bits are inverted, the above pointer processing is performed as a valid negative stuff.

Then, hold the receiving side pointer for 3 frames (
S 112).

(ff) NDF processing (S131, 3112) If the received pointer is NDF = 1001, the received l
Set the value of the O bit pointer to the receiving side pointer (
S 131).

Next, the updated receiving side pointer is held for three frames (S112).

Above, with reference to FIGS. 2 to 8, we have described the operation of the frequency network synchronization method using a payload pointer in a high-order group, for example, a 3-order group. This section describes the effects of the frequency network synchronization method.

9(a) to (d) show VT (Virtu)
alTributary) 1.5, VT2,
Figure 10 shows the data structure diagram of VT3 and VT6 (
a) - Configuration diagram of VT pointer for boat fishing, Figure 10(b)
~(e) are VT6, VT3, VT2, and V, respectively.
The configuration diagram of the VT pointer of Tl,5 is shown. Figure 10 (a
), Vl and v2 are respectively the above-mentioned H
l, ) (corresponds to 2. 4 bits N from the MSB of Vl
NNN indicates NDF. The next 2 bits SS indicate the VTO size.

This VT size is VT6, VT3, VT2,
VTl, 5 corresponding to 00, 01, 10
, 11, followed by ■ (increment) bits and D (decrement) bits arranged alternately.
A 0 bit pointer is provided. Figure 9(a)-(
In d), ■3 indicates an action or a pointer, and VT4 indicates VT retention.

The positive stuff, negative stuff, and NDF processing are the same as those described above.

〔Example〕

A frequency network synchronization method using pointers in the case of VTl, 5, which is used for the primary group (clock frequency 1, 544 MHz), will be described.

FIG. 11 shows a stuff detection circuit provided in the transmitting side network synchronization means 32 of FIG. 1, and FIGS. 12(a) to 12(d)
shows the operation timing of the stuff detection circuit in FIG. 11. Data SIN is input from the terminal 2 in FIG.
Can be written to EM. Writing to this memory is controlled by the clock CLKs+N from terminal 2 - circuit - TC.
It is input to LK and is performed using the clock from this write clock control circuit. The data from the terminal 2 once written to the memory MEM is read out in order to be transmitted to the receiving side. Data reading from this memory is performed by the read clock control circuit RDC based on the clock CLKspyt on the SPE side.
This is done via LK.

3□ on the SPE side clock CL is DCS 31 in Figure 1.
The network synchronization is done via , exactly 1.544M
This is the frequency of H2. The clock CLKs+s of terminal 2 should also be 1.544 MHz, but since network synchronization is not achieved, it may be slightly deviated from 1.544 MHz. In order to absorb this deviation, the memory MEM
Using CLKs*s, data from terminal 2 is written using CLKs*s, and the written data is ct and Ks. This is happening one after another. Furthermore, in the phase comparison circuit PC of FIG.
CLKsp for a window based on IN on CL
Detect the phase difference of t, detect whether there is a 1-byte data advance (positive stuff) or a 1-byte data delay (negative stuff), and if a positive stuff occurs, a positive stuff signal is generated. ten seconds
'rupp, if negative stuff occurs, outputs a negative stuff signal -5TUFF.

FIG. 13 shows a transmitting side pointer control circuit that constitutes the transmitting side network synchronization control means 32 of FIG. 1.

In the figure, reference numeral 321 includes an increment circuit 1NC1 that outputs a positive stuff request signal REG based on the +5TOFF signal from FIG. 11, and a decrement circuit DEC that outputs a negative stuff request signal REQ based on the -5TUFF signal. The above request signal indicating the signal generation circuit is a pointer operation (action)
is generated in response to ■3. 322 indicates a 2-bit delay type flip-flop (DFF);
■ Using 1 as a clock, the above request signal REQP or RE
QD is held and an increment inversion signal T or a decrement inversion signal ■ is output. These inversion signals T or ■ are applied to the VT pointer processing circuit 327, and in the case of positive stuff, the I bit of the 10-bit pointer in FIG. 10(a) is inverted, and in the case of negative stuff,
Used to invert the D bit. Reference numeral 323 indicates an OR gate, which outputs the cause signal of the new data flag to the NDF processing circuit 324. 325 is a VT size setting device, and since the 2-bit VT size shown in FIGS. 10(b) to 10(e) is VTl, 5 in this example, a code Y=11 indicating the VT size is set. be done. 326 is a VT size processing circuit, which sets the set VT size code Y to a predetermined position of the pointer (see FIG. 10(a)); 328 is a VT overhead byte multiplexing circuit, which processes the pointer, etc. multiplex the data.

330 is an initialization/update control circuit, 331 is an initialization/update circuit, and 333 is a circuit for setting mode X.

-T--)'X is VT 1.5 (7) if 25, V
It is 52 for T3(7) and 106 for VT6. Mode settings will be described later. Initialization/update control circuit 33
0 and the initialization/update circuit 331 set the initial value of the pointer.

Further, the initialization/update control circuit 330 and the initialization/update circuit 331 add 1 to the pointer value based on the inverted increment signal T from the DFF 322, and add 1 to the pointer value based on the inverted decrement signal -D-. Subtract.

329 is a three-time holding control circuit, 333 is a pointer storage circuit, and the pointer storage circuit 333 is the initialization/update circuit 3.
Holds a pointer from 31. 3 times holding control circuit 32
9 controls the pointer in the pointer storage circuit 333 to be held for three frames when a positive stuff occurs.

334 is a v5 counter, 335 is a pulse generation circuit, and the V5 counter 334 is a VT byte clock CKV□
is input as a clock, 2 is counted, and the pulse generation circuit 335 is driven by the count signal CO.

FIG. 14 shows an operation timing diagram of the pointer control circuit of FIG. 13. FIG. 14 is a diagram that can be applied to both positive stuff and negative stuff.

Let me explain using positive staff as an example. When a positive stuff is detected by the circuit shown in FIG. 11 at time t1, a positive stuff request signal REQ is output from the request signal generating circuit 321.

At time t2, the inverted increment signal T is output from the DFP 322, and at time t3, the I bit is inverted in the VT pointer circuit 327. Time t
With the arrival of (3) at 4, the DFP 322 is reset, and at time t5, the inverted increment signal T is reset. As a result, at time t6, 1 is added to the pointer via the initialization/update port 1II331. This updated pointer is stored in the pointer holding circuit 33.
3, and is held for three frames thereafter.

Similar processing is performed for negative staff.

For VT 1.5, if the pointer is 25 or less and 26
There may be more than one case. This is shown in FIGS. 15 and 16.

In FIG. 15, when the pointer is 25 or less, V5 is between v2 and ■3. Perform an operation (action) in V3, that is, perform positive stuff or negative stuff to adjust the frequency. Because the action is performed at the position of V3, the byte position of v5 does not change in the current frame, and the byte position of v5 does not change in the next 500 μs. vl from the superframe of.

(2) The value of the pointer indicated by 2 matches the byte position of v5. In FIG. 16, when the pointer is 26 or more, ■5 exists between ■3 and v4. The action is taken at the position of V3, but the byte position of ■5 changes immediately within the current frame, and the pointer values indicated by Vl and V2 and v
The byte position of 5 matches. In this way, two types of processing are required, and in order to identify them, the mode setting circuit 3
If the mode X is VT 1.5, X=25 is set.

FIG. 17 shows a receiving side pointer control circuit diagram constituting the receiving side network synchronization control means 53 of FIG. 1.

The receiving pointer control circuit performs processing corresponding to the transmitting pointer control circuit, as shown in FIG.

In the same figure, 531 is a VT overhead demultiplexing circuit that receives and separates the multiplexed transmission data from the terminal device 3 in FIG. 533 is a circuit that holds the previous pointer, 534 compares the ■ bit and D bit of the previous pointer and the current pointer, and detects positive stuff or negative stuff if there is an inversion. stuff detection circuit, 535 is a 2-bit DFF, 536 is an initialization/update control circuit, 537 is a mode setting circuit, 538 is an initialization/update circuit, 539 is a comparison circuit, 540 is a v5 counter, 541 is a pulse generation circuit, 542 543 is an OR gate, 544 is a VT size holding circuit, and 551 to 553 are an NDF error output circuit, a VT size error output circuit, and a pointer error output circuit, respectively.

Taking the case of a positive stuff as an example, the pointer of the previous pointer holding circuit 533 and the current pointer are compared in the stuff detection circuit 534, a positive stuff is detected, and the DFF 535 is set. DFF
An inverted increment signal T from 535 is applied to initialization/update circuit 538 via initialization/update control circuit 536 to advance the pointer by one.

The three-time hold control circuit 542 holds the updated pointer for three frames. (2) The 5 counter 540 counts so that the position of v5 is determined based on the updated pointer.

The above discussion focused on positive staff and negative staff, but the same applies to NDF.

Furthermore, the same process can be performed for higher-order groups as well.

〔Effect of the invention〕

As described above, according to the present invention, when realizing frequency network synchronization using pointers, it is possible to prevent erroneous transmission of pointers, and furthermore, it is possible to perform network synchronization that does not malfunction even due to noise on a transmission path.

[Brief explanation of the drawing]

FIG. 1 is a principle block diagram of the frequency network synchronization method of the present invention, FIG. 2 is a configuration diagram of a pointer of the present invention, and FIGS. 3 to 5 are diagrams explaining positive stuff, negative stuff, and NDF, respectively. 6 and 7 are processing flowcharts of the transmitting side and receiving side network control means of the present invention, respectively, FIG. 8 is a diagram showing the new pointer processing of the present invention, and FIGS. 9(a) to (d) are VT configuration diagrams of the present invention, FIGS. 10(a) to (e) are similar to FIGS. 9(a) to (
d) Pointer configuration diagram, Figure 11 is a stuff detection circuit diagram of an embodiment of the present invention, Figure 12 is an operation timing diagram of the circuit in Figure 11, and Figure 13 is a transmission side pointer control of an embodiment of the present invention. Circuit diagram; Figures 14(a) to (e) are operation timing diagrams of the circuit in Figure 13; Figures 15 and 16 are timing diagrams of two modes; Figure 17 is the receiving side of the embodiment of the present invention. FIG. 18 is a pointer control circuit diagram and a synchronous network configuration diagram. (Explanation of symbols) 3.5... Terminal device, 2, 6... Terminal, 32
. . . Transmitting side network synchronization control means; 53 . . . Receiving side network synchronization control means. (b)'H1, H goo 70+ 100000. no+o
+o+” PNTR-213 PNTR-435 PNTR-435 Diagram explaining NDF Figure 5 (a) VTl, 5 (b) T2 (c) T3 (d) T6 VT configuration diagram Figure 9 Synchronous network configuration diagram Figure 18 6゜Object of amendment 7゜Contents of amendment in "Brief explanation of drawings" column of specification Correct to. Procedural amendment (method) % formula % Display of the case 1999 Patent Application No. 11902 Name of the invention Frequency network synchronization method Person making the amendment Relationship to the case Patent applicant name (522) Fujitsu Limited 46 agent

Claims (1)

[Claims] 1. A first and a second terminal device (3, 5) connected via a data transmission path (4), each of which is synchronized with a clock from a master station. The first terminal device has network synchronization means (31, 51) for operating the terminal device by synchronizing the synchronization clock, and the first terminal device is configured to synchronize the data from the first terminal (2) connected to the terminal device with respect to the synchronization clock. The second terminal device has a transmitting side network synchronization control means (32) that detects the phase difference and performs pointer processing regarding at least positive stuff, negative stuff, and new data flags, and the second terminal device The receiving side network synchronization control means (53) synchronizes the received data from the first terminal device with the synchronization clock based on the pointer and sends it to the second terminal (6) connected to the second terminal device. ), wherein the transmission side network synchronization control means maintains a current pointer to prevent erroneous transmission. 2. Equipped with first and second terminal devices (3, 5) connected via a data transmission path (4), each of which operates in synchronization with the clock from the master station. The first terminal device has network synchronization means (31, 51) that detects the phase difference of data from the first terminal (2) connected to the terminal device with respect to the synchronization clock, and At least, the second terminal device has a transmission side network synchronization control means (32) that performs pointer processing regarding positive stuff, negative stuff, and new data flags, and the second terminal device performs pointer processing on the first terminal device based on the pointer from the first terminal device. a receiving side network synchronization control means (53) for synchronizing the received data from the terminal device with the synchronization clock and transmitting it to the second terminal (6) connected to the second terminal device; The transmitting side network synchronization control means is configured to perform a first
A frequency network synchronization method, characterized in that when data changes from a terminal continue multiple times, the result of the pointer processing is notified to a second terminal device. 3. The transmitting side network synchronization control means is configured to notify the receiving side of the result of the pointer processing when a change in data from the first terminal related to pointer processing continues multiple times. Frequency network synchronization method described in Section 1.