JPH02192096A - Selective refresh control device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] [Industrial application field] The present invention provides a device comprising a dynamic RAM element. The present invention relates to a refresh control device for.

[Conventional technology]

As is well known, dynamic RAM typically requires a refresh operation to prevent data stored in the form of charges from being lost. A refresh operation is achieved by accessing all memory cells once within a predetermined time. Therefore, there is no need for a refresh operation where the storage device is used so that all addresses are accessed at least once within said predetermined time. One example is an image memory for a display device where screen refresh is repeated at sufficiently short intervals.

On the other hand, the capacity of dynamic RAM elements (packages) continues to increase, and recently 1 Mbit packages have become available, and the practical use of 4 Mbit packages is expected in the near future. In many cases, only a portion of the capacity of a storage device configured with such a large-capacity package is used for display image data. Where such a storage device is used as a display image memory without a refresh mechanism, the surplus storage area cannot be used for other purposes.

According to the prior art, in order to use this surplus area for data other than display image data, it is necessary to refresh the entire storage area including the area for image data.

[Problem to be solved by the invention]

It is uneconomical to leave excess storage space unused.
Needless to say. Furthermore, refreshing the entire storage area is also uneconomical in another sense.

In other words, an unnecessary refresh is performed on the image memory area, and normal access operations are prohibited during that time, resulting in a decrease in the usable time of the storage device, or in other words, an increase in the average access time. . In particular, in small portable computers, the area of the display screen is small, so the area occupied by image data is small, and in order to save on devices, excess storage space can be used as main memory and various buffers. desired. In this case, performing an unnecessary refresh is further disadvantageous in that it wastes the power battery.

An object of the present invention is to localize the execution of a refresh operation to an area where it is really needed, and thereby to use different areas of a single dynamic RAM array for applications that do not require a refresh operation and those that do require it. In doing so, the aim is to reduce access speed and reduce power consumption to the minimum necessary.

[Means to solve the problem]

The refresh control device of the present invention includes, in addition to a circuit that generates a series of refresh addresses at predetermined time intervals, a circuit that stores information indicating a certain address range, and a circuit that stores information indicating whether each refresh address is within the address range. and a circuit for determining whether or not to perform a refresh operation at the refresh address based on the result.

[Effect]

The storage circuit receives from the outside (eg, a CPU) information (eg, a boundary address) indicating an address range corresponding to a storage area that requires refreshing (or a storage area that does not require refreshing), and stores the information. Each successively generated refresh address is checked to see if it is within the said address range, and only if it is within the said address range (or outside the range) is a refresh operation performed on that address. is executed. In this way, the execution of the refresh operation can be limited to only those parts where it is needed.

〔Example〕

FIG. 1 shows an embodiment of a refresh control device according to the present invention, and FIG. 2 shows an entire storage device including the refresh control device of FIG.

The storage device shown in FIG. 2 includes a refresh control circuit 1
01, access control circuit 102, and memory array 10
Consists of 3. The refresh control circuit 101 later
As will be described in detail with reference to the figure, the refresh address 106 and refresh request signal 1 for a specified storage area are connected to the address bus 108 and the data bus 109.
05 is generated. The access control circuit 102 may be a conventional type, and is connected to an address bus 108 and receives a refresh address 104 and a refresh request signal 105.
In response, the memory address 106 and memory control signal (R
AS, CAS, WE, etc.) 107 are supplied to the memory array 103. The memory array 103 is connected to a data bus 109 and receives memory addresses 106 and memory control signals 10.
7, stores the data on the data bus 109;
Output data there or perform a refresh operation.

Memory array 103 consists of 32 IMXI P1 to Dynamic RAM packages, which are grouped into four groups of eight packages each to provide 4 Mbytes of memory space. The address space is from '0Oo000' to 13FFF in hexadecimal notation.
There are two ranges for FF'. The area from 'o o o o o o' to 'IFFFFF' is allocated to the image memory for display, and this part does not require refreshing, and the remaining area, i.e. from '200000' to '3FFFFF'
' is used as main memory and various data buffers, and this part requires refreshing.

As shown at the top of FIG. 3, address data for read/write operations transferred on address bus 108 consists of 22 bits 1 to 1 (bits O-21). The lowest two bits (bits 0, 1) are bytes (package group)
is specified, and within the access control circuit 102, C
The AS signal is used to select the package group to be supplied. Note that the RAS signal is supplied to all packages. Next 10 bits of address data (bit 2
~11) are supplied to the memory array 103 as a column address in synchronization with the CAS signal, and the most significant 10 bits (bits 12 to 21) are supplied as a row address to the RA
It is supplied to the memory array 103 in synchronization with the S signal. The least significant bit (bit 12) of the row address is used together with the column address to select bits within the memory array 103, and the remaining row address bits (bits 13 to 21) are used to selectively activate word lines. It will be done.

Therefore, the refresh address is represented by 9 bits corresponding to bits 13 to 21 of the address data, as shown in the middle part of FIG.

During a normal read/write operation, access control circuit 102 receives address data on address bus 108 and provides RAS signals to all packages.
In synchronization with this, the row address is sent out as the memory address 106, and then the CAS signal is supplied to the package group specified by the byte designation section, and in synchronization therewith, the column address is sent out as the memory address 106. In the case of a write operation, a WE signal is further supplied.

Upon receiving the refresh request signal 105, the access control circuit 102 stops accepting access requests for normal reading/writing, and updates the refresh address 104.
is supplied to the memory array 103 as a memory address 106 in synchronization with the RAS signal. As a result, so-called RAS-only refresh is performed on all addresses having this refresh address in the most significant part.

FIG. 1 shows one embodiment of a refresh control circuit 101 according to the present invention. Refresh cycle generation circuit 110
generates a refresh cycle clock 114 at fixed time intervals determined from the specifications of the memory array 103.

The refresh address generation circuit 111 is a 9-bit (data length of the refresh address) binary counter, counts the refresh cycle clock 114, and outputs the counted value as the refresh address 104.

The refresh range designation circuit 11.2 is a 9-bit register. A CPU, not shown, can write a desired value to this register via address bus 108 and data bus 109, and this value is used as refresh range address 115. The comparator 113 is
Each time the refresh cycle clock 114 is supplied, the refresh address 104 and the refresh range address 115 are compared, and if the former is greater than the latter, then
A refresh request signal 105 is generated.

When each area of the memory array 103 is allocated as shown in FIG.
2, 'OFF' as shown at the bottom of Figure 3.
is set. As a result, refresh request signal 1
05 is when the refresh address 104 is equal to or greater than '100', i.e. '100'
This occurs only when the range is within the range from 'IFF' to 'IFF'. Therefore, the area from '200000' to '3FFFFF' in the address space of the memory array 103 is refreshed, and the remaining area from 'ooooooo' to 'IFFFFFF' is refreshed. In other words, when viewed on the time axis, as shown in Figure 4,
Refresh operations are inhibited until the refresh address reaches 'IFF', thus all of the time that would have been spent on refresh operations during this period is used for normal read or write operations. Can be done. In this example, the time spent on the refresh operation is half that of refreshing all addresses.

As a modification, only the front part of the address space of memory array 103 can be refreshed by changing the function of comparator 113 so that it generates refresh request signal 105 when refresh address 104 is smaller than refresh range address 115. can. Alternatively, a register for an upper limit address and a register for a lower limit address are provided in the refresh range specifying circuit 112, and the refresh request signal 105 is generated (or not) when the refresh address is between the upper limit address and the lower limit address. The comparator 113 may be changed as shown in FIG. Yet another variation is that instead of a two-limited address register,
Data indicating the area width is set as an initial value, a counter is provided to count down the refresh cycle clock, and after the refresh address reaches the lower limit address, the counter operates until the count value reaches '○''. The refresh request signal 105 may be generated (or not generated) for only a period of time.If a plurality of refresh range designation circuits 112 are provided, a plurality of areas arranged at intervals can be designated as (or not) that require refresh. (or unnecessary) area.

[Effects of the Invention] According to the present invention, refresh operations are performed only in areas that really require them, and therefore different areas of a single dynamic RAM array can be used for applications where refresh is not required, such as display image memory. It can be used for applications that require refreshing, such as main memory or data memory, and furthermore, the reduction in access speed and power consumption due to refreshing can be kept to the necessary minimum.

The time required for one read, write or refresh operation is t, the time interval between refresh operations is T,
When the total number of refresh addresses is R and the number of refresh addresses where refresh operations are performed is r,
Compared to refreshing the entire area, the present invention increases the time available for reading/writing by the time (R-r)·t in the time T·R.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a refresh control circuit as an embodiment of the present invention, FIG. 2 is a block diagram of a storage device equipped with the refresh control circuit of FIG. 1, and FIG. 3 is a block diagram of a storage device equipped with the refresh control circuit of FIG. FIG. 4 is a diagram showing the relationship between address data, refresh address data, and refresh range addresses for , and FIG. 4 is a time chart of an example of a refresh sequence according to the present invention. 110...Circuit that generates a refresh cycle clock, 111...Refresh address generation circuit, 1
12... A circuit that stores refresh address range specification information, 113... A comparator that checks whether the refresh address is within the specified range.

Claims (1)

[Claims] 1. A circuit for generating at predetermined time intervals successive refresh addresses each indicating a location of the memory device to be refreshed for controlling a refresh operation of a memory device including at least one dynamic RAM element; A circuit for storing information indicating a certain address range of a storage device, and a circuit connected to the generation circuit and the storage circuit to check whether each refresh address is within the address range, and to determine whether or not each refresh address is within the address range based on the result. A refresh control device comprising: a circuit for determining whether or not to perform a refresh operation.