JPH0218952A - Resin sealed semiconductor device - Google Patents
Resin sealed semiconductor deviceInfo
- Publication number
- JPH0218952A JPH0218952A JP63169723A JP16972388A JPH0218952A JP H0218952 A JPH0218952 A JP H0218952A JP 63169723 A JP63169723 A JP 63169723A JP 16972388 A JP16972388 A JP 16972388A JP H0218952 A JPH0218952 A JP H0218952A
- Authority
- JP
- Japan
- Prior art keywords
- lead frame
- tab
- resin
- semiconductor device
- electric discharge
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/83385—Shape, e.g. interlocking features
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、表面実装用樹脂封止半導体装置に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a resin-sealed semiconductor device for surface mounting.
トランスファ成形法により樹脂封止された半導体止して
、ビン挿入型のＤＩＰ、ＺＩＰや表面実装型のＱＦＰ、
ＳＯＰ、ＳＯＪ等が一般的に用いられている。Semiconductors sealed with resin using the transfer molding method are used for bottle insertion type DIP, ZIP, surface mount type QFP,
SOP, SOJ, etc. are commonly used.
最近、表面実装型の半導体装置が増加する傾向にあり、
表面実装型の半導体装置では、樹脂パッケージ部全体が
２１０℃〜２６０″Ｃのはんだ温度にさらされるため、
特に吸湿したパッケージを用いた場合、内部水分が急激
に気化膨張し、パッケージの裏側（リードのタブ位置）
にクラックが入ったり、リードや素子と樹脂の間が剥離
し、耐湿性が低下する問題などが発生し、大きな問題と
なっている。Recently, the number of surface-mounted semiconductor devices has been increasing.
In surface-mounted semiconductor devices, the entire resin package is exposed to a soldering temperature of 210°C to 260″C.
Particularly when using a package that absorbs moisture, the internal moisture rapidly evaporates and expands, causing the back side of the package (the lead tab position)
This has caused serious problems such as cracks appearing in the lead, peeling between the lead or element and the resin, and a decrease in moisture resistance.
この問題の原因は、リードフレームのタブ裏側の一部が
封止樹脂と剥離し、そこにたまった水が気化膨張するこ
とにあると考えられ、各種の対策がとられてきた。第１
図及び第２図は、従来方式のリードフレームの平面図で
、従来、第１図に示されるようなデインプル加工、ある
いは第２図で示されるようなスリット加工等の剥離防止
の工夫がなされていたが、その効果は充分ではなかった
。The cause of this problem is believed to be that a portion of the back side of the tab of the lead frame separates from the sealing resin, and the water that accumulates there evaporates and expands, and various countermeasures have been taken. 1st
Figures 1 and 2 are plan views of conventional lead frames, which have conventionally been devised to prevent peeling, such as dimple processing as shown in Fig. 1 or slit processing as shown in Fig. 2. However, the effect was not sufficient.
（発明が解決しようとする課題〕
本発明は吸湿した場合にも耐はんだ性において優れてお
り、耐湿性が低下することがない樹脂封止半導体装置を
提供するものである。(Problems to be Solved by the Invention) The present invention provides a resin-sealed semiconductor device that has excellent solder resistance even when moisture is absorbed, and the moisture resistance does not deteriorate.
本発明者は、上記問題に関し鋭意検討した結果、リード
フレームとしてタブ裏側を放電加工法にて凹凸加工を施
したものを使用することが有効であることを見出し本発
明を完成するに至った。As a result of intensive studies regarding the above-mentioned problem, the inventors of the present invention have found that it is effective to use a lead frame whose back side of the tab is textured by electrical discharge machining, and has completed the present invention.
すなわち、本発明はリードフレーム上にシリコン素子を
ダイボンディングし、さらに金線でワイヤボンドした後
、トランスファ成形法で樹脂封止してなる半導体装置に
おいて、リードフレームとしてタブ裏側が放電加工法に
て凹凸加工が施されたリードフレームを用いることを特
徴とする樹脂封止半導体装置を提供するものである。That is, the present invention provides a semiconductor device in which a silicon element is die-bonded onto a lead frame, further wire-bonded with gold wire, and then sealed with resin using a transfer molding method. The present invention provides a resin-sealed semiconductor device characterized by using a lead frame which has been subjected to an uneven process.
放電加工法による凹凸加工は、従来のデインプルや溝と
比較して微細な加工が可能であり、これが、タブ裏側で
の樹脂の剥離に有効なものと考えられる。The uneven machining by electric discharge machining allows finer machining than conventional dimples and grooves, and this is considered to be effective in peeling off the resin on the back side of the tab.
放電加工による穴の深さは１０〜５０μｍが好ましく、
これより浅いと剥離防止効果が小さく、また５０μｍ以
上の加工はコストと技術面から採用することが難しい。The depth of the hole formed by electrical discharge machining is preferably 10 to 50 μm,
If it is shallower than this, the effect of preventing peeling will be small, and processing of 50 μm or more is difficult to adopt from a cost and technical standpoint.
穴径について深さと同等以下にする方が好ましく、径が
大きいと効果は小さくなる。また、大間のピッチはせま
い程良いが、加工コストを下げるために、５００μｍま
で広げることができる。It is preferable to make the hole diameter equal to or smaller than the depth, and the larger the diameter, the smaller the effect. Also, although the pitch between Ohma is relatively small, it can be widened to 500 μm in order to reduce processing costs.
また、放電加工は必ずしもリードフレームのタブ裏全体
に施す必要はなく、コスト面から、例えばタブ裏の周辺
部だけに放電加工を施すなど、必要最小限に施すことに
よっても効果がある。Furthermore, it is not necessarily necessary to perform electric discharge machining on the entire back of the tab of the lead frame, but from a cost perspective, it is also effective to perform electric discharge machining to the minimum necessary extent, for example, by performing electric discharge machining only on the peripheral portion of the back of the tab.
さらに、上記半導体装置において、タブ吊りリードが離
型処理されているリードフレームを用いるとさらに樹脂
の剥離防止に効果がある。これはタブ吊りリードがパッ
ケージの外へ貫通していることから、蒸気を外に逃がす
ことができ、内圧の上昇を防ぐ効果があるものと思われ
る。Further, in the above semiconductor device, if a lead frame in which the tab suspension lead is subjected to mold release treatment is used, it is more effective in preventing peeling of the resin. This is thought to be because the tab suspension lead penetrates to the outside of the package, allowing steam to escape to the outside and preventing a rise in internal pressure.
離型処理はタブ吊りリードに例えばシリコーンコーティ
ング剤を塗布し乾燥、硬化させることにより行われる。The mold release treatment is performed by applying, for example, a silicone coating agent to the tab suspension lead and drying and curing it.
以下実施例をもって効果を説明する。 The effects will be explained below using examples.
第１図〜第４図はリードフレームの平面図で、ｌはタブ
、２はリードピン、３はタブ吊りピンである。1 to 4 are plan views of the lead frame, where l is a tab, 2 is a lead pin, and 3 is a tab hanging pin.
（実施例１）
第３図に示すようにリードフレームのタブ裏全面に、深
さ３０μｍ、径２０μｍ、ピンチ５０μｍの放電加工を
施した。(Example 1) As shown in FIG. 3, the entire back surface of the tab of the lead frame was subjected to electric discharge machining with a depth of 30 μm, a diameter of 20 μm, and a pinch of 50 μm.
（実施例２）
第３図と同様にリードフレームのタブ裏全面に深さ２５
ａｍ、径２０ａｍ、ピッチ３００ ｐｍの放電加工を施
した。(Example 2) As in Fig. 3, a depth of 25 mm was applied to the entire back surface of the tab of the lead frame.
electric discharge machining with a diameter of 20 am and a pitch of 300 pm.
（実施例３）
第４図に示すようにリードフレームのタブ裏周辺部に深
さ３０μｍ、径２０ｐｍ、ピッチ５０μｍの放電加工を
施した。(Example 3) As shown in FIG. 4, the periphery of the back of the tab of the lead frame was subjected to electric discharge machining with a depth of 30 μm, a diameter of 20 pm, and a pitch of 50 μm.
（比較例１） リードフレームのタブ裏に放電加工を行わなかった。(Comparative example 1) Electric discharge machining was not performed on the back of the tab of the lead frame.
（比較例２）
第１図に示すように、リードフレームのタブ塩に径３０
０μｍ、深さ１００μｍのピッチｌ ｍｍのデインプル
加工を行った。(Comparative Example 2) As shown in Figure 1, the tab salt of the lead frame has a diameter of 30 mm.
Dimple processing was performed with a pitch of 1 mm and a depth of 100 μm.
（比較例３）
第２図に示すように、リードフレームのタブ塩に巾５０
０μｍ、深さ１００μｍの溝加工を行った。(Comparative Example 3) As shown in Figure 2, the tab salt of the lead frame has a width of 50 mm.
A groove of 0 μm and a depth of 100 μm was formed.
以上のリードフレームを用い、ダミー素子を搭載し、テ
スト用ＳＯＪパッケージを成形した。封止材には、ＣＥ
Ｌ−Ｆ−７５７（日立化成工業型、エポキシ樹脂封止材
）を用い、常法に従い１８０“Ｃで９０秒成形を行い、
さらに１８０ ”Ｃで４時間の後硬化を行った。Using the above lead frame, a dummy element was mounted and a test SOJ package was molded. The sealing material is CE
Using L-F-757 (Hitachi Chemical type, epoxy resin sealant), molding was performed at 180"C for 90 seconds according to the usual method,
Further post-curing was performed at 180"C for 4 hours.
耐はんだテストは、パッケージを８５’Ｃ／８５％ＲＨ
Ｍの条件で、７２時間〜１２０時間吸湿させ、２１５°
Ｃのベーパリフローを９０秒かけた後、パッケージ裏側
のクランク発生数を評価した。結果を表１に示す。Solder resistance test was performed on the package at 85'C/85%RH.
Absorb moisture for 72 hours to 120 hours under the conditions of 215°
After vapor reflow of C for 90 seconds, the number of crank occurrences on the back side of the package was evaluated. The results are shown in Table 1.
（実施例４）
第３図に示すようにリードフレームのタブ裏全面に、深
さ３０μｍ、径２０μｍ、ピッチ５０μｍの放電加工を
施し、さらにタブ吊りリードにシリコーンコーティング
剤 ５Ｒ２４１０（トーレシリコーン株式会社製）を塗
り３０°Ｃで２４時間乾燥、硬化させた。(Example 4) As shown in Fig. 3, the entire back surface of the tab of the lead frame was subjected to electrical discharge machining with a depth of 30 μm, a diameter of 20 μm, and a pitch of 50 μm, and the tab suspension lead was coated with silicone coating agent 5R2410 (manufactured by Toray Silicone Co., Ltd.). ) was applied and dried and cured at 30°C for 24 hours.
に径３００μｍ、深さ１００μｍのピッチ１ ｍｍのデ
インプル加工を行った。A dimple process with a diameter of 300 μm, a depth of 100 μm, and a pitch of 1 mm was performed.
（比較例６）
第２図に示すように、リードフレームのタブ塩に巾５０
０μｍ、深さ１００μｍの溝加工を行った。(Comparative Example 6) As shown in Figure 2, the tab salt of the lead frame has a width of 50 mm.
A groove of 0 μm and a depth of 100 μm was formed.
（実施例５）
第４図に示すようにリードフレームのタブ裏周辺部に深
さ２５μｍ、径２０μｍ、ピッチ３００μｍの放電加工
を施し、さらに実施例１と同じ方法でタブ吊りリードの
離型処理を行った。(Example 5) As shown in Fig. 4, electric discharge machining was performed on the back side of the lead frame with a depth of 25 μm, a diameter of 20 μm, and a pitch of 300 μm, and the tab hanging lead was then released from the mold using the same method as in Example 1. I did it.
（比較例４）
リードフレームのタブ塩に放電加工を行なわず、タブ吊
りリードの離型処理も行わなかった。(Comparative Example 4) No electrical discharge machining was performed on the tab salt of the lead frame, and no mold release treatment was performed on the tab suspension lead.
（比較例５）
第１図に示すように、リードフレームのタブ裏以上のリ
ードフレームを用い、ダミー素子を搭載し、テスト用Ｓ
ＯＪパッケージを成形した。封止材には、ＣＥＬ−Ｆ〜
７５７（日立化成工業型、エポキシ樹脂封止材）を用い
、常法に従い１８０°Ｃで９０秒成形を行い、さらに１
８０°Ｃで４時間の後硬化を行った。(Comparative Example 5) As shown in Figure 1, a dummy element is mounted on a lead frame with a length larger than the back of the lead frame tab, and a test S
An OJ package was molded. The sealing material is CEL-F~
757 (Hitachi Chemical Co., Ltd. type, epoxy resin sealant), molding was performed at 180°C for 90 seconds according to the usual method, and further 1
Post-curing was carried out at 80°C for 4 hours.
耐はんだテストは、パッケージを８５’Ｃ／８５％ＲＨ
Ｍの条件で、７２時間〜１４４時間吸湿させ、２１５°
Ｃのベーパリフローを９０秒かけた後、パッケージ裏側
のクランク発生数を評価した。結果を表２に示す。Solder resistance test was performed on the package at 85'C/85%RH.
Absorb moisture for 72 to 144 hours under the conditions of 215°
After vapor reflow of C for 90 seconds, the number of crank occurrences on the back side of the package was evaluated. The results are shown in Table 2.
第
図
〔発明の効果〕
本発明の樹脂封止半導体装置は、タブ裏面に放電加工に
て微細な凹凸加工を施したリードフレームを用いること
により、吸湿した表面実装用樹脂封止半導体装置であっ
ても耐はんだ性が向上し、耐湿性の優れたものが得られ
る。Figure [Effects of the Invention] The resin-sealed semiconductor device of the present invention is a surface-mounted resin-sealed semiconductor device that absorbs moisture by using a lead frame whose back surface of the tab is processed with fine irregularities by electrical discharge machining. However, the solder resistance is improved and a product with excellent moisture resistance can be obtained.
さらに、タブ吊りリードを離型処理することにより耐は
んだ性は大幅に向上する。Furthermore, by subjecting the tab suspension lead to mold release treatment, the solder resistance is greatly improved.
第１図は、従来方式のデインプル加工を施したリードフ
レームの平面図、第２図は、従来方式の溝加工を施した
リードフレームの平面図、第３図は、実施例の放電加工
を施したリードフレームの平面図１、第４図は、実施例
の部分的に放電加工を施したリードフレームの平面図で
ある。
１、タブ ２．リードビン
３、タブ吊りピン
第２
図
第３図
○○
第４
図Fig. 1 is a plan view of a lead frame with conventional dimple processing, Fig. 2 is a plan view of a lead frame with conventional groove processing, and Fig. 3 is a plan view of a lead frame with conventional electrical discharge machining. 1 and 4 are plan views of the lead frame partially subjected to electric discharge machining according to the embodiment. 1. Tab 2. Lead bin 3, tab hanging pin 2 Figure 3 ○○ Figure 4
Claims (1)
グし、さらに金線でワイヤボンドした後、トランスファ
成形法で樹脂封止してなる半導体装置において、リード
フレームとしてタブ裏側が放電加工法にて凹凸加工が施
されたリードフレームを用いることを特徴とする樹脂封
止半導体装置。 ２、リードフレーム上にシリコン素子をダイボンディン
グし、さらに金線でワイヤボンドした後、トランスファ
成形法で樹脂封止してなる半導体装置において、リード
フレームとしてタブ裏側が放電加工法にて凹凸加工が施
され、かつタブ吊りリードが離型処理されたリードフレ
ームを用いることを特徴とする樹脂封止半導体装置。[Claims] 1. In a semiconductor device in which a silicon element is die-bonded onto a lead frame, further wire-bonded with gold wire, and then resin-sealed using a transfer molding method, the back side of the tab is processed by electrical discharge as a lead frame. 1. A resin-sealed semiconductor device characterized by using a lead frame that is textured using a method. 2. In a semiconductor device in which a silicon element is die-bonded onto a lead frame, further wire-bonded with gold wire, and then sealed with resin using a transfer molding method, the back side of the tab as a lead frame is processed with unevenness using an electric discharge machining method. What is claimed is: 1. A resin-sealed semiconductor device characterized by using a lead frame in which the tab suspension leads have been subjected to mold release treatment.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63169723A JPH0218952A (en) | 1988-07-07 | 1988-07-07 | Resin sealed semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63169723A JPH0218952A (en) | 1988-07-07 | 1988-07-07 | Resin sealed semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0218952A true JPH0218952A (en) | 1990-01-23 |
Family
ID=15891662
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63169723A Pending JPH0218952A (en) | 1988-07-07 | 1988-07-07 | Resin sealed semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0218952A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6002173A (en) * | 1991-12-20 | 1999-12-14 | Sgs-Thomson Microelectronics S.R.L. | Semiconductor device package with metal-polymer joint of controlled roughness |
-
1988
- 1988-07-07 JP JP63169723A patent/JPH0218952A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6002173A (en) * | 1991-12-20 | 1999-12-14 | Sgs-Thomson Microelectronics S.R.L. | Semiconductor device package with metal-polymer joint of controlled roughness |
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