JPH02189013A - chip type delay line - Google Patents

Abstract

PURPOSE:To attain miniaturization and high density by laminating plural strip bases and dielectric bases alternately. CONSTITUTION:The delay line is constituted by laminating a dielectric base 30-1, a strip line base 31-1, a dielectric base 30-2, a strip line base 31-2, a dielectric base 30-3 and a strip line 31-3 from the lower face side in this order. Thus, each ground pattern is connected to a conductor land 39a and both ends of conductor strip lines connected in series are connected to conductor lands 40a, 42a and the chip type delay line is used for the surface mount use. Since the plural strip line bases are laminated in this way, miniaturization and high density are attained and since most of the electric connection is implemented in incorporating each base, the manufacture efficiency is improved.

Description

[Detailed Description of the Invention] Overview Regarding chip-type delay lines used in high-frequency circuits, the purpose of this invention is to improve manufacturing efficiency, reduce size, and increase density. A plurality of IJ tube line substrates and a plurality of dielectric substrates each having a ground pattern formed on the bottom surface thereof are alternately stacked such that the bottom layer is the dielectric substrate, The above-mentioned ground patterns are interconnected through through-holes provided so as to penetrate through the main body substrate, and the above-mentioned conductor strip lines are connected in series on the side surfaces of the above-mentioned IJ tube line board and the above-mentioned dielectric substrate, and the series connection is made. Both ends of the IJ tube line and the interconnected ground pattern are connected to a conductor land provided on the lower surface of the lowermost dielectric substrate.

INDUSTRIAL APPLICATION FIELD The present invention relates to a chip-type delay line (chip-type delay line) used in high-frequency circuits, and more specifically, the present invention relates to a chip-type delay line (chip-type delay line) used in high-frequency circuits. This invention relates to a chip-type delay line formed by interposing a dielectric material having an appropriate dielectric constant such as.

For example, in optical transmission equipment that handles high bit rate signals, it may be necessary to delay the signal transmission of high frequency signals. A day line is used. This type of delay line is required to be smaller and more dense due to the recent trend towards higher density packaging. Specifically, there is a demand for a chip-type delay line that can be surface mounted and has excellent manufacturability.

Conventional technology Fig. 5 is a perspective view of a conventional delay line, Fig. 6 is a perspective view of the first board of the conventional example seen from the front and back, and Fig. 7 is a perspective view of the second board of the conventional example. . The delay line extracts the input signal after a certain period of time delay, and in the conventional example, a substrate 10.20 of alumina, glass epoxy, etc. is used, and one surface of these substrates 10.20 is coated with a thin film deposition technique or A zigzag-shaped elongated conductor strip line 1121 for signal transmission is formed using film printing/firing technology, etc., and a ground pattern 12. is formed almost entirely on the other side.
22 is formed. Two conductor strip lines 11 are formed on the first substrate 10 (FIG. 6), one end of which is connected to a conductor land 13, and the other end connected to a conductor land 15 at a position adjacent to the edge of the substrate 10. has been done. An earth lead 16 protruding from the substrate 10 is connected to the earth pattern 12 on the back surface by caulking or the like. In addition, the second substrate 20 (only the surface is shown in FIG. 7) has one slot).
An IJ tube line 21 is formed, and both ends thereof are connected to the first substrate 1.
They are respectively connected to two conductor lands 25 located at positions corresponding to the two conductor lands 15 of 0. And 2
One board 10.20 has a ground pattern 12.22 on the back side.
They are integrated by facing each other and, for example, being connected by soldering. next,
Corresponding conductor lands 15.25 of both system boards 10.20 are connected using tin-plated copper wires 17 or the like. Next, the signal lead 14
is connected to the conductor land 13 by caulking or the like, and is made to protrude from the substrate 10. Further, the ground terminal 16 is also connected to the ground pattern 12 by caulking or the like, and is caused to protrude from the substrate 10. Then, it is completed by molding with resin 18 or the like. At this time, the signal lead 13 and the ground terminal 16 are connected to the mold 1.
It stands out from 8.

Problems to be Solved by the Invention In the conventional example described above, the wiring area of the conductor strip line 11.21 is expanded by bonding the substrates 10.20 together, and the delay line having a predetermined amount of delay is made smaller and more dense. I'm trying. However, since it was necessary to solder the strip lines 11 and 21 on both sides with tin-plated copper wire 17, the number of manufacturing steps was large. On the other hand, in recent years, surface mounting technology that enables high-density mounting has developed, and in order to further miniaturize and increase the density of devices, derailleur devices are being developed as chip-type components without lead wires. It is requested that an inn be provided.

The present invention was created in view of these technical problems, and aims to provide a chip-type delay line that can be made smaller, more dense, and more efficient in manufacturing.

Means for Solving the Problems The above-mentioned technical problem consists of a plurality of stripline substrates each having a conductor stripline for signal transmission formed on the top surface and a ground pattern formed on the bottom surface, and a plurality of dielectric substrates whose bottom layer is The ground patterns are alternately laminated to form a dielectric substrate, and the ground patterns are interconnected through through holes provided to penetrate the strip line substrate and the dielectric substrate, and the conductive strip lines are connected to each other through the strip line. The substrate and the dielectric substrate are connected in series on the side surfaces thereof, and both ends of the series-connected conductor strip lines and the interconnected ground pattern are connected to a conductor land provided on the lower surface of the lowermost dielectric substrate. This problem is solved by a chip-type delay line composed of

Effect According to the configuration of the present invention, since a plurality of stripline substrates and dielectric substrates are alternately laminated, it is possible to significantly expand the area in which conductive striplines can be formed in a unit volume. This allows for smaller size and higher density. Note that the reason why the bottom layer is a dielectric substrate is that if the bottom layer is a U-tube line board, a ground pattern is formed on the bottom surface, making surface mounting virtually impossible. Because it will be. That is, in the present invention, surface mounting on a printed wiring board or the like is performed via conductive lands provided on the lower surface of the lowermost dielectric substrate.

Example Embodiments of the present invention will be described below based on the drawings.

FIG. 1 is a perspective view of a chip type delay line showing an embodiment of the present invention, and FIG. 2 is a sectional view showing a cross section of the chip type delay line at a through hole. Although FIG. 2 shows that a space is formed between each substrate, in reality, the thickness of the conductor pattern is very small, so the thickness of the conductor pattern is very small.

When they are integrated by knotting, etc., the above space almost disappears. This chip type delay line consists of a dielectric substrate 30-1, a stripline substrate 31-L, a dielectric substrate 30-2, a stripline substrate 31-2, a dielectric substrate 30-3, and an IJ tube line substrate 31 from the bottom side. -3
are laminated in this order.

FIGS. 3(a) and 3(b) show the strip line board 31.
(31-1, 2, 3>) as seen from the upper surface side and the lower surface side, respectively.The upper surface of the disk-shaped conductive substrate 33 with the through hole 34 formed in the center is coated with a thin film deposition technique, for example. Alternatively, a long and thin zigzag conductor strip line 35 for signal transmission is formed using thick film printing and firing technology, and both ends 35a and 35b of the conductor strip line 35 are connected to the dielectric substrate 33.
It extends through the sides and partially to the bottom. On the lower surface of the dielectric substrate 33, both ends 35a of the conductor strip line are provided.
, 35b, a ground pattern 36 is formed using a technique similar to the conductor strip line forming technique, and this ground pattern 36 extends partially to the top surface of the dielectric substrate 33 through the wall surface of the through hole 34. There is (3
6 a).

Figure 4(a) shows a dielectric substrate 30 (30-1, 2°3)
Figure (b) is a perspective view of the dielectric substrate 30 (30-2°3) other than the bottom dielectric substrate, as seen from the top side, and figure (C) is the bottom side of the dielectric substrate 30 (30-2°3). Lower dielectric substrate 30
It is a perspective view seen from the lower surface side of (30-1). The dielectric substrates 30-2.3 other than the bottom layer dielectric substrate have a conductor pattern 39 in a through hole 34 of the dielectric substrate 37 similar to that in the stripline substrate, with a part of the conductor pattern 39 on the upper surface of the dielectric substrate 37 and A conductive pattern 40 is formed on the side surface of the dielectric substrate 37 so that both end portions of the conductive pattern 40 partially extend to the upper and lower surfaces of the dielectric substrate 37. On the other hand, the lowermost dielectric substrate 30-1 has a conductor pattern 42 formed on the lower side of the side surface of the dielectric substrate 37, and conductor patterns 39, 4 to enable surface mounting.
0.42 to conductor lands 39a, 40a, 42a, respectively.
It is configured by connecting to.

These dielectric substrate 30 and stripline substrate 31
are laminated as follows.

First, the conductor pattern 40 of the dielectric substrate 30-1 in the lowermost layer
The stripline substrate 31-1 is stacked on the dielectric substrate 30-1 so that the ends 35a of the conductive striplines of the stripline substrate 31-1 are aligned with each other.

Next, the stripline substrate 31 is placed so that the end portion 35b of the conductive stripline of the stripline substrate 31-1 and the conductor pattern 40 of the dielectric substrate 30-2 are aligned with each other.
Dielectric substrate 30-2 is stacked on top of -1.

Next, the stripline substrate 31-2 is placed on the dielectric substrate 30-2 so that the conductive pattern 40 of the dielectric substrate 30-2 and the end 35a of the conductive strip line of the stripline substrate 31-2 match. pile up.

Next, the stripline board 31-2 is aligned so that the end portion 35b of the conductor stripline of the stripline board 31-2 and the conductor pattern 40 of the dielectric board 30-3 are aligned with each other.
Dielectric substrate 30-3 is stacked on -2.

Next, the stripline board 31-3 is placed on the dielectric board 30-3 so that the conductive pattern 40 of the dielectric board 30-3 and the end 35a of the conductive strip line of the stripline board 31-3 match. Stack.

The dielectric substrate 30 and the strip line substrate 31 are then sintered so that the above-mentioned positional relationship is maintained.
The conductor strip lines 35 of each strip line board 31 are connected in series.

Finally, the end portion 35b of the conductor strip line of the top layer strip line board 31-3 and the bottom layer dielectric board 3
The conductor pattern 42 of 0-1 is connected by the conductive part 43. In order to form the conductive portion 43, for example, a conductive paste may be applied to the side surface of each integrated substrate. In addition, like other conductive patterns, etc., a conductive pattern is formed in advance in the part where the conductive part 43 is to be formed, and when the respective substrates are integrated by sintering or the like, the conductive part 43 is automatically formed.
3 can also be formed.

If the chip type delay line is manufactured in this way, each ground pattern can be connected to the conductor land 39a, and both ends of the conductor strip lines connected in series can be connected to the conductor lands 40a, 42a. can be used for surface mounting. In this case, because multiple stripline boards are stacked together, miniaturization and high density are achieved, and most of the electrical connections can be made when integrating each board, resulting in manufacturing efficiency. will improve.

In this embodiment, three dielectric substrates 30 and three stripline substrates 31 are laminated.
The number of laminated layers can also be increased by adjusting the spacing between 3.35b.

Further, in the embodiments described so far, a disk-shaped dielectric substrate and a stripline substrate are used, but a polygonal flat dielectric substrate and a stripline substrate can also be used. In this case, for example, by forming the conductor pattern to be formed on the side surface at the apex portion of the polygon, alignment can be easily performed when stacking the substrates.

DETAILED DESCRIPTION OF THE INVENTION As described in detail, the present invention has the advantage that it is possible to provide a chip-type delay line that can be made smaller, have higher density, and improve manufacturing efficiency.

[Brief explanation of the drawing]

FIG. 1 is a perspective view of a chi-knob type delay line showing an embodiment of the present invention, FIG. 2 is a sectional view showing a cross section of the tip type delay line shown in FIG. 4 is a perspective view of the dielectric substrate shown in FIG. 1, FIG. 5 is an overall perspective view of a conventional delay line, and FIGS.
The figure is an exploded perspective view of a conventional delay line. 30... Dielectric substrate, 31... Strip line board, 4... Through hole, 5... Conductor strip line, 6... Earth pattern, Qa. a...Conductor land.

Claims (1)

[Claims] A plurality of stripline substrates (31) having conductor striplines (35) for signal transmission formed on the upper surface and a ground pattern (36) formed on the lower surface, and a plurality of dielectric substrates (30). are stacked alternately so that the bottom layer is the dielectric substrate (30), and the ground is connected to the ground via a through hole (34) provided to penetrate the strip line substrate (31) and the dielectric substrate (30). The patterns (36) are interconnected, the conductor strip lines (35) are connected in series on the side surfaces of the strip line substrate (31) and the dielectric substrate (30), and the series connected conductor strip lines are connected to each other in series. (35) and the interconnected ground pattern (36) are connected to conductor lands (39a, 40a, 42a) provided on the lower surface of the lowermost dielectric substrate (30). type delay line.